mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-03 13:51:33 +01:00
96 lines
5.2 KiB
Python
96 lines
5.2 KiB
Python
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.multi_bit_circuits.adders import (
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UnsignedCarryLookaheadAdder,
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UnsignedPGRippleCarryAdder,
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UnsignedRippleCarryAdder,
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UnsignedCarrySkipAdder,
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)
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from ariths_gen.multi_bit_circuits.approximate_multipliers import (
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UnsignedTruncatedArrayMultiplier,
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UnsignedTruncatedCarrySaveMultiplier,
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UnsignedBrokenArrayMultiplier,
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UnsignedBrokenCarrySaveMultiplier
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)
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from ariths_gen.pdk import *
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import os
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from itertools import product
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def open_file_with_folder(filename, mode):
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d = os.path.dirname(filename)
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if d:
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os.makedirs(d, exist_ok=True)
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return open(filename, mode)
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if __name__ == "__main__":
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# Optional use HA and FA technology from pdk45 library
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# set_pdk45_library()
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# 8-bit unsigned BAMs
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root_path = "test_circuits/ax"
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adders = {UnsignedCarryLookaheadAdder: "cla", UnsignedPGRippleCarryAdder: "pg_rca", UnsignedRippleCarryAdder: "rca", UnsignedCarrySkipAdder: "cska"}
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i = 0
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for h in range(0, 8):
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# v <= (8-1) + (8-2)
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for v in range(h, 13):
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i += 1
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N = 8
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a = Bus(prefix="a", N=N)
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b = Bus(prefix="b", N=N)
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for bam in [UnsignedBrokenArrayMultiplier, UnsignedBrokenCarrySaveMultiplier]:
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if bam == UnsignedBrokenCarrySaveMultiplier:
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for add_type in adders.keys():
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flat_bam = bam(a, b, name=f"f_u_csabam{N}_{adders[add_type]}_h{h}_v{v}", horizontal_cut=h, vertical_cut=v, unsigned_adder_class_name=add_type)
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hier_bam = bam(a, b, name=f"h_u_csabam{N}_{adders[add_type]}_h{h}_v{v}", horizontal_cut=h, vertical_cut=v, unsigned_adder_class_name=add_type)
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flat_bam.get_c_code_flat(open_file_with_folder(os.path.join(root_path, f"BAM/C/flat/f_u_csabam{N}_{adders[add_type]}_h{h}_v{v}.c"), "w"))
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flat_bam.get_v_code_flat(open_file_with_folder(os.path.join(root_path, f"BAM/Verilog/flat/f_u_csabam{N}_{adders[add_type]}_h{h}_v{v}.v"), "w"))
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hier_bam.get_c_code_hier(open_file_with_folder(os.path.join(root_path, f"BAM/C/hier/h_u_csabam{N}_{adders[add_type]}_h{h}_v{v}.c"), "w"))
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hier_bam.get_v_code_hier(open_file_with_folder(os.path.join(root_path, f"BAM/Verilog/hier/h_u_csabam{N}_{adders[add_type]}_h{h}_v{v}.v"), "w"))
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else:
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flat_bam = bam(a, b, name=f"f_u_arrbam{N}_h{h}_v{v}", horizontal_cut=h, vertical_cut=v)
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hier_bam = bam(a, b, name=f"h_u_arrbam{N}_h{h}_v{v}", horizontal_cut=h, vertical_cut=v)
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flat_bam.get_c_code_flat(open_file_with_folder(os.path.join(root_path, f"BAM/C/flat/f_u_arrbam{N}_h{h}_v{v}.c"), "w"))
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flat_bam.get_v_code_flat(open_file_with_folder(os.path.join(root_path, f"BAM/Verilog/flat/f_u_arrbam{N}_h{h}_v{v}.v"), "w"))
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hier_bam.get_c_code_hier(open_file_with_folder(os.path.join(root_path, f"BAM/C/hier/h_u_arrbam{N}_h{h}_v{v}.c"), "w"))
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hier_bam.get_v_code_hier(open_file_with_folder(os.path.join(root_path, f"BAM/Verilog/hier/h_u_arrbam{N}_h{h}_v{v}.v"), "w"))
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# 8-bit unsigned TMs
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for i in range(0, 8):
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N = 8
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a = Bus(prefix="a", N=N)
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b = Bus(prefix="b", N=N)
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for tm in [UnsignedTruncatedArrayMultiplier, UnsignedTruncatedCarrySaveMultiplier]:
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if tm == UnsignedTruncatedCarrySaveMultiplier:
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for add_type in adders.keys():
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flat_tm = tm(a, b, name=f"f_u_csatm{N}_{adders[add_type]}_k{i}", truncation_cut=i, unsigned_adder_class_name=add_type)
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hier_tm = tm(a, b, name=f"h_u_csatm{N}_{adders[add_type]}_k{i}", truncation_cut=i, unsigned_adder_class_name=add_type)
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flat_tm.get_c_code_flat(open_file_with_folder(os.path.join(root_path, f"TM/C/flat/f_u_csatm{N}_{adders[add_type]}_k{i}.c"), "w"))
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flat_tm.get_v_code_flat(open_file_with_folder(os.path.join(root_path, f"TM/Verilog/flat/f_u_csatm{N}_{adders[add_type]}_k{i}.v"), "w"))
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hier_tm.get_c_code_hier(open_file_with_folder(os.path.join(root_path, f"TM/C/hier/h_u_csatm{N}_{adders[add_type]}_k{i}.c"), "w"))
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hier_tm.get_v_code_hier(open_file_with_folder(os.path.join(root_path, f"TM/Verilog/hier/h_u_csatm{N}_{adders[add_type]}_k{i}.v"), "w"))
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else:
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flat_tm = tm(a, b, name=f"f_u_arrtm{N}_k{i}", truncation_cut=i)
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hier_tm = tm(a, b, name=f"h_u_arrtm{N}_k{i}", truncation_cut=i)
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flat_tm.get_c_code_flat(open_file_with_folder(os.path.join(root_path, f"TM/C/flat/f_u_arrtm{N}_k{i}.c"), "w"))
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flat_tm.get_v_code_flat(open_file_with_folder(os.path.join(root_path, f"TM/Verilog/flat/f_u_arrtm{N}_k{i}.v"), "w"))
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hier_tm.get_c_code_hier(open_file_with_folder(os.path.join(root_path, f"TM/C/hier/h_u_arrtm{N}_k{i}.c"), "w"))
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hier_tm.get_v_code_hier(open_file_with_folder(os.path.join(root_path, f"TM/Verilog/hier/h_u_arrtm{N}_k{i}.v"), "w"))
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