4 Commits

Author SHA1 Message Date
Jan Klhůfek
6bbe9eb253
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. (#18) 2023-02-24 13:34:35 +01:00
Jan Klhůfek
56c86c13ca
New multipliers (#13)
* #10 CGP Circuits as inputs (#11)

* CGP Circuits as inputs

* #10 support of signed output in general circuit

* input as output works

* output connected to input (c)

* automated verilog testing

* output rename

* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.

* Typos fix and code cleanup.

* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

* Updated automated testing scripts.

* Small bugfix in python code generation (I initially thought this line is useless).

* Updated generated circuits folder.

Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Vojta Mrazek
aeacd72d24 Readme, axmults in workflow 2022-01-13 16:10:51 +01:00
Honza
13c085f169 Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers. 2022-01-13 13:11:24 +01:00