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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
17 lines
175 B
Plaintext
17 lines
175 B
Plaintext
__pycache__/
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.vscode
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test.py
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Makefile
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*__pycache__*
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build/
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dist/
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test_circuits/
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tests/tmp.exe
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tests/tmp.c
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tests/tmp.verilog
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html/
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*.egg-info
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.pytest_cache
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.ipynb_checkpoints |