12 Commits

Author	SHA1	Message	Date
Jan Klhůfek	56c86c13ca	New multipliers (#13) ... * #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>	2022-04-17 16:00:00 +02:00
Vojta Mrazek	8c0f24cd2d	General MAC circuit	2021-09-06 12:52:13 +02:00
Vojta Mrazek	c6e542231c	CGP tests; reversed output order	2021-06-23 13:43:58 +02:00
Vojta Mrazek	cfe0ca6b4b	Automated testing, preparing the package for publishing (#1) ... * automated pandoc deploy * automated pandoc deploy (v2) * automated pandoc deploy (v2) * automated pdoc deploy (v3) * automated pdoc deploy (v4) * automated pdoc deploy (v5) * automated pdoc deploy (v5) * prepare for python project * 8-bit testing * 8-bit testing * 8-bit testing (v2) * 8-bit testing (v3) * update of sign	2021-06-18 12:38:11 +02:00
honzastor	e5f2dd893a	Fixed proper generated circuits names (mistakenly named cska as csa).	2021-04-28 21:39:58 +02:00
honzastor	7a6d5213f8	Updating gitignore	2021-03-30 16:15:54 +02:00
honzastor	ef5dc80382	Implemented generation to flat Verilog format and improved some other minor bits of code.	2021-02-16 10:41:29 +01:00
honzastor	f1142b51d9	Implemented basic tests for generated flat C code circuits.	2021-02-09 21:02:50 +01:00
honzastor	4f8de30911	Implementation organized into multiple scripts. Added basic generation example call. Adjusting code to PEP8 standard (except long lines).)	2021-01-18 19:29:31 +01:00
root	7fba0f0aea	Added ripple carry adder and started work on C code generation.	2020-12-10 22:37:10 +01:00
root	99d23be531	Implemented logic for wire, bus, logic gates, and 1-bit adders.	2020-12-10 03:52:00 +01:00
root	a3ba1fca58	Implemented logic for basic components such as logic gates, bus and wire. From these components were built primary low level 1-bit circuits (half, full adder).	2020-12-10 03:45:46 +01:00