3 Commits

Author	SHA1	Message	Date
honzastor	0f66c5a2e9	Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.	2021-04-23 11:49:24 +02:00
honzastor	670ba45ee5	Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.	2021-04-23 02:44:14 +02:00
honzastor	f57a633f6c	Renamed generated circuits folders.	2021-04-22 20:56:38 +02:00