Honza
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d9b56e8a00
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Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm.
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2022-01-06 19:23:56 +01:00 |
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Honza
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9aa0fb1858
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Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work.
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2022-01-06 06:39:58 +01:00 |
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Honza
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f830029c54
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Added truncated multiplier circuit implementation. Needs testing.
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2022-01-04 03:13:21 +01:00 |
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honzastor
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f582ee729e
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Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations.
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2021-10-25 01:11:34 +02:00 |
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honzastor
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5d41997560
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Added assertion checks for the same input bus lengths when initializing arithmetic circuits.
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2021-10-24 18:48:00 +02:00 |
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honzastor
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d41c5f3c94
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Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
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2021-10-10 22:15:13 +02:00 |
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honzastor
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16c1757bc3
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Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
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2021-10-09 23:45:54 +02:00 |
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Vojta Mrazek
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152a6b1583
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Python eval (#4)
* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
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2021-10-04 11:58:28 +02:00 |
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Vojta Mrazek
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995107eecc
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Removing of file closing
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2021-09-23 08:50:18 +02:00 |
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honzastor
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eba0a7a938
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Made some minor changes concerning proper exportation of multiplier circuits.
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2021-09-09 13:57:36 +02:00 |
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honzastor
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e16de78c2b
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Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
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2021-09-07 17:39:39 +02:00 |
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Vojta Mrazek
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8c0f24cd2d
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General MAC circuit
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2021-09-06 12:52:13 +02:00 |
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Vojta Mrazek
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0a487ee699
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CGP format
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2021-06-23 14:08:49 +02:00 |
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Vojta Mrazek
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c6e542231c
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CGP tests; reversed output order
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2021-06-23 13:43:58 +02:00 |
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honzastor
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0f66c5a2e9
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Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
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2021-04-23 11:49:24 +02:00 |
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honzastor
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670ba45ee5
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Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
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2021-04-23 02:44:14 +02:00 |
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honzastor
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8e950fc51f
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Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
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2021-04-21 11:33:07 +02:00 |
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