6 Commits

Author SHA1 Message Date
Jan Klhůfek
56c86c13ca
New multipliers (#13)
* #10 CGP Circuits as inputs (#11)

* CGP Circuits as inputs

* #10 support of signed output in general circuit

* input as output works

* output connected to input (c)

* automated verilog testing

* output rename

* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.

* Typos fix and code cleanup.

* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

* Updated automated testing scripts.

* Small bugfix in python code generation (I initially thought this line is useless).

* Updated generated circuits folder.

Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
honzastor
50c33d27d2 Updated generated circuits. 2021-04-28 21:47:33 +02:00
honzastor
e5f2dd893a Fixed proper generated circuits names (mistakenly named cska as csa). 2021-04-28 21:39:58 +02:00
honzastor
0f66c5a2e9 Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated. 2021-04-23 11:49:24 +02:00
honzastor
670ba45ee5 Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup. 2021-04-23 02:44:14 +02:00
honzastor
f57a633f6c Renamed generated circuits folders. 2021-04-22 20:56:38 +02:00