1402 lines
64 KiB
Plaintext
1402 lines
64 KiB
Plaintext
.model h_u_cla8
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7]
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.outputs out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8]
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.names a[0] a_0
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1 1
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.names a[1] a_1
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1 1
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.names a[2] a_2
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1 1
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.names a[3] a_3
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1 1
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.names a[4] a_4
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1 1
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.names a[5] a_5
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1 1
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.names a[6] a_6
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1 1
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.names a[7] a_7
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1 1
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.names b[0] b_0
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1 1
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.names b[1] b_1
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1 1
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.names b[2] b_2
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1 1
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.names b[3] b_3
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1 1
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.names b[4] b_4
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1 1
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.names b[5] b_5
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1 1
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.names b[6] b_6
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1 1
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.names b[7] b_7
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1 1
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.names a_0 constant_wire_value_0_a_0
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1 1
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.names b_0 constant_wire_value_0_b_0
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1 1
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.subckt constant_wire_value_0 a=constant_wire_value_0_a_0 b=constant_wire_value_0_b_0 constant_wire_0=constant_wire_0
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.names a_0 h_u_cla8_pg_logic0_a_0
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1 1
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.names b_0 h_u_cla8_pg_logic0_b_0
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1 1
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.subckt pg_logic a=h_u_cla8_pg_logic0_a_0 b=h_u_cla8_pg_logic0_b_0 pg_logic_y0=h_u_cla8_pg_logic0_y0 pg_logic_y1=h_u_cla8_pg_logic0_y1 pg_logic_y2=h_u_cla8_pg_logic0_y2
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.names h_u_cla8_pg_logic0_y2 h_u_cla8_xor0_h_u_cla8_pg_logic0_y2
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1 1
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.names constant_wire_0 h_u_cla8_xor0_constant_wire_0
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1 1
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.subckt xor_gate _a=h_u_cla8_xor0_h_u_cla8_pg_logic0_y2 _b=h_u_cla8_xor0_constant_wire_0 _y0=h_u_cla8_xor0_y0
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.names h_u_cla8_pg_logic0_y0 h_u_cla8_and0_h_u_cla8_pg_logic0_y0
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1 1
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.names constant_wire_0 h_u_cla8_and0_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and0_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and0_constant_wire_0 _y0=h_u_cla8_and0_y0
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.names h_u_cla8_pg_logic0_y1 h_u_cla8_or0_h_u_cla8_pg_logic0_y1
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1 1
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.names h_u_cla8_and0_y0 h_u_cla8_or0_h_u_cla8_and0_y0
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1 1
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.subckt or_gate _a=h_u_cla8_or0_h_u_cla8_pg_logic0_y1 _b=h_u_cla8_or0_h_u_cla8_and0_y0 _y0=h_u_cla8_or0_y0
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.names a_1 h_u_cla8_pg_logic1_a_1
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1 1
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.names b_1 h_u_cla8_pg_logic1_b_1
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1 1
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.subckt pg_logic a=h_u_cla8_pg_logic1_a_1 b=h_u_cla8_pg_logic1_b_1 pg_logic_y0=h_u_cla8_pg_logic1_y0 pg_logic_y1=h_u_cla8_pg_logic1_y1 pg_logic_y2=h_u_cla8_pg_logic1_y2
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.names h_u_cla8_pg_logic1_y2 h_u_cla8_xor1_h_u_cla8_pg_logic1_y2
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1 1
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.names h_u_cla8_or0_y0 h_u_cla8_xor1_h_u_cla8_or0_y0
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1 1
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.subckt xor_gate _a=h_u_cla8_xor1_h_u_cla8_pg_logic1_y2 _b=h_u_cla8_xor1_h_u_cla8_or0_y0 _y0=h_u_cla8_xor1_y0
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.names h_u_cla8_pg_logic0_y0 h_u_cla8_and1_h_u_cla8_pg_logic0_y0
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1 1
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.names constant_wire_0 h_u_cla8_and1_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and1_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and1_constant_wire_0 _y0=h_u_cla8_and1_y0
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.names h_u_cla8_pg_logic1_y0 h_u_cla8_and2_h_u_cla8_pg_logic1_y0
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1 1
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.names constant_wire_0 h_u_cla8_and2_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and2_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and2_constant_wire_0 _y0=h_u_cla8_and2_y0
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.names h_u_cla8_and2_y0 h_u_cla8_and3_h_u_cla8_and2_y0
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1 1
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.names h_u_cla8_and1_y0 h_u_cla8_and3_h_u_cla8_and1_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and3_h_u_cla8_and2_y0 _b=h_u_cla8_and3_h_u_cla8_and1_y0 _y0=h_u_cla8_and3_y0
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.names h_u_cla8_pg_logic1_y0 h_u_cla8_and4_h_u_cla8_pg_logic1_y0
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1 1
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.names h_u_cla8_pg_logic0_y1 h_u_cla8_and4_h_u_cla8_pg_logic0_y1
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1 1
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.subckt and_gate _a=h_u_cla8_and4_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and4_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and4_y0
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.names h_u_cla8_and4_y0 h_u_cla8_or1_h_u_cla8_and4_y0
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1 1
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.names h_u_cla8_and3_y0 h_u_cla8_or1_h_u_cla8_and3_y0
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1 1
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.subckt or_gate _a=h_u_cla8_or1_h_u_cla8_and4_y0 _b=h_u_cla8_or1_h_u_cla8_and3_y0 _y0=h_u_cla8_or1_y0
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.names h_u_cla8_pg_logic1_y1 h_u_cla8_or2_h_u_cla8_pg_logic1_y1
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1 1
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.names h_u_cla8_or1_y0 h_u_cla8_or2_h_u_cla8_or1_y0
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1 1
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.subckt or_gate _a=h_u_cla8_or2_h_u_cla8_pg_logic1_y1 _b=h_u_cla8_or2_h_u_cla8_or1_y0 _y0=h_u_cla8_or2_y0
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.names a_2 h_u_cla8_pg_logic2_a_2
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1 1
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.names b_2 h_u_cla8_pg_logic2_b_2
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1 1
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.subckt pg_logic a=h_u_cla8_pg_logic2_a_2 b=h_u_cla8_pg_logic2_b_2 pg_logic_y0=h_u_cla8_pg_logic2_y0 pg_logic_y1=h_u_cla8_pg_logic2_y1 pg_logic_y2=h_u_cla8_pg_logic2_y2
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.names h_u_cla8_pg_logic2_y2 h_u_cla8_xor2_h_u_cla8_pg_logic2_y2
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1 1
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.names h_u_cla8_or2_y0 h_u_cla8_xor2_h_u_cla8_or2_y0
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1 1
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.subckt xor_gate _a=h_u_cla8_xor2_h_u_cla8_pg_logic2_y2 _b=h_u_cla8_xor2_h_u_cla8_or2_y0 _y0=h_u_cla8_xor2_y0
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.names h_u_cla8_pg_logic0_y0 h_u_cla8_and5_h_u_cla8_pg_logic0_y0
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1 1
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.names constant_wire_0 h_u_cla8_and5_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and5_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and5_constant_wire_0 _y0=h_u_cla8_and5_y0
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.names h_u_cla8_pg_logic1_y0 h_u_cla8_and6_h_u_cla8_pg_logic1_y0
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1 1
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.names constant_wire_0 h_u_cla8_and6_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and6_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and6_constant_wire_0 _y0=h_u_cla8_and6_y0
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.names h_u_cla8_and6_y0 h_u_cla8_and7_h_u_cla8_and6_y0
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1 1
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.names h_u_cla8_and5_y0 h_u_cla8_and7_h_u_cla8_and5_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and7_h_u_cla8_and6_y0 _b=h_u_cla8_and7_h_u_cla8_and5_y0 _y0=h_u_cla8_and7_y0
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.names h_u_cla8_pg_logic2_y0 h_u_cla8_and8_h_u_cla8_pg_logic2_y0
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1 1
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.names constant_wire_0 h_u_cla8_and8_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and8_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and8_constant_wire_0 _y0=h_u_cla8_and8_y0
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.names h_u_cla8_and8_y0 h_u_cla8_and9_h_u_cla8_and8_y0
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1 1
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.names h_u_cla8_and7_y0 h_u_cla8_and9_h_u_cla8_and7_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and9_h_u_cla8_and8_y0 _b=h_u_cla8_and9_h_u_cla8_and7_y0 _y0=h_u_cla8_and9_y0
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.names h_u_cla8_pg_logic1_y0 h_u_cla8_and10_h_u_cla8_pg_logic1_y0
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1 1
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.names h_u_cla8_pg_logic0_y1 h_u_cla8_and10_h_u_cla8_pg_logic0_y1
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1 1
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.subckt and_gate _a=h_u_cla8_and10_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and10_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and10_y0
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.names h_u_cla8_pg_logic2_y0 h_u_cla8_and11_h_u_cla8_pg_logic2_y0
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1 1
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.names h_u_cla8_pg_logic0_y1 h_u_cla8_and11_h_u_cla8_pg_logic0_y1
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1 1
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.subckt and_gate _a=h_u_cla8_and11_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and11_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and11_y0
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.names h_u_cla8_and11_y0 h_u_cla8_and12_h_u_cla8_and11_y0
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1 1
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.names h_u_cla8_and10_y0 h_u_cla8_and12_h_u_cla8_and10_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and12_h_u_cla8_and11_y0 _b=h_u_cla8_and12_h_u_cla8_and10_y0 _y0=h_u_cla8_and12_y0
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.names h_u_cla8_pg_logic2_y0 h_u_cla8_and13_h_u_cla8_pg_logic2_y0
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1 1
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.names h_u_cla8_pg_logic1_y1 h_u_cla8_and13_h_u_cla8_pg_logic1_y1
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1 1
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.subckt and_gate _a=h_u_cla8_and13_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and13_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and13_y0
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.names h_u_cla8_and13_y0 h_u_cla8_or3_h_u_cla8_and13_y0
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1 1
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.names h_u_cla8_and9_y0 h_u_cla8_or3_h_u_cla8_and9_y0
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1 1
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.subckt or_gate _a=h_u_cla8_or3_h_u_cla8_and13_y0 _b=h_u_cla8_or3_h_u_cla8_and9_y0 _y0=h_u_cla8_or3_y0
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.names h_u_cla8_or3_y0 h_u_cla8_or4_h_u_cla8_or3_y0
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1 1
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.names h_u_cla8_and12_y0 h_u_cla8_or4_h_u_cla8_and12_y0
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1 1
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.subckt or_gate _a=h_u_cla8_or4_h_u_cla8_or3_y0 _b=h_u_cla8_or4_h_u_cla8_and12_y0 _y0=h_u_cla8_or4_y0
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.names h_u_cla8_pg_logic2_y1 h_u_cla8_or5_h_u_cla8_pg_logic2_y1
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1 1
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.names h_u_cla8_or4_y0 h_u_cla8_or5_h_u_cla8_or4_y0
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1 1
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.subckt or_gate _a=h_u_cla8_or5_h_u_cla8_pg_logic2_y1 _b=h_u_cla8_or5_h_u_cla8_or4_y0 _y0=h_u_cla8_or5_y0
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.names a_3 h_u_cla8_pg_logic3_a_3
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1 1
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.names b_3 h_u_cla8_pg_logic3_b_3
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1 1
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.subckt pg_logic a=h_u_cla8_pg_logic3_a_3 b=h_u_cla8_pg_logic3_b_3 pg_logic_y0=h_u_cla8_pg_logic3_y0 pg_logic_y1=h_u_cla8_pg_logic3_y1 pg_logic_y2=h_u_cla8_pg_logic3_y2
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.names h_u_cla8_pg_logic3_y2 h_u_cla8_xor3_h_u_cla8_pg_logic3_y2
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1 1
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.names h_u_cla8_or5_y0 h_u_cla8_xor3_h_u_cla8_or5_y0
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1 1
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.subckt xor_gate _a=h_u_cla8_xor3_h_u_cla8_pg_logic3_y2 _b=h_u_cla8_xor3_h_u_cla8_or5_y0 _y0=h_u_cla8_xor3_y0
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.names h_u_cla8_pg_logic0_y0 h_u_cla8_and14_h_u_cla8_pg_logic0_y0
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1 1
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.names constant_wire_0 h_u_cla8_and14_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and14_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and14_constant_wire_0 _y0=h_u_cla8_and14_y0
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.names h_u_cla8_pg_logic1_y0 h_u_cla8_and15_h_u_cla8_pg_logic1_y0
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1 1
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.names constant_wire_0 h_u_cla8_and15_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and15_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and15_constant_wire_0 _y0=h_u_cla8_and15_y0
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.names h_u_cla8_and15_y0 h_u_cla8_and16_h_u_cla8_and15_y0
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1 1
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.names h_u_cla8_and14_y0 h_u_cla8_and16_h_u_cla8_and14_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and16_h_u_cla8_and15_y0 _b=h_u_cla8_and16_h_u_cla8_and14_y0 _y0=h_u_cla8_and16_y0
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.names h_u_cla8_pg_logic2_y0 h_u_cla8_and17_h_u_cla8_pg_logic2_y0
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1 1
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.names constant_wire_0 h_u_cla8_and17_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and17_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and17_constant_wire_0 _y0=h_u_cla8_and17_y0
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.names h_u_cla8_and17_y0 h_u_cla8_and18_h_u_cla8_and17_y0
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1 1
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.names h_u_cla8_and16_y0 h_u_cla8_and18_h_u_cla8_and16_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and18_h_u_cla8_and17_y0 _b=h_u_cla8_and18_h_u_cla8_and16_y0 _y0=h_u_cla8_and18_y0
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.names h_u_cla8_pg_logic3_y0 h_u_cla8_and19_h_u_cla8_pg_logic3_y0
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1 1
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.names constant_wire_0 h_u_cla8_and19_constant_wire_0
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1 1
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.subckt and_gate _a=h_u_cla8_and19_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and19_constant_wire_0 _y0=h_u_cla8_and19_y0
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.names h_u_cla8_and19_y0 h_u_cla8_and20_h_u_cla8_and19_y0
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1 1
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.names h_u_cla8_and18_y0 h_u_cla8_and20_h_u_cla8_and18_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and20_h_u_cla8_and19_y0 _b=h_u_cla8_and20_h_u_cla8_and18_y0 _y0=h_u_cla8_and20_y0
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.names h_u_cla8_pg_logic1_y0 h_u_cla8_and21_h_u_cla8_pg_logic1_y0
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1 1
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.names h_u_cla8_pg_logic0_y1 h_u_cla8_and21_h_u_cla8_pg_logic0_y1
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1 1
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.subckt and_gate _a=h_u_cla8_and21_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and21_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and21_y0
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.names h_u_cla8_pg_logic2_y0 h_u_cla8_and22_h_u_cla8_pg_logic2_y0
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1 1
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.names h_u_cla8_pg_logic0_y1 h_u_cla8_and22_h_u_cla8_pg_logic0_y1
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1 1
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.subckt and_gate _a=h_u_cla8_and22_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and22_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and22_y0
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.names h_u_cla8_and22_y0 h_u_cla8_and23_h_u_cla8_and22_y0
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1 1
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.names h_u_cla8_and21_y0 h_u_cla8_and23_h_u_cla8_and21_y0
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1 1
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.subckt and_gate _a=h_u_cla8_and23_h_u_cla8_and22_y0 _b=h_u_cla8_and23_h_u_cla8_and21_y0 _y0=h_u_cla8_and23_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and24_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and24_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and24_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and24_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and24_y0
|
|
.names h_u_cla8_and24_y0 h_u_cla8_and25_h_u_cla8_and24_y0
|
|
1 1
|
|
.names h_u_cla8_and23_y0 h_u_cla8_and25_h_u_cla8_and23_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and25_h_u_cla8_and24_y0 _b=h_u_cla8_and25_h_u_cla8_and23_y0 _y0=h_u_cla8_and25_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and26_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and26_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and26_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and26_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and26_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and27_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and27_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and27_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and27_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and27_y0
|
|
.names h_u_cla8_and27_y0 h_u_cla8_and28_h_u_cla8_and27_y0
|
|
1 1
|
|
.names h_u_cla8_and26_y0 h_u_cla8_and28_h_u_cla8_and26_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and28_h_u_cla8_and27_y0 _b=h_u_cla8_and28_h_u_cla8_and26_y0 _y0=h_u_cla8_and28_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and29_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and29_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and29_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and29_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and29_y0
|
|
.names h_u_cla8_and29_y0 h_u_cla8_or6_h_u_cla8_and29_y0
|
|
1 1
|
|
.names h_u_cla8_and20_y0 h_u_cla8_or6_h_u_cla8_and20_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or6_h_u_cla8_and29_y0 _b=h_u_cla8_or6_h_u_cla8_and20_y0 _y0=h_u_cla8_or6_y0
|
|
.names h_u_cla8_or6_y0 h_u_cla8_or7_h_u_cla8_or6_y0
|
|
1 1
|
|
.names h_u_cla8_and25_y0 h_u_cla8_or7_h_u_cla8_and25_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or7_h_u_cla8_or6_y0 _b=h_u_cla8_or7_h_u_cla8_and25_y0 _y0=h_u_cla8_or7_y0
|
|
.names h_u_cla8_or7_y0 h_u_cla8_or8_h_u_cla8_or7_y0
|
|
1 1
|
|
.names h_u_cla8_and28_y0 h_u_cla8_or8_h_u_cla8_and28_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or8_h_u_cla8_or7_y0 _b=h_u_cla8_or8_h_u_cla8_and28_y0 _y0=h_u_cla8_or8_y0
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_or9_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.names h_u_cla8_or8_y0 h_u_cla8_or9_h_u_cla8_or8_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or9_h_u_cla8_pg_logic3_y1 _b=h_u_cla8_or9_h_u_cla8_or8_y0 _y0=h_u_cla8_or9_y0
|
|
.names a_4 h_u_cla8_pg_logic4_a_4
|
|
1 1
|
|
.names b_4 h_u_cla8_pg_logic4_b_4
|
|
1 1
|
|
.subckt pg_logic a=h_u_cla8_pg_logic4_a_4 b=h_u_cla8_pg_logic4_b_4 pg_logic_y0=h_u_cla8_pg_logic4_y0 pg_logic_y1=h_u_cla8_pg_logic4_y1 pg_logic_y2=h_u_cla8_pg_logic4_y2
|
|
.names h_u_cla8_pg_logic4_y2 h_u_cla8_xor4_h_u_cla8_pg_logic4_y2
|
|
1 1
|
|
.names h_u_cla8_or9_y0 h_u_cla8_xor4_h_u_cla8_or9_y0
|
|
1 1
|
|
.subckt xor_gate _a=h_u_cla8_xor4_h_u_cla8_pg_logic4_y2 _b=h_u_cla8_xor4_h_u_cla8_or9_y0 _y0=h_u_cla8_xor4_y0
|
|
.names h_u_cla8_pg_logic0_y0 h_u_cla8_and30_h_u_cla8_pg_logic0_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and30_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and30_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and30_constant_wire_0 _y0=h_u_cla8_and30_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and31_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and31_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and31_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and31_constant_wire_0 _y0=h_u_cla8_and31_y0
|
|
.names h_u_cla8_and31_y0 h_u_cla8_and32_h_u_cla8_and31_y0
|
|
1 1
|
|
.names h_u_cla8_and30_y0 h_u_cla8_and32_h_u_cla8_and30_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and32_h_u_cla8_and31_y0 _b=h_u_cla8_and32_h_u_cla8_and30_y0 _y0=h_u_cla8_and32_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and33_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and33_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and33_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and33_constant_wire_0 _y0=h_u_cla8_and33_y0
|
|
.names h_u_cla8_and33_y0 h_u_cla8_and34_h_u_cla8_and33_y0
|
|
1 1
|
|
.names h_u_cla8_and32_y0 h_u_cla8_and34_h_u_cla8_and32_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and34_h_u_cla8_and33_y0 _b=h_u_cla8_and34_h_u_cla8_and32_y0 _y0=h_u_cla8_and34_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and35_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and35_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and35_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and35_constant_wire_0 _y0=h_u_cla8_and35_y0
|
|
.names h_u_cla8_and35_y0 h_u_cla8_and36_h_u_cla8_and35_y0
|
|
1 1
|
|
.names h_u_cla8_and34_y0 h_u_cla8_and36_h_u_cla8_and34_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and36_h_u_cla8_and35_y0 _b=h_u_cla8_and36_h_u_cla8_and34_y0 _y0=h_u_cla8_and36_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and37_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and37_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and37_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and37_constant_wire_0 _y0=h_u_cla8_and37_y0
|
|
.names h_u_cla8_and37_y0 h_u_cla8_and38_h_u_cla8_and37_y0
|
|
1 1
|
|
.names h_u_cla8_and36_y0 h_u_cla8_and38_h_u_cla8_and36_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and38_h_u_cla8_and37_y0 _b=h_u_cla8_and38_h_u_cla8_and36_y0 _y0=h_u_cla8_and38_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and39_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and39_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and39_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and39_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and39_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and40_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and40_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and40_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and40_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and40_y0
|
|
.names h_u_cla8_and40_y0 h_u_cla8_and41_h_u_cla8_and40_y0
|
|
1 1
|
|
.names h_u_cla8_and39_y0 h_u_cla8_and41_h_u_cla8_and39_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and41_h_u_cla8_and40_y0 _b=h_u_cla8_and41_h_u_cla8_and39_y0 _y0=h_u_cla8_and41_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and42_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and42_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and42_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and42_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and42_y0
|
|
.names h_u_cla8_and42_y0 h_u_cla8_and43_h_u_cla8_and42_y0
|
|
1 1
|
|
.names h_u_cla8_and41_y0 h_u_cla8_and43_h_u_cla8_and41_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and43_h_u_cla8_and42_y0 _b=h_u_cla8_and43_h_u_cla8_and41_y0 _y0=h_u_cla8_and43_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and44_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and44_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and44_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and44_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and44_y0
|
|
.names h_u_cla8_and44_y0 h_u_cla8_and45_h_u_cla8_and44_y0
|
|
1 1
|
|
.names h_u_cla8_and43_y0 h_u_cla8_and45_h_u_cla8_and43_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and45_h_u_cla8_and44_y0 _b=h_u_cla8_and45_h_u_cla8_and43_y0 _y0=h_u_cla8_and45_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and46_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and46_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and46_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and46_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and46_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and47_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and47_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and47_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and47_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and47_y0
|
|
.names h_u_cla8_and47_y0 h_u_cla8_and48_h_u_cla8_and47_y0
|
|
1 1
|
|
.names h_u_cla8_and46_y0 h_u_cla8_and48_h_u_cla8_and46_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and48_h_u_cla8_and47_y0 _b=h_u_cla8_and48_h_u_cla8_and46_y0 _y0=h_u_cla8_and48_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and49_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and49_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and49_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and49_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and49_y0
|
|
.names h_u_cla8_and49_y0 h_u_cla8_and50_h_u_cla8_and49_y0
|
|
1 1
|
|
.names h_u_cla8_and48_y0 h_u_cla8_and50_h_u_cla8_and48_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and50_h_u_cla8_and49_y0 _b=h_u_cla8_and50_h_u_cla8_and48_y0 _y0=h_u_cla8_and50_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and51_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and51_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and51_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and51_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and51_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and52_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and52_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and52_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and52_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and52_y0
|
|
.names h_u_cla8_and52_y0 h_u_cla8_and53_h_u_cla8_and52_y0
|
|
1 1
|
|
.names h_u_cla8_and51_y0 h_u_cla8_and53_h_u_cla8_and51_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and53_h_u_cla8_and52_y0 _b=h_u_cla8_and53_h_u_cla8_and51_y0 _y0=h_u_cla8_and53_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and54_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and54_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and54_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and54_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and54_y0
|
|
.names h_u_cla8_and54_y0 h_u_cla8_or10_h_u_cla8_and54_y0
|
|
1 1
|
|
.names h_u_cla8_and38_y0 h_u_cla8_or10_h_u_cla8_and38_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or10_h_u_cla8_and54_y0 _b=h_u_cla8_or10_h_u_cla8_and38_y0 _y0=h_u_cla8_or10_y0
|
|
.names h_u_cla8_or10_y0 h_u_cla8_or11_h_u_cla8_or10_y0
|
|
1 1
|
|
.names h_u_cla8_and45_y0 h_u_cla8_or11_h_u_cla8_and45_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or11_h_u_cla8_or10_y0 _b=h_u_cla8_or11_h_u_cla8_and45_y0 _y0=h_u_cla8_or11_y0
|
|
.names h_u_cla8_or11_y0 h_u_cla8_or12_h_u_cla8_or11_y0
|
|
1 1
|
|
.names h_u_cla8_and50_y0 h_u_cla8_or12_h_u_cla8_and50_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or12_h_u_cla8_or11_y0 _b=h_u_cla8_or12_h_u_cla8_and50_y0 _y0=h_u_cla8_or12_y0
|
|
.names h_u_cla8_or12_y0 h_u_cla8_or13_h_u_cla8_or12_y0
|
|
1 1
|
|
.names h_u_cla8_and53_y0 h_u_cla8_or13_h_u_cla8_and53_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or13_h_u_cla8_or12_y0 _b=h_u_cla8_or13_h_u_cla8_and53_y0 _y0=h_u_cla8_or13_y0
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_or14_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.names h_u_cla8_or13_y0 h_u_cla8_or14_h_u_cla8_or13_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or14_h_u_cla8_pg_logic4_y1 _b=h_u_cla8_or14_h_u_cla8_or13_y0 _y0=h_u_cla8_or14_y0
|
|
.names a_5 h_u_cla8_pg_logic5_a_5
|
|
1 1
|
|
.names b_5 h_u_cla8_pg_logic5_b_5
|
|
1 1
|
|
.subckt pg_logic a=h_u_cla8_pg_logic5_a_5 b=h_u_cla8_pg_logic5_b_5 pg_logic_y0=h_u_cla8_pg_logic5_y0 pg_logic_y1=h_u_cla8_pg_logic5_y1 pg_logic_y2=h_u_cla8_pg_logic5_y2
|
|
.names h_u_cla8_pg_logic5_y2 h_u_cla8_xor5_h_u_cla8_pg_logic5_y2
|
|
1 1
|
|
.names h_u_cla8_or14_y0 h_u_cla8_xor5_h_u_cla8_or14_y0
|
|
1 1
|
|
.subckt xor_gate _a=h_u_cla8_xor5_h_u_cla8_pg_logic5_y2 _b=h_u_cla8_xor5_h_u_cla8_or14_y0 _y0=h_u_cla8_xor5_y0
|
|
.names h_u_cla8_pg_logic0_y0 h_u_cla8_and55_h_u_cla8_pg_logic0_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and55_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and55_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and55_constant_wire_0 _y0=h_u_cla8_and55_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and56_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and56_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and56_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and56_constant_wire_0 _y0=h_u_cla8_and56_y0
|
|
.names h_u_cla8_and56_y0 h_u_cla8_and57_h_u_cla8_and56_y0
|
|
1 1
|
|
.names h_u_cla8_and55_y0 h_u_cla8_and57_h_u_cla8_and55_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and57_h_u_cla8_and56_y0 _b=h_u_cla8_and57_h_u_cla8_and55_y0 _y0=h_u_cla8_and57_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and58_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and58_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and58_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and58_constant_wire_0 _y0=h_u_cla8_and58_y0
|
|
.names h_u_cla8_and58_y0 h_u_cla8_and59_h_u_cla8_and58_y0
|
|
1 1
|
|
.names h_u_cla8_and57_y0 h_u_cla8_and59_h_u_cla8_and57_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and59_h_u_cla8_and58_y0 _b=h_u_cla8_and59_h_u_cla8_and57_y0 _y0=h_u_cla8_and59_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and60_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and60_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and60_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and60_constant_wire_0 _y0=h_u_cla8_and60_y0
|
|
.names h_u_cla8_and60_y0 h_u_cla8_and61_h_u_cla8_and60_y0
|
|
1 1
|
|
.names h_u_cla8_and59_y0 h_u_cla8_and61_h_u_cla8_and59_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and61_h_u_cla8_and60_y0 _b=h_u_cla8_and61_h_u_cla8_and59_y0 _y0=h_u_cla8_and61_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and62_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and62_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and62_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and62_constant_wire_0 _y0=h_u_cla8_and62_y0
|
|
.names h_u_cla8_and62_y0 h_u_cla8_and63_h_u_cla8_and62_y0
|
|
1 1
|
|
.names h_u_cla8_and61_y0 h_u_cla8_and63_h_u_cla8_and61_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and63_h_u_cla8_and62_y0 _b=h_u_cla8_and63_h_u_cla8_and61_y0 _y0=h_u_cla8_and63_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and64_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and64_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and64_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and64_constant_wire_0 _y0=h_u_cla8_and64_y0
|
|
.names h_u_cla8_and64_y0 h_u_cla8_and65_h_u_cla8_and64_y0
|
|
1 1
|
|
.names h_u_cla8_and63_y0 h_u_cla8_and65_h_u_cla8_and63_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and65_h_u_cla8_and64_y0 _b=h_u_cla8_and65_h_u_cla8_and63_y0 _y0=h_u_cla8_and65_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and66_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and66_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and66_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and66_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and66_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and67_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and67_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and67_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and67_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and67_y0
|
|
.names h_u_cla8_and67_y0 h_u_cla8_and68_h_u_cla8_and67_y0
|
|
1 1
|
|
.names h_u_cla8_and66_y0 h_u_cla8_and68_h_u_cla8_and66_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and68_h_u_cla8_and67_y0 _b=h_u_cla8_and68_h_u_cla8_and66_y0 _y0=h_u_cla8_and68_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and69_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and69_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and69_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and69_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and69_y0
|
|
.names h_u_cla8_and69_y0 h_u_cla8_and70_h_u_cla8_and69_y0
|
|
1 1
|
|
.names h_u_cla8_and68_y0 h_u_cla8_and70_h_u_cla8_and68_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and70_h_u_cla8_and69_y0 _b=h_u_cla8_and70_h_u_cla8_and68_y0 _y0=h_u_cla8_and70_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and71_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and71_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and71_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and71_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and71_y0
|
|
.names h_u_cla8_and71_y0 h_u_cla8_and72_h_u_cla8_and71_y0
|
|
1 1
|
|
.names h_u_cla8_and70_y0 h_u_cla8_and72_h_u_cla8_and70_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and72_h_u_cla8_and71_y0 _b=h_u_cla8_and72_h_u_cla8_and70_y0 _y0=h_u_cla8_and72_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and73_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and73_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and73_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and73_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and73_y0
|
|
.names h_u_cla8_and73_y0 h_u_cla8_and74_h_u_cla8_and73_y0
|
|
1 1
|
|
.names h_u_cla8_and72_y0 h_u_cla8_and74_h_u_cla8_and72_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and74_h_u_cla8_and73_y0 _b=h_u_cla8_and74_h_u_cla8_and72_y0 _y0=h_u_cla8_and74_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and75_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and75_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and75_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and75_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and75_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and76_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and76_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and76_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and76_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and76_y0
|
|
.names h_u_cla8_and76_y0 h_u_cla8_and77_h_u_cla8_and76_y0
|
|
1 1
|
|
.names h_u_cla8_and75_y0 h_u_cla8_and77_h_u_cla8_and75_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and77_h_u_cla8_and76_y0 _b=h_u_cla8_and77_h_u_cla8_and75_y0 _y0=h_u_cla8_and77_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and78_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and78_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and78_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and78_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and78_y0
|
|
.names h_u_cla8_and78_y0 h_u_cla8_and79_h_u_cla8_and78_y0
|
|
1 1
|
|
.names h_u_cla8_and77_y0 h_u_cla8_and79_h_u_cla8_and77_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and79_h_u_cla8_and78_y0 _b=h_u_cla8_and79_h_u_cla8_and77_y0 _y0=h_u_cla8_and79_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and80_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and80_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and80_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and80_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and80_y0
|
|
.names h_u_cla8_and80_y0 h_u_cla8_and81_h_u_cla8_and80_y0
|
|
1 1
|
|
.names h_u_cla8_and79_y0 h_u_cla8_and81_h_u_cla8_and79_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and81_h_u_cla8_and80_y0 _b=h_u_cla8_and81_h_u_cla8_and79_y0 _y0=h_u_cla8_and81_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and82_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and82_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and82_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and82_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and82_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and83_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and83_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and83_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and83_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and83_y0
|
|
.names h_u_cla8_and83_y0 h_u_cla8_and84_h_u_cla8_and83_y0
|
|
1 1
|
|
.names h_u_cla8_and82_y0 h_u_cla8_and84_h_u_cla8_and82_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and84_h_u_cla8_and83_y0 _b=h_u_cla8_and84_h_u_cla8_and82_y0 _y0=h_u_cla8_and84_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and85_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and85_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and85_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and85_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and85_y0
|
|
.names h_u_cla8_and85_y0 h_u_cla8_and86_h_u_cla8_and85_y0
|
|
1 1
|
|
.names h_u_cla8_and84_y0 h_u_cla8_and86_h_u_cla8_and84_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and86_h_u_cla8_and85_y0 _b=h_u_cla8_and86_h_u_cla8_and84_y0 _y0=h_u_cla8_and86_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and87_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and87_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and87_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and87_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and87_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and88_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and88_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and88_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and88_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and88_y0
|
|
.names h_u_cla8_and88_y0 h_u_cla8_and89_h_u_cla8_and88_y0
|
|
1 1
|
|
.names h_u_cla8_and87_y0 h_u_cla8_and89_h_u_cla8_and87_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and89_h_u_cla8_and88_y0 _b=h_u_cla8_and89_h_u_cla8_and87_y0 _y0=h_u_cla8_and89_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and90_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_and90_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and90_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and90_h_u_cla8_pg_logic4_y1 _y0=h_u_cla8_and90_y0
|
|
.names h_u_cla8_and90_y0 h_u_cla8_or15_h_u_cla8_and90_y0
|
|
1 1
|
|
.names h_u_cla8_and65_y0 h_u_cla8_or15_h_u_cla8_and65_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or15_h_u_cla8_and90_y0 _b=h_u_cla8_or15_h_u_cla8_and65_y0 _y0=h_u_cla8_or15_y0
|
|
.names h_u_cla8_or15_y0 h_u_cla8_or16_h_u_cla8_or15_y0
|
|
1 1
|
|
.names h_u_cla8_and74_y0 h_u_cla8_or16_h_u_cla8_and74_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or16_h_u_cla8_or15_y0 _b=h_u_cla8_or16_h_u_cla8_and74_y0 _y0=h_u_cla8_or16_y0
|
|
.names h_u_cla8_or16_y0 h_u_cla8_or17_h_u_cla8_or16_y0
|
|
1 1
|
|
.names h_u_cla8_and81_y0 h_u_cla8_or17_h_u_cla8_and81_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or17_h_u_cla8_or16_y0 _b=h_u_cla8_or17_h_u_cla8_and81_y0 _y0=h_u_cla8_or17_y0
|
|
.names h_u_cla8_or17_y0 h_u_cla8_or18_h_u_cla8_or17_y0
|
|
1 1
|
|
.names h_u_cla8_and86_y0 h_u_cla8_or18_h_u_cla8_and86_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or18_h_u_cla8_or17_y0 _b=h_u_cla8_or18_h_u_cla8_and86_y0 _y0=h_u_cla8_or18_y0
|
|
.names h_u_cla8_or18_y0 h_u_cla8_or19_h_u_cla8_or18_y0
|
|
1 1
|
|
.names h_u_cla8_and89_y0 h_u_cla8_or19_h_u_cla8_and89_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or19_h_u_cla8_or18_y0 _b=h_u_cla8_or19_h_u_cla8_and89_y0 _y0=h_u_cla8_or19_y0
|
|
.names h_u_cla8_pg_logic5_y1 h_u_cla8_or20_h_u_cla8_pg_logic5_y1
|
|
1 1
|
|
.names h_u_cla8_or19_y0 h_u_cla8_or20_h_u_cla8_or19_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or20_h_u_cla8_pg_logic5_y1 _b=h_u_cla8_or20_h_u_cla8_or19_y0 _y0=h_u_cla8_or20_y0
|
|
.names a_6 h_u_cla8_pg_logic6_a_6
|
|
1 1
|
|
.names b_6 h_u_cla8_pg_logic6_b_6
|
|
1 1
|
|
.subckt pg_logic a=h_u_cla8_pg_logic6_a_6 b=h_u_cla8_pg_logic6_b_6 pg_logic_y0=h_u_cla8_pg_logic6_y0 pg_logic_y1=h_u_cla8_pg_logic6_y1 pg_logic_y2=h_u_cla8_pg_logic6_y2
|
|
.names h_u_cla8_pg_logic6_y2 h_u_cla8_xor6_h_u_cla8_pg_logic6_y2
|
|
1 1
|
|
.names h_u_cla8_or20_y0 h_u_cla8_xor6_h_u_cla8_or20_y0
|
|
1 1
|
|
.subckt xor_gate _a=h_u_cla8_xor6_h_u_cla8_pg_logic6_y2 _b=h_u_cla8_xor6_h_u_cla8_or20_y0 _y0=h_u_cla8_xor6_y0
|
|
.names h_u_cla8_pg_logic0_y0 h_u_cla8_and91_h_u_cla8_pg_logic0_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and91_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and91_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and91_constant_wire_0 _y0=h_u_cla8_and91_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and92_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and92_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and92_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and92_constant_wire_0 _y0=h_u_cla8_and92_y0
|
|
.names h_u_cla8_and92_y0 h_u_cla8_and93_h_u_cla8_and92_y0
|
|
1 1
|
|
.names h_u_cla8_and91_y0 h_u_cla8_and93_h_u_cla8_and91_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and93_h_u_cla8_and92_y0 _b=h_u_cla8_and93_h_u_cla8_and91_y0 _y0=h_u_cla8_and93_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and94_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and94_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and94_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and94_constant_wire_0 _y0=h_u_cla8_and94_y0
|
|
.names h_u_cla8_and94_y0 h_u_cla8_and95_h_u_cla8_and94_y0
|
|
1 1
|
|
.names h_u_cla8_and93_y0 h_u_cla8_and95_h_u_cla8_and93_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and95_h_u_cla8_and94_y0 _b=h_u_cla8_and95_h_u_cla8_and93_y0 _y0=h_u_cla8_and95_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and96_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and96_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and96_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and96_constant_wire_0 _y0=h_u_cla8_and96_y0
|
|
.names h_u_cla8_and96_y0 h_u_cla8_and97_h_u_cla8_and96_y0
|
|
1 1
|
|
.names h_u_cla8_and95_y0 h_u_cla8_and97_h_u_cla8_and95_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and97_h_u_cla8_and96_y0 _b=h_u_cla8_and97_h_u_cla8_and95_y0 _y0=h_u_cla8_and97_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and98_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and98_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and98_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and98_constant_wire_0 _y0=h_u_cla8_and98_y0
|
|
.names h_u_cla8_and98_y0 h_u_cla8_and99_h_u_cla8_and98_y0
|
|
1 1
|
|
.names h_u_cla8_and97_y0 h_u_cla8_and99_h_u_cla8_and97_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and99_h_u_cla8_and98_y0 _b=h_u_cla8_and99_h_u_cla8_and97_y0 _y0=h_u_cla8_and99_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and100_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and100_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and100_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and100_constant_wire_0 _y0=h_u_cla8_and100_y0
|
|
.names h_u_cla8_and100_y0 h_u_cla8_and101_h_u_cla8_and100_y0
|
|
1 1
|
|
.names h_u_cla8_and99_y0 h_u_cla8_and101_h_u_cla8_and99_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and101_h_u_cla8_and100_y0 _b=h_u_cla8_and101_h_u_cla8_and99_y0 _y0=h_u_cla8_and101_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and102_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and102_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and102_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and102_constant_wire_0 _y0=h_u_cla8_and102_y0
|
|
.names h_u_cla8_and102_y0 h_u_cla8_and103_h_u_cla8_and102_y0
|
|
1 1
|
|
.names h_u_cla8_and101_y0 h_u_cla8_and103_h_u_cla8_and101_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and103_h_u_cla8_and102_y0 _b=h_u_cla8_and103_h_u_cla8_and101_y0 _y0=h_u_cla8_and103_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and104_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and104_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and104_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and104_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and104_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and105_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and105_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and105_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and105_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and105_y0
|
|
.names h_u_cla8_and105_y0 h_u_cla8_and106_h_u_cla8_and105_y0
|
|
1 1
|
|
.names h_u_cla8_and104_y0 h_u_cla8_and106_h_u_cla8_and104_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and106_h_u_cla8_and105_y0 _b=h_u_cla8_and106_h_u_cla8_and104_y0 _y0=h_u_cla8_and106_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and107_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and107_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and107_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and107_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and107_y0
|
|
.names h_u_cla8_and107_y0 h_u_cla8_and108_h_u_cla8_and107_y0
|
|
1 1
|
|
.names h_u_cla8_and106_y0 h_u_cla8_and108_h_u_cla8_and106_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and108_h_u_cla8_and107_y0 _b=h_u_cla8_and108_h_u_cla8_and106_y0 _y0=h_u_cla8_and108_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and109_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and109_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and109_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and109_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and109_y0
|
|
.names h_u_cla8_and109_y0 h_u_cla8_and110_h_u_cla8_and109_y0
|
|
1 1
|
|
.names h_u_cla8_and108_y0 h_u_cla8_and110_h_u_cla8_and108_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and110_h_u_cla8_and109_y0 _b=h_u_cla8_and110_h_u_cla8_and108_y0 _y0=h_u_cla8_and110_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and111_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and111_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and111_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and111_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and111_y0
|
|
.names h_u_cla8_and111_y0 h_u_cla8_and112_h_u_cla8_and111_y0
|
|
1 1
|
|
.names h_u_cla8_and110_y0 h_u_cla8_and112_h_u_cla8_and110_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and112_h_u_cla8_and111_y0 _b=h_u_cla8_and112_h_u_cla8_and110_y0 _y0=h_u_cla8_and112_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and113_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and113_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and113_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and113_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and113_y0
|
|
.names h_u_cla8_and113_y0 h_u_cla8_and114_h_u_cla8_and113_y0
|
|
1 1
|
|
.names h_u_cla8_and112_y0 h_u_cla8_and114_h_u_cla8_and112_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and114_h_u_cla8_and113_y0 _b=h_u_cla8_and114_h_u_cla8_and112_y0 _y0=h_u_cla8_and114_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and115_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and115_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and115_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and115_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and115_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and116_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and116_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and116_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and116_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and116_y0
|
|
.names h_u_cla8_and116_y0 h_u_cla8_and117_h_u_cla8_and116_y0
|
|
1 1
|
|
.names h_u_cla8_and115_y0 h_u_cla8_and117_h_u_cla8_and115_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and117_h_u_cla8_and116_y0 _b=h_u_cla8_and117_h_u_cla8_and115_y0 _y0=h_u_cla8_and117_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and118_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and118_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and118_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and118_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and118_y0
|
|
.names h_u_cla8_and118_y0 h_u_cla8_and119_h_u_cla8_and118_y0
|
|
1 1
|
|
.names h_u_cla8_and117_y0 h_u_cla8_and119_h_u_cla8_and117_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and119_h_u_cla8_and118_y0 _b=h_u_cla8_and119_h_u_cla8_and117_y0 _y0=h_u_cla8_and119_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and120_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and120_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and120_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and120_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and120_y0
|
|
.names h_u_cla8_and120_y0 h_u_cla8_and121_h_u_cla8_and120_y0
|
|
1 1
|
|
.names h_u_cla8_and119_y0 h_u_cla8_and121_h_u_cla8_and119_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and121_h_u_cla8_and120_y0 _b=h_u_cla8_and121_h_u_cla8_and119_y0 _y0=h_u_cla8_and121_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and122_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and122_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and122_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and122_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and122_y0
|
|
.names h_u_cla8_and122_y0 h_u_cla8_and123_h_u_cla8_and122_y0
|
|
1 1
|
|
.names h_u_cla8_and121_y0 h_u_cla8_and123_h_u_cla8_and121_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and123_h_u_cla8_and122_y0 _b=h_u_cla8_and123_h_u_cla8_and121_y0 _y0=h_u_cla8_and123_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and124_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and124_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and124_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and124_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and124_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and125_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and125_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and125_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and125_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and125_y0
|
|
.names h_u_cla8_and125_y0 h_u_cla8_and126_h_u_cla8_and125_y0
|
|
1 1
|
|
.names h_u_cla8_and124_y0 h_u_cla8_and126_h_u_cla8_and124_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and126_h_u_cla8_and125_y0 _b=h_u_cla8_and126_h_u_cla8_and124_y0 _y0=h_u_cla8_and126_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and127_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and127_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and127_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and127_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and127_y0
|
|
.names h_u_cla8_and127_y0 h_u_cla8_and128_h_u_cla8_and127_y0
|
|
1 1
|
|
.names h_u_cla8_and126_y0 h_u_cla8_and128_h_u_cla8_and126_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and128_h_u_cla8_and127_y0 _b=h_u_cla8_and128_h_u_cla8_and126_y0 _y0=h_u_cla8_and128_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and129_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and129_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and129_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and129_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and129_y0
|
|
.names h_u_cla8_and129_y0 h_u_cla8_and130_h_u_cla8_and129_y0
|
|
1 1
|
|
.names h_u_cla8_and128_y0 h_u_cla8_and130_h_u_cla8_and128_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and130_h_u_cla8_and129_y0 _b=h_u_cla8_and130_h_u_cla8_and128_y0 _y0=h_u_cla8_and130_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and131_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and131_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and131_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and131_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and131_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and132_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and132_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and132_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and132_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and132_y0
|
|
.names h_u_cla8_and132_y0 h_u_cla8_and133_h_u_cla8_and132_y0
|
|
1 1
|
|
.names h_u_cla8_and131_y0 h_u_cla8_and133_h_u_cla8_and131_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and133_h_u_cla8_and132_y0 _b=h_u_cla8_and133_h_u_cla8_and131_y0 _y0=h_u_cla8_and133_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and134_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and134_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and134_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and134_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and134_y0
|
|
.names h_u_cla8_and134_y0 h_u_cla8_and135_h_u_cla8_and134_y0
|
|
1 1
|
|
.names h_u_cla8_and133_y0 h_u_cla8_and135_h_u_cla8_and133_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and135_h_u_cla8_and134_y0 _b=h_u_cla8_and135_h_u_cla8_and133_y0 _y0=h_u_cla8_and135_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and136_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_and136_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and136_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and136_h_u_cla8_pg_logic4_y1 _y0=h_u_cla8_and136_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and137_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_and137_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and137_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and137_h_u_cla8_pg_logic4_y1 _y0=h_u_cla8_and137_y0
|
|
.names h_u_cla8_and137_y0 h_u_cla8_and138_h_u_cla8_and137_y0
|
|
1 1
|
|
.names h_u_cla8_and136_y0 h_u_cla8_and138_h_u_cla8_and136_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and138_h_u_cla8_and137_y0 _b=h_u_cla8_and138_h_u_cla8_and136_y0 _y0=h_u_cla8_and138_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and139_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic5_y1 h_u_cla8_and139_h_u_cla8_pg_logic5_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and139_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and139_h_u_cla8_pg_logic5_y1 _y0=h_u_cla8_and139_y0
|
|
.names h_u_cla8_and139_y0 h_u_cla8_or21_h_u_cla8_and139_y0
|
|
1 1
|
|
.names h_u_cla8_and103_y0 h_u_cla8_or21_h_u_cla8_and103_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or21_h_u_cla8_and139_y0 _b=h_u_cla8_or21_h_u_cla8_and103_y0 _y0=h_u_cla8_or21_y0
|
|
.names h_u_cla8_or21_y0 h_u_cla8_or22_h_u_cla8_or21_y0
|
|
1 1
|
|
.names h_u_cla8_and114_y0 h_u_cla8_or22_h_u_cla8_and114_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or22_h_u_cla8_or21_y0 _b=h_u_cla8_or22_h_u_cla8_and114_y0 _y0=h_u_cla8_or22_y0
|
|
.names h_u_cla8_or22_y0 h_u_cla8_or23_h_u_cla8_or22_y0
|
|
1 1
|
|
.names h_u_cla8_and123_y0 h_u_cla8_or23_h_u_cla8_and123_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or23_h_u_cla8_or22_y0 _b=h_u_cla8_or23_h_u_cla8_and123_y0 _y0=h_u_cla8_or23_y0
|
|
.names h_u_cla8_or23_y0 h_u_cla8_or24_h_u_cla8_or23_y0
|
|
1 1
|
|
.names h_u_cla8_and130_y0 h_u_cla8_or24_h_u_cla8_and130_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or24_h_u_cla8_or23_y0 _b=h_u_cla8_or24_h_u_cla8_and130_y0 _y0=h_u_cla8_or24_y0
|
|
.names h_u_cla8_or24_y0 h_u_cla8_or25_h_u_cla8_or24_y0
|
|
1 1
|
|
.names h_u_cla8_and135_y0 h_u_cla8_or25_h_u_cla8_and135_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or25_h_u_cla8_or24_y0 _b=h_u_cla8_or25_h_u_cla8_and135_y0 _y0=h_u_cla8_or25_y0
|
|
.names h_u_cla8_or25_y0 h_u_cla8_or26_h_u_cla8_or25_y0
|
|
1 1
|
|
.names h_u_cla8_and138_y0 h_u_cla8_or26_h_u_cla8_and138_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or26_h_u_cla8_or25_y0 _b=h_u_cla8_or26_h_u_cla8_and138_y0 _y0=h_u_cla8_or26_y0
|
|
.names h_u_cla8_pg_logic6_y1 h_u_cla8_or27_h_u_cla8_pg_logic6_y1
|
|
1 1
|
|
.names h_u_cla8_or26_y0 h_u_cla8_or27_h_u_cla8_or26_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or27_h_u_cla8_pg_logic6_y1 _b=h_u_cla8_or27_h_u_cla8_or26_y0 _y0=h_u_cla8_or27_y0
|
|
.names a_7 h_u_cla8_pg_logic7_a_7
|
|
1 1
|
|
.names b_7 h_u_cla8_pg_logic7_b_7
|
|
1 1
|
|
.subckt pg_logic a=h_u_cla8_pg_logic7_a_7 b=h_u_cla8_pg_logic7_b_7 pg_logic_y0=h_u_cla8_pg_logic7_y0 pg_logic_y1=h_u_cla8_pg_logic7_y1 pg_logic_y2=h_u_cla8_pg_logic7_y2
|
|
.names h_u_cla8_pg_logic7_y2 h_u_cla8_xor7_h_u_cla8_pg_logic7_y2
|
|
1 1
|
|
.names h_u_cla8_or27_y0 h_u_cla8_xor7_h_u_cla8_or27_y0
|
|
1 1
|
|
.subckt xor_gate _a=h_u_cla8_xor7_h_u_cla8_pg_logic7_y2 _b=h_u_cla8_xor7_h_u_cla8_or27_y0 _y0=h_u_cla8_xor7_y0
|
|
.names h_u_cla8_pg_logic0_y0 h_u_cla8_and140_h_u_cla8_pg_logic0_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and140_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and140_h_u_cla8_pg_logic0_y0 _b=h_u_cla8_and140_constant_wire_0 _y0=h_u_cla8_and140_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and141_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and141_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and141_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and141_constant_wire_0 _y0=h_u_cla8_and141_y0
|
|
.names h_u_cla8_and141_y0 h_u_cla8_and142_h_u_cla8_and141_y0
|
|
1 1
|
|
.names h_u_cla8_and140_y0 h_u_cla8_and142_h_u_cla8_and140_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and142_h_u_cla8_and141_y0 _b=h_u_cla8_and142_h_u_cla8_and140_y0 _y0=h_u_cla8_and142_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and143_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and143_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and143_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and143_constant_wire_0 _y0=h_u_cla8_and143_y0
|
|
.names h_u_cla8_and143_y0 h_u_cla8_and144_h_u_cla8_and143_y0
|
|
1 1
|
|
.names h_u_cla8_and142_y0 h_u_cla8_and144_h_u_cla8_and142_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and144_h_u_cla8_and143_y0 _b=h_u_cla8_and144_h_u_cla8_and142_y0 _y0=h_u_cla8_and144_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and145_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and145_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and145_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and145_constant_wire_0 _y0=h_u_cla8_and145_y0
|
|
.names h_u_cla8_and145_y0 h_u_cla8_and146_h_u_cla8_and145_y0
|
|
1 1
|
|
.names h_u_cla8_and144_y0 h_u_cla8_and146_h_u_cla8_and144_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and146_h_u_cla8_and145_y0 _b=h_u_cla8_and146_h_u_cla8_and144_y0 _y0=h_u_cla8_and146_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and147_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and147_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and147_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and147_constant_wire_0 _y0=h_u_cla8_and147_y0
|
|
.names h_u_cla8_and147_y0 h_u_cla8_and148_h_u_cla8_and147_y0
|
|
1 1
|
|
.names h_u_cla8_and146_y0 h_u_cla8_and148_h_u_cla8_and146_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and148_h_u_cla8_and147_y0 _b=h_u_cla8_and148_h_u_cla8_and146_y0 _y0=h_u_cla8_and148_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and149_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and149_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and149_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and149_constant_wire_0 _y0=h_u_cla8_and149_y0
|
|
.names h_u_cla8_and149_y0 h_u_cla8_and150_h_u_cla8_and149_y0
|
|
1 1
|
|
.names h_u_cla8_and148_y0 h_u_cla8_and150_h_u_cla8_and148_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and150_h_u_cla8_and149_y0 _b=h_u_cla8_and150_h_u_cla8_and148_y0 _y0=h_u_cla8_and150_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and151_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and151_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and151_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and151_constant_wire_0 _y0=h_u_cla8_and151_y0
|
|
.names h_u_cla8_and151_y0 h_u_cla8_and152_h_u_cla8_and151_y0
|
|
1 1
|
|
.names h_u_cla8_and150_y0 h_u_cla8_and152_h_u_cla8_and150_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and152_h_u_cla8_and151_y0 _b=h_u_cla8_and152_h_u_cla8_and150_y0 _y0=h_u_cla8_and152_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and153_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names constant_wire_0 h_u_cla8_and153_constant_wire_0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and153_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and153_constant_wire_0 _y0=h_u_cla8_and153_y0
|
|
.names h_u_cla8_and153_y0 h_u_cla8_and154_h_u_cla8_and153_y0
|
|
1 1
|
|
.names h_u_cla8_and152_y0 h_u_cla8_and154_h_u_cla8_and152_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and154_h_u_cla8_and153_y0 _b=h_u_cla8_and154_h_u_cla8_and152_y0 _y0=h_u_cla8_and154_y0
|
|
.names h_u_cla8_pg_logic1_y0 h_u_cla8_and155_h_u_cla8_pg_logic1_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and155_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and155_h_u_cla8_pg_logic1_y0 _b=h_u_cla8_and155_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and155_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and156_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and156_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and156_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and156_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and156_y0
|
|
.names h_u_cla8_and156_y0 h_u_cla8_and157_h_u_cla8_and156_y0
|
|
1 1
|
|
.names h_u_cla8_and155_y0 h_u_cla8_and157_h_u_cla8_and155_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and157_h_u_cla8_and156_y0 _b=h_u_cla8_and157_h_u_cla8_and155_y0 _y0=h_u_cla8_and157_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and158_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and158_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and158_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and158_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and158_y0
|
|
.names h_u_cla8_and158_y0 h_u_cla8_and159_h_u_cla8_and158_y0
|
|
1 1
|
|
.names h_u_cla8_and157_y0 h_u_cla8_and159_h_u_cla8_and157_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and159_h_u_cla8_and158_y0 _b=h_u_cla8_and159_h_u_cla8_and157_y0 _y0=h_u_cla8_and159_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and160_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and160_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and160_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and160_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and160_y0
|
|
.names h_u_cla8_and160_y0 h_u_cla8_and161_h_u_cla8_and160_y0
|
|
1 1
|
|
.names h_u_cla8_and159_y0 h_u_cla8_and161_h_u_cla8_and159_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and161_h_u_cla8_and160_y0 _b=h_u_cla8_and161_h_u_cla8_and159_y0 _y0=h_u_cla8_and161_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and162_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and162_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and162_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and162_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and162_y0
|
|
.names h_u_cla8_and162_y0 h_u_cla8_and163_h_u_cla8_and162_y0
|
|
1 1
|
|
.names h_u_cla8_and161_y0 h_u_cla8_and163_h_u_cla8_and161_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and163_h_u_cla8_and162_y0 _b=h_u_cla8_and163_h_u_cla8_and161_y0 _y0=h_u_cla8_and163_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and164_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and164_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and164_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and164_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and164_y0
|
|
.names h_u_cla8_and164_y0 h_u_cla8_and165_h_u_cla8_and164_y0
|
|
1 1
|
|
.names h_u_cla8_and163_y0 h_u_cla8_and165_h_u_cla8_and163_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and165_h_u_cla8_and164_y0 _b=h_u_cla8_and165_h_u_cla8_and163_y0 _y0=h_u_cla8_and165_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and166_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic0_y1 h_u_cla8_and166_h_u_cla8_pg_logic0_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and166_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and166_h_u_cla8_pg_logic0_y1 _y0=h_u_cla8_and166_y0
|
|
.names h_u_cla8_and166_y0 h_u_cla8_and167_h_u_cla8_and166_y0
|
|
1 1
|
|
.names h_u_cla8_and165_y0 h_u_cla8_and167_h_u_cla8_and165_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and167_h_u_cla8_and166_y0 _b=h_u_cla8_and167_h_u_cla8_and165_y0 _y0=h_u_cla8_and167_y0
|
|
.names h_u_cla8_pg_logic2_y0 h_u_cla8_and168_h_u_cla8_pg_logic2_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and168_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and168_h_u_cla8_pg_logic2_y0 _b=h_u_cla8_and168_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and168_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and169_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and169_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and169_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and169_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and169_y0
|
|
.names h_u_cla8_and169_y0 h_u_cla8_and170_h_u_cla8_and169_y0
|
|
1 1
|
|
.names h_u_cla8_and168_y0 h_u_cla8_and170_h_u_cla8_and168_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and170_h_u_cla8_and169_y0 _b=h_u_cla8_and170_h_u_cla8_and168_y0 _y0=h_u_cla8_and170_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and171_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and171_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and171_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and171_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and171_y0
|
|
.names h_u_cla8_and171_y0 h_u_cla8_and172_h_u_cla8_and171_y0
|
|
1 1
|
|
.names h_u_cla8_and170_y0 h_u_cla8_and172_h_u_cla8_and170_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and172_h_u_cla8_and171_y0 _b=h_u_cla8_and172_h_u_cla8_and170_y0 _y0=h_u_cla8_and172_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and173_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and173_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and173_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and173_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and173_y0
|
|
.names h_u_cla8_and173_y0 h_u_cla8_and174_h_u_cla8_and173_y0
|
|
1 1
|
|
.names h_u_cla8_and172_y0 h_u_cla8_and174_h_u_cla8_and172_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and174_h_u_cla8_and173_y0 _b=h_u_cla8_and174_h_u_cla8_and172_y0 _y0=h_u_cla8_and174_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and175_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and175_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and175_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and175_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and175_y0
|
|
.names h_u_cla8_and175_y0 h_u_cla8_and176_h_u_cla8_and175_y0
|
|
1 1
|
|
.names h_u_cla8_and174_y0 h_u_cla8_and176_h_u_cla8_and174_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and176_h_u_cla8_and175_y0 _b=h_u_cla8_and176_h_u_cla8_and174_y0 _y0=h_u_cla8_and176_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and177_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic1_y1 h_u_cla8_and177_h_u_cla8_pg_logic1_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and177_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and177_h_u_cla8_pg_logic1_y1 _y0=h_u_cla8_and177_y0
|
|
.names h_u_cla8_and177_y0 h_u_cla8_and178_h_u_cla8_and177_y0
|
|
1 1
|
|
.names h_u_cla8_and176_y0 h_u_cla8_and178_h_u_cla8_and176_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and178_h_u_cla8_and177_y0 _b=h_u_cla8_and178_h_u_cla8_and176_y0 _y0=h_u_cla8_and178_y0
|
|
.names h_u_cla8_pg_logic3_y0 h_u_cla8_and179_h_u_cla8_pg_logic3_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and179_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and179_h_u_cla8_pg_logic3_y0 _b=h_u_cla8_and179_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and179_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and180_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and180_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and180_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and180_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and180_y0
|
|
.names h_u_cla8_and180_y0 h_u_cla8_and181_h_u_cla8_and180_y0
|
|
1 1
|
|
.names h_u_cla8_and179_y0 h_u_cla8_and181_h_u_cla8_and179_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and181_h_u_cla8_and180_y0 _b=h_u_cla8_and181_h_u_cla8_and179_y0 _y0=h_u_cla8_and181_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and182_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and182_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and182_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and182_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and182_y0
|
|
.names h_u_cla8_and182_y0 h_u_cla8_and183_h_u_cla8_and182_y0
|
|
1 1
|
|
.names h_u_cla8_and181_y0 h_u_cla8_and183_h_u_cla8_and181_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and183_h_u_cla8_and182_y0 _b=h_u_cla8_and183_h_u_cla8_and181_y0 _y0=h_u_cla8_and183_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and184_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and184_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and184_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and184_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and184_y0
|
|
.names h_u_cla8_and184_y0 h_u_cla8_and185_h_u_cla8_and184_y0
|
|
1 1
|
|
.names h_u_cla8_and183_y0 h_u_cla8_and185_h_u_cla8_and183_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and185_h_u_cla8_and184_y0 _b=h_u_cla8_and185_h_u_cla8_and183_y0 _y0=h_u_cla8_and185_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and186_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic2_y1 h_u_cla8_and186_h_u_cla8_pg_logic2_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and186_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and186_h_u_cla8_pg_logic2_y1 _y0=h_u_cla8_and186_y0
|
|
.names h_u_cla8_and186_y0 h_u_cla8_and187_h_u_cla8_and186_y0
|
|
1 1
|
|
.names h_u_cla8_and185_y0 h_u_cla8_and187_h_u_cla8_and185_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and187_h_u_cla8_and186_y0 _b=h_u_cla8_and187_h_u_cla8_and185_y0 _y0=h_u_cla8_and187_y0
|
|
.names h_u_cla8_pg_logic4_y0 h_u_cla8_and188_h_u_cla8_pg_logic4_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and188_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and188_h_u_cla8_pg_logic4_y0 _b=h_u_cla8_and188_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and188_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and189_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and189_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and189_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and189_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and189_y0
|
|
.names h_u_cla8_and189_y0 h_u_cla8_and190_h_u_cla8_and189_y0
|
|
1 1
|
|
.names h_u_cla8_and188_y0 h_u_cla8_and190_h_u_cla8_and188_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and190_h_u_cla8_and189_y0 _b=h_u_cla8_and190_h_u_cla8_and188_y0 _y0=h_u_cla8_and190_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and191_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and191_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and191_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and191_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and191_y0
|
|
.names h_u_cla8_and191_y0 h_u_cla8_and192_h_u_cla8_and191_y0
|
|
1 1
|
|
.names h_u_cla8_and190_y0 h_u_cla8_and192_h_u_cla8_and190_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and192_h_u_cla8_and191_y0 _b=h_u_cla8_and192_h_u_cla8_and190_y0 _y0=h_u_cla8_and192_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and193_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic3_y1 h_u_cla8_and193_h_u_cla8_pg_logic3_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and193_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and193_h_u_cla8_pg_logic3_y1 _y0=h_u_cla8_and193_y0
|
|
.names h_u_cla8_and193_y0 h_u_cla8_and194_h_u_cla8_and193_y0
|
|
1 1
|
|
.names h_u_cla8_and192_y0 h_u_cla8_and194_h_u_cla8_and192_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and194_h_u_cla8_and193_y0 _b=h_u_cla8_and194_h_u_cla8_and192_y0 _y0=h_u_cla8_and194_y0
|
|
.names h_u_cla8_pg_logic5_y0 h_u_cla8_and195_h_u_cla8_pg_logic5_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_and195_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and195_h_u_cla8_pg_logic5_y0 _b=h_u_cla8_and195_h_u_cla8_pg_logic4_y1 _y0=h_u_cla8_and195_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and196_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_and196_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and196_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and196_h_u_cla8_pg_logic4_y1 _y0=h_u_cla8_and196_y0
|
|
.names h_u_cla8_and196_y0 h_u_cla8_and197_h_u_cla8_and196_y0
|
|
1 1
|
|
.names h_u_cla8_and195_y0 h_u_cla8_and197_h_u_cla8_and195_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and197_h_u_cla8_and196_y0 _b=h_u_cla8_and197_h_u_cla8_and195_y0 _y0=h_u_cla8_and197_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and198_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic4_y1 h_u_cla8_and198_h_u_cla8_pg_logic4_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and198_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and198_h_u_cla8_pg_logic4_y1 _y0=h_u_cla8_and198_y0
|
|
.names h_u_cla8_and198_y0 h_u_cla8_and199_h_u_cla8_and198_y0
|
|
1 1
|
|
.names h_u_cla8_and197_y0 h_u_cla8_and199_h_u_cla8_and197_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and199_h_u_cla8_and198_y0 _b=h_u_cla8_and199_h_u_cla8_and197_y0 _y0=h_u_cla8_and199_y0
|
|
.names h_u_cla8_pg_logic6_y0 h_u_cla8_and200_h_u_cla8_pg_logic6_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic5_y1 h_u_cla8_and200_h_u_cla8_pg_logic5_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and200_h_u_cla8_pg_logic6_y0 _b=h_u_cla8_and200_h_u_cla8_pg_logic5_y1 _y0=h_u_cla8_and200_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and201_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic5_y1 h_u_cla8_and201_h_u_cla8_pg_logic5_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and201_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and201_h_u_cla8_pg_logic5_y1 _y0=h_u_cla8_and201_y0
|
|
.names h_u_cla8_and201_y0 h_u_cla8_and202_h_u_cla8_and201_y0
|
|
1 1
|
|
.names h_u_cla8_and200_y0 h_u_cla8_and202_h_u_cla8_and200_y0
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and202_h_u_cla8_and201_y0 _b=h_u_cla8_and202_h_u_cla8_and200_y0 _y0=h_u_cla8_and202_y0
|
|
.names h_u_cla8_pg_logic7_y0 h_u_cla8_and203_h_u_cla8_pg_logic7_y0
|
|
1 1
|
|
.names h_u_cla8_pg_logic6_y1 h_u_cla8_and203_h_u_cla8_pg_logic6_y1
|
|
1 1
|
|
.subckt and_gate _a=h_u_cla8_and203_h_u_cla8_pg_logic7_y0 _b=h_u_cla8_and203_h_u_cla8_pg_logic6_y1 _y0=h_u_cla8_and203_y0
|
|
.names h_u_cla8_and203_y0 h_u_cla8_or28_h_u_cla8_and203_y0
|
|
1 1
|
|
.names h_u_cla8_and154_y0 h_u_cla8_or28_h_u_cla8_and154_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or28_h_u_cla8_and203_y0 _b=h_u_cla8_or28_h_u_cla8_and154_y0 _y0=h_u_cla8_or28_y0
|
|
.names h_u_cla8_or28_y0 h_u_cla8_or29_h_u_cla8_or28_y0
|
|
1 1
|
|
.names h_u_cla8_and167_y0 h_u_cla8_or29_h_u_cla8_and167_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or29_h_u_cla8_or28_y0 _b=h_u_cla8_or29_h_u_cla8_and167_y0 _y0=h_u_cla8_or29_y0
|
|
.names h_u_cla8_or29_y0 h_u_cla8_or30_h_u_cla8_or29_y0
|
|
1 1
|
|
.names h_u_cla8_and178_y0 h_u_cla8_or30_h_u_cla8_and178_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or30_h_u_cla8_or29_y0 _b=h_u_cla8_or30_h_u_cla8_and178_y0 _y0=h_u_cla8_or30_y0
|
|
.names h_u_cla8_or30_y0 h_u_cla8_or31_h_u_cla8_or30_y0
|
|
1 1
|
|
.names h_u_cla8_and187_y0 h_u_cla8_or31_h_u_cla8_and187_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or31_h_u_cla8_or30_y0 _b=h_u_cla8_or31_h_u_cla8_and187_y0 _y0=h_u_cla8_or31_y0
|
|
.names h_u_cla8_or31_y0 h_u_cla8_or32_h_u_cla8_or31_y0
|
|
1 1
|
|
.names h_u_cla8_and194_y0 h_u_cla8_or32_h_u_cla8_and194_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or32_h_u_cla8_or31_y0 _b=h_u_cla8_or32_h_u_cla8_and194_y0 _y0=h_u_cla8_or32_y0
|
|
.names h_u_cla8_or32_y0 h_u_cla8_or33_h_u_cla8_or32_y0
|
|
1 1
|
|
.names h_u_cla8_and199_y0 h_u_cla8_or33_h_u_cla8_and199_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or33_h_u_cla8_or32_y0 _b=h_u_cla8_or33_h_u_cla8_and199_y0 _y0=h_u_cla8_or33_y0
|
|
.names h_u_cla8_or33_y0 h_u_cla8_or34_h_u_cla8_or33_y0
|
|
1 1
|
|
.names h_u_cla8_and202_y0 h_u_cla8_or34_h_u_cla8_and202_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or34_h_u_cla8_or33_y0 _b=h_u_cla8_or34_h_u_cla8_and202_y0 _y0=h_u_cla8_or34_y0
|
|
.names h_u_cla8_pg_logic7_y1 h_u_cla8_or35_h_u_cla8_pg_logic7_y1
|
|
1 1
|
|
.names h_u_cla8_or34_y0 h_u_cla8_or35_h_u_cla8_or34_y0
|
|
1 1
|
|
.subckt or_gate _a=h_u_cla8_or35_h_u_cla8_pg_logic7_y1 _b=h_u_cla8_or35_h_u_cla8_or34_y0 _y0=h_u_cla8_or35_y0
|
|
.names h_u_cla8_xor0_y0 out[0]
|
|
1 1
|
|
.names h_u_cla8_xor1_y0 out[1]
|
|
1 1
|
|
.names h_u_cla8_xor2_y0 out[2]
|
|
1 1
|
|
.names h_u_cla8_xor3_y0 out[3]
|
|
1 1
|
|
.names h_u_cla8_xor4_y0 out[4]
|
|
1 1
|
|
.names h_u_cla8_xor5_y0 out[5]
|
|
1 1
|
|
.names h_u_cla8_xor6_y0 out[6]
|
|
1 1
|
|
.names h_u_cla8_xor7_y0 out[7]
|
|
1 1
|
|
.names h_u_cla8_or35_y0 out[8]
|
|
1 1
|
|
.end
|
|
|
|
.model pg_logic
|
|
.inputs a b
|
|
.outputs pg_logic_y0 pg_logic_y1 pg_logic_y2
|
|
.names a pg_logic_a
|
|
1 1
|
|
.names b pg_logic_b
|
|
1 1
|
|
.subckt or_gate _a=pg_logic_a _b=pg_logic_b _y0=pg_logic_y0
|
|
.subckt and_gate _a=pg_logic_a _b=pg_logic_b _y0=pg_logic_y1
|
|
.subckt xor_gate _a=pg_logic_a _b=pg_logic_b _y0=pg_logic_y2
|
|
.end
|
|
|
|
.model constant_wire_value_0
|
|
.inputs a b
|
|
.outputs constant_wire_0
|
|
.names a constant_wire_value_0_a
|
|
1 1
|
|
.names b constant_wire_value_0_b
|
|
1 1
|
|
.subckt xor_gate _a=constant_wire_value_0_a _b=constant_wire_value_0_b _y0=constant_wire_value_0_y0
|
|
.subckt xnor_gate _a=constant_wire_value_0_a _b=constant_wire_value_0_b _y0=constant_wire_value_0_y1
|
|
.subckt nor_gate _a=constant_wire_value_0_y0 _b=constant_wire_value_0_y1 _y0=constant_wire_0
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
11 1
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
1- 1
|
|
-1 1
|
|
.end
|
|
|
|
.model nor_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
00 1
|
|
.end
|
|
|
|
.model xnor_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
00 1
|
|
11 1
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
01 1
|
|
10 1
|
|
.end
|