honzastor e5f2dd893a Fixed proper generated circuits names (mistakenly named cska as csa).

2021-04-28 21:39:58 +02:00

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__init__.py

Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.

2021-04-23 02:44:14 +02:00

carry_lookahead_adder.py

Updated circuits documentation.

2021-04-21 13:42:07 +02:00

carry_skip_adder.py

Fixed proper generated circuits names (mistakenly named cska as csa).

2021-04-28 21:39:58 +02:00

pg_ripple_carry_adder.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00

ripple_carry_adder.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00