156 lines
5.4 KiB
Python
156 lines
5.4 KiB
Python
from ariths_gen.wire_components import (
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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GeneralCircuit
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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XnorGate,
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NotGate
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)
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from ariths_gen.multi_bit_circuits.others import (
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OrReduce
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)
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class UnsignedCompareLT(GeneralCircuit):
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"""Class representing unsigned compare
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Returns true if a < b
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"""
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def __init__(self, a: Bus, b: Bus, prefix : str = "", name : str = "cmp_lt", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(name=name, prefix=prefix, inputs=[a, b], out_N=1)
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# create wires
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psum = ConstantWireValue1()
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res = Bus(N = self.N, prefix=self.prefix + "res")
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for i in reversed(range(self.N)):
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iA = self.a[i] if i < self.a.N else ConstantWireValue0()
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iB = self.b[i] if i < self.b.N else ConstantWireValue0()
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i1 = self.add_component(NotGate(iA, f"{self.prefix}_i1_{i}")).out
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i2 = iB
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and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
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res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
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pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
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psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
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red = self.add_component(OrReduce(res, prefix=f"{self.prefix}_orred", inner_component=True))
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self.out.connect_bus(red.out)
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class UnsignedCompareLTE(GeneralCircuit):
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"""Class representing unsigned compare
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Returns true if a <= b
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"""
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def __init__(self, a: Bus, b: Bus, prefix : str = "", name : str = "cmp_lte", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(name=name, prefix=prefix, inputs=[a, b], out_N=1)
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# create wires
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psum = ConstantWireValue1()
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res = Bus(N = self.N + 1, prefix=self.prefix + "res")
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for i in reversed(range(self.N)):
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iA = self.a[i] if i < self.a.N else ConstantWireValue0()
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iB = self.b[i] if i < self.b.N else ConstantWireValue0()
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i1 = self.add_component(NotGate(iA, f"{self.prefix}_i1_{i}")).out
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i2 = iB
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and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
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res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
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pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
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psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
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res[self.N] = psum # or all equal (xor)
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red = self.add_component(OrReduce(res, prefix=f"{self.prefix}_orred", inner_component=True))
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self.out.connect_bus(red.out)
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class UnsignedCompareGT(GeneralCircuit):
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"""Class representing unsigned compare
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Returns true if a < b
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"""
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def __init__(self, a: Bus, b: Bus, prefix : str = "", name : str = "cmp_gt", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(name=name, prefix=prefix, inputs=[a, b], out_N=1)
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# create wires
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psum = ConstantWireValue1()
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res = Bus(N = self.N, prefix=self.prefix + "res")
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for i in reversed(range(self.N)):
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iA = self.a[i] if i < self.a.N else ConstantWireValue0()
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iB = self.b[i] if i < self.b.N else ConstantWireValue0()
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i1 = iA
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i2 = self.add_component(NotGate(iB, f"{self.prefix}_i2_{i}")).out
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and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
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res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
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pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
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psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
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red = self.add_component(OrReduce(res, prefix=f"{self.prefix}_orred", inner_component=True))
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self.out.connect_bus(red.out)
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class UnsignedCompareGTE(GeneralCircuit):
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"""Class representing unsigned compare
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Returns true if a <= b
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"""
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def __init__(self, a: Bus, b: Bus, prefix : str = "", name : str = "cmp_gte", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(name=name, prefix=prefix, inputs=[a, b], out_N=1)
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# create wires
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psum = ConstantWireValue1()
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res = Bus(N = self.N + 1, prefix=self.prefix + "res")
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for i in reversed(range(self.N)):
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iA = self.a[i] if i < self.a.N else ConstantWireValue0()
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iB = self.b[i] if i < self.b.N else ConstantWireValue0()
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i1 = iA
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i2 = self.add_component(NotGate(iB, f"{self.prefix}_i1_{i}", parent_component=self)).out
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and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}", parent_component=self)).out
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res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}", parent_component=self)).out
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pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
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psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}", parent_component=self)).out
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res[self.N] = psum # or all equal (xor)
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red = self.add_component(OrReduce(res, prefix=f"{self.prefix}_orred", inner_component=True, parent_component=self))
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self.out.connect_bus(red.out)
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