123 lines
4.2 KiB
Python
123 lines
4.2 KiB
Python
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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GeneralCircuit
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)
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from ariths_gen.core.logic_gate_circuits import (
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MultipleInputLogicGate
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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PGLogicBlock,
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FullAdder,
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FullAdderPG
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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import re
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class UnsignedCGPCircuit(GeneralCircuit):
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""" Circuit that loads CGP code and is able to export it to C/verilog/Blif/CGP """
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def __init__(self, code: str, input_widths: list, prefix: str = "", name: str = "cgp", **kwargs):
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cgp_prefix, cgp_core, cgp_outputs = re.match(
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r"{(.*)}(.*)\(([^()]+)\)", code).groups()
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c_in, c_out, c_rows, c_cols, c_ni, c_no, c_lback = map(
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int, cgp_prefix.split(","))
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print(cgp_core)
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print(cgp_outputs)
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assert sum(
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input_widths) == c_in, f"CGP input widht {c_in} doesn't match input_widhts {input_widths}"
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#assert c_rows == 1, f"Only one-row CGP is supported {c_rows}x{c_cols}"
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inputs = [Bus(N=bw, prefix=f"input_{chr(i)}")
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for i, bw in enumerate(input_widths, start=0x61)]
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#vals = Bus(N=c_rows * c_cols, prefix=f"{prefix}_data")
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# adding values to the list
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self.vals = {}
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j = 2 # start from two, 0=false, 1 = true
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for iid, bw in enumerate(input_widths):
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for i in range(bw):
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assert j not in self.vals
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self.vals[j] = inputs[iid].get_wire(i)
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j += 1
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super().__init__(prefix=prefix, name=name, out_N=c_out, inputs=inputs, **kwargs)
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cgp_core = cgp_core.split(")(")
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i = 0
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for definition in cgp_core:
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i, in_a, in_b, fn = map(int, re.match(
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r"\(?\[(\d+)\](\d+),(\d+),(\d+)\)?", definition).groups())
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assert in_a < i
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assert in_b < i
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comp_set = dict(prefix=f"{self.prefix}_core_{i:03d}", parent_component=self)
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a, b = self._get_wire(in_a), self._get_wire(in_b)
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if fn == 0: # identity
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o = a
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elif fn == 1: # not
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o = self.add_component(NotGate(a, **comp_set)).out
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elif fn == 2: # and
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o = self.add_component(AndGate(a, b, **comp_set)).out
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elif fn == 3: # or
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o = self.add_component(OrGate(a, b, **comp_set)).out
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elif fn == 4: # xor
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o = self.add_component(XorGate(a, b, **comp_set)).out
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elif fn == 5: # nand
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o = self.add_component(NandGate(a, b, **comp_set)).out
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elif fn == 6: # nor
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o = self.add_component(NorGate(a, b, **comp_set)).out
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elif fn == 7: # xnor
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o = self.add_component(XnorGate(a, b, **comp_set)).out
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elif fn == 8: # true
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o = ConstantWireValue1()
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elif fn == 9: # false
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o = ConstantWireValue0()
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assert i not in self.vals
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self.vals[i] = o
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# output connection
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for i, o in enumerate(map(int, cgp_outputs.split(","))):
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w = self._get_wire(o)
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#print(i, o, w, w.name)
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self.out.connect(i, w)
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def _get_wire(self, i):
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if i == 0:
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return ConstantWireValue0()
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if i == 1:
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return ConstantWireValue1()
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return self.vals[i]
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#self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
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#self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
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# self.out.connect_bus(connecting_bus=self.add.out)
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class SignedCGPCircuit(UnsignedCGPCircuit):
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def __init__(self, code: str, input_widths: list, prefix: str = "", name: str = "cgp", **kwargs):
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super().__init__(code=code, input_widths=input_widths, prefix=prefix, name=name, signed=True, **kwargs)
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self.c_data_type = "int64_t" |