334 lines
16 KiB
Python
334 lines
16 KiB
Python
from arithmetic_circuits import arithmetic_circuit
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from logic_gates import logic_gate, and_gate, nand_gate, or_gate, nor_gate, xor_gate, xnor_gate, not_gate
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from wire_components import wire, bus
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""" ONE BIT CIRCUITS """
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class one_bit_circuit(arithmetic_circuit):
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def __init__(self):
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super().__init__()
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""" C CODE GENERATION """
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# FLAT C #
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c_flat(self):
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self.get_circuit_wires()
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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# Half adder (2 inputs adder) wires values initialization
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def get_init_c_flat(self):
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return f"{self.components[0].a.get_assign_c(name=self.components[0].a.get_wire_value_c(name=self.a.name))}" + \
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f"{self.components[0].b.get_assign_c(name=self.components[0].b.get_wire_value_c(name=self.b.name))}" + \
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"".join([f" {c.out.name} = {c.get_init_c_flat()};\n" for c in self.components])
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# Generating flat C code representation of circuit
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def get_c_code_flat(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(self.out.get_declaration_c())
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file_object.write(self.get_declaration_c_flat()+"\n")
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file_object.write(self.get_init_c_flat()+"\n")
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file_object.write(self.get_function_out_c_flat())
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C #
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def get_function_block_c(self):
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adder_block = half_adder(a=wire(name="a"), b=wire(name="b")) if isinstance(self, half_adder) else full_adder(a=wire(name="a"), b=wire(name="b"), c=wire(name="cin"))
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return f"{adder_block.get_circuit_c()}\n\n"
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def get_wire_declaration_c_hier(self):
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return f"{self.out.get_wire_declaration_c()}"
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def get_out_invocation_c(self, **kwargs):
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return self.get_sum_invocation_c()+"\n" + \
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self.get_cout_invocation_c()+"\n"
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def get_sum_invocation_c(self):
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return f" {self.get_sum_wire().name} = (ha({self.a.name}, {self.b.name}) >> 0) & 0x01;"
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def get_cout_invocation_c(self):
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return f" {self.get_carry_wire().name} = (ha({self.a.name}, {self.b.name}) >> 1) & 0x01;"
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def get_function_sum_c_hier(self, offset: int = 0):
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return f" {self.out.prefix} |= {self.components[0].get_gate_output_c(a=self.a ,b=self.b, offset=offset)};\n"
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def get_function_carry_c_hier(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.components[1].get_gate_output_c(a=self.a ,b=self.b, offset=offset)};\n"
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def get_circuit_c(self):
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}" + \
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f"{self.get_function_sum_c_hier()}" + \
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input {self.a.name}, input {self.b.name}, output {self.out.get_wire(0).name}, output {self.out.get_wire(1).name});\n"
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def get_declaration_v_flat(self):
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self.get_circuit_wires()
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_v() for c in self.circuit_wires])
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# Half adder (2 inputs adder) wires values initialization
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def get_init_v_flat(self):
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return f"{self.components[0].get_assign_v_flat()}" + \
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f" assign {self.components[1].out.name} = {self.components[1].get_init_v_flat()};\n"
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# Not used in 1 bit circuits (no effect when calling while generating)
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def get_function_out_v_flat(self):
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return ""
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# HIERARCHICAL VERILOG #
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def get_function_block_v(self):
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adder_block = half_adder(a=wire(name="a"), b=wire(name="b")) if isinstance(self, half_adder) else full_adder(a=wire(name="a"), b=wire(name="b"), c=wire(name="cin"))
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return f"{adder_block.get_circuit_v()}\n\n"
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def get_wire_declaration_v_hier(self):
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return f"{self.out.get_wire_declaration_v()}"
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def get_invocation_v(self, **kwargs):
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return f" ha ha_{self.get_carry_wire().name}({self.a.name}, {self.b.name}, {self.get_sum_wire().name}, {self.get_carry_wire().name});\n"
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def get_function_sum_v_hier(self):
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return f"{self.components[0].get_gate_invocation_v()}"
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def get_function_carry_v_hier(self):
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return f"{self.components[1].get_gate_invocation_v()}"
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def get_circuit_v(self):
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return f"{self.get_prototype_v()}" + \
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f"{self.get_function_sum_v_hier()}" + \
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f"{self.get_function_carry_v_hier()}" + \
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f"endmodule"
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""" BLIF CODE GENERATION """
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# FLAT BLIF #
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def get_declaration_blif(self):
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return f".inputs {self.a.name} {self.b.name}" + \
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f"\n.outputs" + \
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"".join([f" {w.name}" for w in self.out.bus])+"\n"
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def get_wire_mapping_blif(self):
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# For unique mapping of all circuit's input interconnections
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self.get_circuit_wires()
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return "".join([c[0].get_assign_blif(name=c[0].name.replace(self.prefix+'_', '')) for c in self.circuit_wires[:self.out.N]])
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def get_function_blif_flat(self):
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return f"{self.get_wire_mapping_blif()}"+"".join([c.get_function_blif_flat() for c in self.components])
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# Not needed in 1-bit circuits
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def get_function_out_blif(self):
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return ""
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# HIERARCHICAL BLIF #
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def get_function_block_blif(self):
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adder_block = half_adder(a=wire(name="a"), b=wire(name="b")) if isinstance(self, half_adder) else full_adder(a=wire(name="a"), b=wire(name="b"), c=wire(name="cin"))
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return f"{adder_block.get_circuit_blif()}"
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def get_function_blif_hier(self):
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return "".join(c.get_invocation_blif_hier(init=False) for c in self.components)
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def get_invocation_blif_hier(self, **kwargs):
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return f"{self.get_wire_mapping_blif()}" + \
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f".subckt ha a={self.circuit_wires[0][0].name} b={self.circuit_wires[1][0].name} ha_y0={self.out.get_wire(0).name} ha_y1={self.out.get_wire(1).name}\n"
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def get_circuit_blif(self):
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return f"{self.get_prototype_blif()}" + \
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f"{self.get_declaration_blif()}" + \
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f"{self.get_wire_mapping_blif()}" + \
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f"{self.get_function_blif_hier()}" + \
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f".end\n"
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""" CGP CODE GENERATION """
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# FLAT CGP #
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def get_parameters_cgp(self):
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self.circuit_gates = self.get_circuit_gates()
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return f"{{2,2,1,{len(self.circuit_gates)},2,1,0}}"
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class half_adder(one_bit_circuit):
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def __init__(self, a: wire, b: wire, prefix: str = "ha"):
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super().__init__()
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self.c_data_type = "uint8_t"
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self.prefix = prefix
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self.a = a
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self.b = b
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", self.N+1)
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# Sum
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# XOR gate for calculation of 1-bit sum
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obj_xor_gate = xor_gate(a, b, prefix, outid=0)
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self.add_component(obj_xor_gate)
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self.out.connect(0, obj_xor_gate.out)
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# Cout
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# AND gate for calculation of 1-bit cout
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obj_and_gate = and_gate(a, b, prefix, outid=1)
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self.add_component(obj_and_gate)
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self.out.connect(1, obj_and_gate.out)
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class full_adder(one_bit_circuit):
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def __init__(self, a: wire, b: wire, c: wire, prefix: str = "fa"):
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super().__init__()
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self.c_data_type = "uint8_t"
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self.prefix = prefix
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self.a = a
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self.b = b
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self.c = c
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", self.N+1)
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# PG logic
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propagate_xor_gate1 = xor_gate(a, b, prefix, outid=0)
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self.add_component(propagate_xor_gate1)
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generate_and_gate1 = and_gate(a, b, prefix, outid=1)
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self.add_component(generate_and_gate1)
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# Sum
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# XOR gate for calculation of 1-bit sum
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obj_xor_gate2 = xor_gate(propagate_xor_gate1.out, c, prefix, outid=2)
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self.add_component(obj_xor_gate2)
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self.out.connect(0, obj_xor_gate2.out)
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# Cout
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# AND gate for calculation of 1-bit cout
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obj_and_gate2 = and_gate(propagate_xor_gate1.out, c, prefix, outid=3)
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self.add_component(obj_and_gate2)
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obj_or_gate = or_gate(generate_and_gate1.out, obj_and_gate2.out, prefix, outid=4)
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self.add_component(obj_or_gate)
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self.out.connect(1, obj_or_gate.out)
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# TODO delete?
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# Storing PG logic gates for better accessibility
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self.propagate = propagate_xor_gate1
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self.generate = generate_and_gate1
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""" C CODE GENERATION """
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# FLAT C #
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# Full adder function prototype with three inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix}, {self.c_data_type} {self.c.prefix})" + "{" + "\n"
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# Full adder wires values initialization
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def get_init_c_flat(self):
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return f"{self.components[0].a.get_assign_c(name=self.components[0].a.get_wire_value_c(name=self.a.name))}" + \
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f"{self.components[0].b.get_assign_c(name=self.components[0].b.get_wire_value_c(name=self.b.name))}" + \
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f"{self.components[2].b.get_assign_c(name=self.components[2].b.get_wire_value_c(name=self.c.name))}" + \
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"".join([f" {c.out.name} = {c.get_init_c_flat()};\n" for c in self.components])
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# HIERARCHICAL C #
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def get_declaration_c_hier(self):
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return f"{self.components[0].out.get_declaration_c()}" + \
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f"{self.components[1].out.get_declaration_c()}" + \
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f"{self.components[3].out.get_declaration_c()}"
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def get_init_c_hier(self):
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# Temporarily change cin name for proper gate invocation
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self.components[2].b.name = self.components[3].b.name = self.components[2].b.name.replace(self.prefix+"_", "")
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return f" {self.components[0].out.name} = {self.components[0].get_gate_invocation_c()}" + \
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f" {self.components[1].out.name} = {self.components[1].get_gate_invocation_c()}" + \
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f" {self.components[3].out.name} = {self.components[3].get_gate_invocation_c(remove_prefix=False)}"
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def get_sum_invocation_c(self):
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return f" {self.get_sum_wire().name} = (fa({self.a.name}, {self.b.name}, {self.c.name}) >> 0) & 0x01;"
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def get_cout_invocation_c(self):
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return f" {self.get_carry_wire().name} = (fa({self.a.name}, {self.b.name}, {self.c.name}) >> 1) & 0x01;"
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def get_function_sum_c_hier(self, offset: int = 0):
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return f" {self.out.prefix} |= {self.components[0].get_gate_output_c(a=self.components[0].out, b=self.c, offset=offset)};\n"
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def get_function_carry_c_hier(self, offset: int = 1):
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# Return cin name to previous string value for sake of consistency
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self.components[2].b.name = self.components[3].b.name = self.prefix+"_"+self.c.name
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return f" {self.out.prefix} |= {self.get_previous_component().get_gate_output_c(a=self.components[1].out, b=self.components[3].out, offset=offset)};\n"
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def get_circuit_c(self):
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}" + \
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f"{self.get_declaration_c_hier()}\n" + \
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f"{self.get_init_c_hier()}\n" + \
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f"{self.get_function_sum_c_hier()}" + \
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input {self.a.name}, input {self.b.name}, input {self.c.name}, output {self.out.get_wire(0).name}, output {self.out.get_wire(1).name});\n"
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# Full adder wires values initialization
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def get_init_v_flat(self):
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return f"{self.components[0].a.get_assign_v(name=self.components[0].a.name.replace(self.prefix+'_', ''))}" + \
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f"{self.components[0].b.get_assign_v(name=self.components[0].b.name.replace(self.prefix+'_', ''))}" + \
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f"{self.components[2].b.get_assign_v(name=self.components[2].b.name.replace(self.prefix+'_', ''))}" + \
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"".join([f" assign {c.out.name} = {c.get_init_v_flat()};\n" for c in self.components])
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# HIERARCHICAL VERILOG #
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def get_invocation_v(self, **kwargs):
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return f" fa fa_{self.get_carry_wire().name}({self.a.name}, {self.b.name}, {self.c.name}, {self.get_sum_wire().name}, {self.get_carry_wire().name});\n"
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def get_declaration_v_hier(self):
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return f"{self.components[0].out.get_declaration_v()}" + \
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f"{self.components[1].out.get_declaration_v()}" + \
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f"{self.components[3].out.get_declaration_v()}"
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def get_init_v_hier(self):
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# Temporarily change cin name for proper gate invocation
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self.components[2].b.name = self.components[3].b.name = self.components[2].b.name.replace(self.prefix+"_", "")
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return f"{self.components[0].get_gate_invocation_v()}" + \
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f"{self.components[1].get_gate_invocation_v()}" + \
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f"{self.components[3].get_gate_invocation_v(remove_prefix=False)}"
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def get_function_sum_v_hier(self):
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return f"{self.components[2].get_gate_invocation_v(remove_prefix=False)}"
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def get_function_carry_v_hier(self):
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# Return cin name to previous string value for sake of consistency
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self.components[2].b.name = self.components[3].b.name = self.prefix+"_"+self.c.name
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return f"{self.components[4].get_gate_invocation_v(remove_prefix=False)}"
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def get_circuit_v(self):
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return f"{self.get_prototype_v()}" + \
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f"{self.get_declaration_v_hier()}\n" + \
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f"{self.get_init_v_hier()}\n" + \
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f"{self.get_function_sum_v_hier()}" + \
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f"{self.get_function_carry_v_hier()}" + \
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f"endmodule"
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""" BLIF CODE GENERATION """
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# FLAT BLIF #
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def get_declaration_blif(self):
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return f".inputs {self.a.name} {self.b.name} {self.c.name}" + \
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f"\n.outputs" + \
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"".join([f" {w.name}" for w in self.out.bus])+"\n"
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def get_wire_mapping_blif(self):
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# For unique mapping of all circuit's input interconnections
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self.get_circuit_wires()
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# getting desired inner wires and selecting first element from list of tuples containing wires and other info
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return f"{self.circuit_wires[0][0].get_assign_blif(name=self.circuit_wires[0][0].name.replace(self.prefix+'_', ''))}" + \
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f"{self.circuit_wires[1][0].get_assign_blif(name=self.circuit_wires[1][0].name.replace(self.prefix+'_', ''))}" + \
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f"{self.circuit_wires[4][0].get_assign_blif(name=self.circuit_wires[4][0].name.replace(self.prefix+'_', ''))}"
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# HIERARCHICAL BLIF #
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def get_invocation_blif_hier(self, **kwargs):
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return f"{self.get_wire_mapping_blif()}" + \
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f".subckt fa a={self.circuit_wires[0][0].name} b={self.circuit_wires[1][0].name} cin={self.circuit_wires[4][0].name} fa_y2={self.out.get_wire(0).name} fa_y4={self.out.get_wire(1).name}\n"
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""" CGP CODE GENERATION """
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# FLAT CGP #
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def get_parameters_cgp(self):
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self.circuit_gates = self.get_circuit_gates()
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return f"{{3,2,1,{len(self.circuit_gates)},2,1,0}}" |