376 lines
20 KiB
Python
376 lines
20 KiB
Python
from itertools import combinations_with_replacement
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from arithmetic_circuits import arithmetic_circuit, multiplier_circuit
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from one_bit_circuits import half_adder, full_adder
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from logic_gates import logic_gate, and_gate, nand_gate, or_gate, nor_gate, xor_gate, xnor_gate, not_gate
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from wire_components import wire, bus
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""" MULTI BIT CIRCUITS """
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# ADDERS
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class unsigned_ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "u_rca"):
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super().__init__()
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self.N = max(a.N, b.N)
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self.a = bus(prefix=a.prefix, wires_list=a.bus)
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self.b = bus(prefix=b.prefix, wires_list=b.bus)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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if prefix == "u_rca" or prefix == "s_rca":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for N sum bits and additional cout bit
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self.out = bus("out", self.N+1)
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# TODO replace ha for fa???
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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# First one is a half adder
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if input_index == 0:
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obj_ha = half_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), prefix=self.prefix+"_ha")
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self.add_component(obj_ha)
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self.out.connect(input_index, obj_ha.get_sum_wire())
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if input_index == (self.N-1):
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self.out.connect(self.N, obj_ha.get_carry_wire())
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# Rest are full adders
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else:
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obj_fa = full_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_fa)
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self.out.connect(input_index, obj_fa.get_sum_wire())
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if input_index == (self.N-1):
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self.out.connect(self.N, obj_fa.get_carry_wire())
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class signed_ripple_carry_adder(unsigned_ripple_carry_adder, arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "s_rca"):
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super().__init__(a=a, b=b, prefix=prefix)
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self.c_data_type = "int64_t"
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# Additional XOR gates to ensure correct sign extension in case of sign addition
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sign_xor_1 = xor_gate(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=xor_gate)))
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self.add_component(sign_xor_1)
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sign_xor_2 = xor_gate(sign_xor_1.out, self.get_previous_component(2).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=xor_gate)))
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self.add_component(sign_xor_2)
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self.out.connect(self.N, sign_xor_2.out)
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# TODO CHANGE!!! test, think about proper P/G gates generation
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class unsigned_carry_lookahead_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "u_cla"):
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super().__init__()
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self.N = max(a.N, b.N)
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self.a = bus(prefix=a.prefix, wires_list=a.bus)
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self.b = bus(prefix=b.prefix, wires_list=b.bus)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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if prefix == "u_cla" or prefix == "s_cla":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for N sum bits and additional cout bit
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self.out = bus("out", self.N+1)
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# Generating wire with constant logic value 0 (output of the nor gate), used as cin to first fa
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obj_xor = xor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xor_constant_wire")
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obj_xnor = xnor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xnor_constant_wire")
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obj_nor = nor_gate(obj_xor.out, obj_xnor.out, prefix=self.prefix+"_nor_constant_wire")
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obj_nor.out.name = "constant_wire"
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obj_nor.out.prefix = "constant_wire"
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self.add_component(obj_xor)
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self.add_component(obj_xnor)
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self.add_component(obj_nor)
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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obj_fa = full_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), self.get_previous_component().out, prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_fa)
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self.out.connect(input_index, obj_fa.get_sum_wire())
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if input_index == (self.N-1):
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self.out.connect(self.N, obj_fa.get_carry_wire())
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else:
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obj_and = and_gate(self.get_previous_component().get_carry_wire(), self.get_previous_component().propagate.out, prefix=self.prefix+"_and"+str(input_index))
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obj_xor = xor_gate(obj_and.out, self.get_previous_component().generate.out, prefix=self.prefix+"_xor"+str(input_index))
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self.add_component(self.get_previous_component().propagate)
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self.add_component(self.get_previous_component(2).generate)
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self.add_component(obj_and)
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self.add_component(obj_xor)
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# TODO CHANGE!!!
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class signed_carry_lookahead_adder(unsigned_carry_lookahead_adder, arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "s_cla"):
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super().__init__(a=a, b=b, prefix=prefix)
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self.c_data_type = "int64_t"
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# Additional XOR gates to ensure correct sign extension in case of sign addition
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sign_xor_1 = xor_gate(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=xor_gate)))
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self.add_component(sign_xor_1)
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sign_xor_2 = xor_gate(sign_xor_1.out, self.get_previous_component(2).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=xor_gate)))
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self.add_component(sign_xor_2)
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self.out.connect(self.N, sign_xor_2.out)
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# MULTIPLIERS
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class unsigned_array_multiplier(multiplier_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "u_arr_mul"):
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super().__init__()
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self.N = max(a.N, b.N)
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self.a = bus(prefix=a.prefix, wires_list=a.bus)
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self.b = bus(prefix=b.prefix, wires_list=b.bus)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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if prefix == "u_arr_mul":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for multiplication product
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self.out = bus("out", self.N*2)
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# Gradual generation of partial products
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for b_multiplier_index in range(self.N):
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for a_multiplicand_index in range(self.N):
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# AND gates generation for calculation of partial products
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obj_and = and_gate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_and)
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if b_multiplier_index != 0:
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previous_product = self.components[a_multiplicand_index + b_multiplier_index].out if b_multiplier_index == 1 else self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index)
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# HA generation for first 1-bit adder in each row starting from the second one
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if a_multiplicand_index == 0:
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obj_adder = half_adder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# Product generation
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self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
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# HA generation, last 1-bit adder in second row
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elif a_multiplicand_index == self.N-1 and b_multiplier_index == 1:
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obj_adder = half_adder(self.get_previous_component().out, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# FA generation
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else:
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obj_adder = full_adder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# PRODUCT GENERATION
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if a_multiplicand_index == 0 and b_multiplier_index == 0:
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self.out.connect(a_multiplicand_index, obj_and.out)
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# 1 bit multiplier case
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if a_multiplicand_index == self.N-1:
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obj_xor = xor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xor_constant_wire")
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obj_xnor = xnor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xnor_constant_wire")
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obj_and = and_gate(obj_xor.out, obj_xnor.out, prefix=self.prefix+"_and_constant_wire")
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obj_and.out.name = "constant_wire"
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obj_and.out.prefix = "constant_wire"
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self.add_component(obj_xor)
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self.add_component(obj_xnor)
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self.add_component(obj_and)
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self.out.connect(a_multiplicand_index+1, obj_and.out)
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elif b_multiplier_index == self.N-1:
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self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
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if a_multiplicand_index == self.N-1:
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self.out.connect(self.out.N-1, obj_adder.get_carry_wire())
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class signed_array_multiplier(multiplier_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "s_arr_mul"):
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super().__init__()
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self.c_data_type = "int64_t"
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self.N = max(a.N, b.N)
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self.a = bus(prefix=a.prefix, wires_list=a.bus)
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self.b = bus(prefix=b.prefix, wires_list=b.bus)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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if prefix == "s_arr_mul":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for multiplication product
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self.out = bus("out", self.N*2)
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# Generating wire with constant logic value 1 (output of the or gate)
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obj_xor = xor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xor_constant_wire")
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obj_xnor = xnor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xnor_constant_wire")
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obj_or = or_gate(obj_xor.out, obj_xnor.out, prefix=self.prefix+"_or_constant_wire")
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obj_or.out.name = "constant_wire"
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obj_or.out.prefix = "constant_wire"
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self.add_component(obj_xor)
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self.add_component(obj_xnor)
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self.add_component(obj_or)
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# To adjust proper wire connection between adders and AND/NAND gates
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# we add offset equal to first 3 gates in circuits components list (that are present to prevent the need to use constant wire with logic value 1)
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components_offset = 3
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# Gradual generation of partial products
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for b_multiplier_index in range(self.N):
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for a_multiplicand_index in range(self.N):
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# AND and NAND gates generation for calculation of partial products and sign extension
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if (b_multiplier_index == self.N-1 and a_multiplicand_index != self.N-1) or (b_multiplier_index != self.N-1 and a_multiplicand_index == self.N-1):
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obj_nand = nand_gate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_nand"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_nand)
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else:
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obj_and = and_gate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_and)
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if b_multiplier_index != 0:
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previous_product = self.components[a_multiplicand_index + b_multiplier_index + components_offset].out if b_multiplier_index == 1 else self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, offset=components_offset)
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# HA generation for first 1-bit adder in each row starting from the second one
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if a_multiplicand_index == 0:
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obj_adder = half_adder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# Product generation
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self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
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# FA generation
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else:
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if a_multiplicand_index == self.N-1 and b_multiplier_index == 1:
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previous_product = obj_or.out
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obj_adder = full_adder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# PRODUCT GENERATION
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if a_multiplicand_index == 0 and b_multiplier_index == 0:
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self.out.connect(a_multiplicand_index, obj_and.out)
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# 1 bit multiplier case
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if a_multiplicand_index == self.N-1:
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obj_nor = nor_gate(obj_or.out, self.get_previous_component().out, prefix=self.prefix+"_nor_zero_extend")
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self.add_component(obj_nor)
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self.out.connect(a_multiplicand_index+1, obj_nor.out)
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elif b_multiplier_index == self.N-1:
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self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
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if a_multiplicand_index == self.N-1:
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obj_xor = xor_gate(self.get_previous_component().get_carry_wire(), obj_or.out, prefix=self.prefix+"_xor"+str(a_multiplicand_index+1)+"_"+str(b_multiplier_index))
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self.add_component(obj_xor)
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self.out.connect(self.out.N-1, obj_xor.out)
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class unsigned_dadda_multiplier(multiplier_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "u_dadda_mul"):
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super().__init__()
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self.N = max(a.N, b.N)
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self.a = bus(prefix=a.prefix, wires_list=a.bus)
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self.b = bus(prefix=b.prefix, wires_list=b.bus)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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if prefix == "u_dadda_mul" or prefix == "s_dadda_mul":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for multiplication product
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self.out = bus("out", self.N*2)
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# Get starting stage and maximum possible column height
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self.stage, self.d = self.get_maximum_height(initial_value=min(self.a.N, self.b.N))
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self.columns = self.init_column_heights()
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# Perform reduction until stage 0
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for stage in range(self.stage, 0, -1):
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col = 0
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while col < len(self.columns):
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if self.get_column_height(col) == self.d + 1:
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# Add half adder and also and gates if neccesarry (via get_column_wire invocation) into list of circuits components
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obj_adder = half_adder(self.get_column_wire(column=col, bit=1), self.get_column_wire(column=col, bit=2), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=half_adder)))
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self.add_component(obj_adder)
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# Update the number of current and next column wires
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self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
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# Update current and next column wires arrangement
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# add ha's generated sum to the bottom of current column
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# add ha's generated cout to the top of next column
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self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
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elif self.get_column_height(col) > self.d:
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# Add full adder and also and gates if neccesarry (via get_column_wire invocation) into list of circuits components
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obj_adder = full_adder(self.get_column_wire(column=col, bit=1), self.get_column_wire(column=col, bit=2), self.get_column_wire(column=col, bit=3), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=full_adder)))
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self.add_component(obj_adder)
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# Update the number of current and next column wires
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self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
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# Update current and next column wires arrangement
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# add fa's generated sum to the bottom of current column
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# add fa's generated cout to the top of next column
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self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
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# Next iteration with same column in case there is need for further reduction
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col -= 1
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col += 1
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# Update maximum possible column height
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_, self.d = self.get_maximum_height(stage)
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# Output generation
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# Final addition of remaining bits using RCA # TODO add CLA
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self.out.connect(0, self.get_column_wire(column=0, bit=1))
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# 1 bit multiplier case
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if 1 == self.N:
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obj_xor = xor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xor_constant_wire")
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obj_xnor = xnor_gate(self.a.get_wire(), self.b.get_wire(), prefix=self.prefix+"_xnor_constant_wire")
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obj_and = and_gate(obj_xor.out, obj_xnor.out, prefix=self.prefix+"_and_constant_wire")
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obj_and.out.name = "constant_wire"
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obj_and.out.prefix = "constant_wire"
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self.add_component(obj_xor)
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self.add_component(obj_xnor)
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self.add_component(obj_and)
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self.out.connect(1, obj_and.out)
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# 2 bit multiplier case
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elif 2 == self.N:
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obj_ha = half_adder(self.get_column_wire(column=1, bit=1), self.get_column_wire(column=1, bit=2), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=half_adder)))
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self.add_component(obj_ha)
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self.out.connect(1, obj_ha.get_sum_wire())
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obj_ha = half_adder(self.get_previous_component().get_carry_wire(), self.get_column_wire(column=2, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=half_adder)))
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self.add_component(obj_ha)
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self.out.connect(2, obj_ha.get_sum_wire())
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self.out.connect(3, obj_ha.get_carry_wire())
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# Final addition of remaining bits using RCA # TODO add CLA
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else:
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rca_a = bus(prefix="rca_a", wires_list=[self.get_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
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rca_b = bus(prefix="rca_b", wires_list=[self.get_column_wire(column=col, bit=2) for col in range(1, len(self.columns))])
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rca = unsigned_ripple_carry_adder(a=rca_a, b=rca_b, prefix=self.prefix+"_u_rca"+str(len(self.columns)-1))
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self.add_component(rca)
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[self.out.connect(o, rca.out.get_wire(o-1)) for o in range(1, len(self.out.bus))]
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# TODO signed dadda_multiplier
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