honzastor f582ee729e Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations.

2021-10-25 01:11:34 +02:00

..

arithmetic_circuits

Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations.

2021-10-25 01:11:34 +02:00

logic_gate_circuits

Bitwise and operation fix.

2021-10-10 00:02:58 +02:00

one_bit_circuits

Bitwise and operation fix.

2021-10-10 00:02:58 +02:00

__init__.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00