49 lines
1.0 KiB
Verilog
49 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 15:04:26 02/24/2021
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// Design Name: not_gate
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// Module Name: C:/Xilinx_projects/Verilog_generated_circuits/Logic_gates/not_gate_test.v
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// Project Name: Logic_gates
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: not_gate
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module not_gate_test;
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// Inputs
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reg _a;
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// Outputs
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wire _y0;
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// Instantiate the Unit Under Test (UUT)
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not_gate uut (
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._a(_a),
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._y0(_y0)
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);
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initial begin
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// Initialize Inputs
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_a = 1'b0;
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end
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always #2 _a = ~_a;
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initial $monitor("Time:",$time," ns ", "a=%b, y=%b",_a,_y0);
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initial #50 $finish;
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endmodule
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