ariths-gen-mig/.gitignore at a3ba1fca58c2898e12bd198faf3afa7f58ca9b29 - ariths-gen-mig - Gitea: Git with a cup of tea

dissertation_thesis/ariths-gen-mig

root a3ba1fca58 Implemented logic for basic components such as logic gates, bus and wire. From these components were built primary low level 1-bit circuits (half, full adder).

2020-12-10 03:45:46 +01:00

3 lines

21 B

Plaintext

Raw Blame History

	`__pycache__/`
	`test.py`