301 lines
13 KiB
Python
301 lines
13 KiB
Python
from wire_components import wire
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""" LOGIC GATE COMPONENTS """
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# Two-input #
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class logic_gate():
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def __init__(self, a: wire, b: wire, prefix: str = "gate"):
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.b = wire(name=prefix+"_"+b.name.replace(prefix+"_", ""), value=b.value)
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self.prefix = prefix
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def get_component_types(self):
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return list([self])
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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return f"uint8_t {self.gate_type}(uint8_t {self.a.name}, uint8_t {self.b.name})" + "{" + "\n"
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def get_function_c(self):
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return f"{self.a.get_wire_value_c()} {self.operator} {self.b.get_wire_value_c()}"
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def get_declaration_c_flat(self):
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return f"{self.a.get_declaration_c()}{self.b.get_declaration_c()}{self.out.get_declaration_c()}"
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def get_init_c_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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def get_assign_c_flat(self, prefix_a: str = "a", prefix_b: str = "b", offset: int = 0):
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return f" {self.a.name} = {self.a.get_wire_value_c(prefix=prefix_a, offset=offset)};\n" + \
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f" {self.b.name} = {self.b.get_wire_value_c(prefix=prefix_b, offset=offset)};\n" + \
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f" {self.out.prefix} = {self.a.name} {self.operator} {self.b.name};\n"
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# Generating flat C code representation of the logic gate itself
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# (i.e. not as a component of bigger circuit)
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def get_c_code(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(" return "+(self.get_function_c())+";\n}")
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file_object.close()
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# HIERARCHICAL C #
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def get_function_block_c(self):
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return f"{self.get_prototype_c()}" + \
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f" return "+(self.get_function_c())+";\n}\n\n"
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def get_gate_invocation_c(self, a: wire, b: wire, sign: bool = False, get_index: bool = False):
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a_name = a.prefix if sign is False else a.name
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b_name = b.prefix if sign is False else b.name
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a_name = a_name if get_index is False else "a" + a.name[a.name.rfind("_"):]
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b_name = b_name if get_index is False else "b" + b.name[b.name.rfind("_"):]
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return f"{self.gate_type}({a_name}, {b_name});"
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def get_gate_output_c(self, a: wire, b: wire, offset: int = 0, sign: bool = False):
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a_name = a.prefix if sign is False else a.name
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b_name = b.prefix if sign is False else b.name
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return f"({self.gate_type}({a_name}, {b_name}) & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.gate_type}(input {self.a.name}, input {self.b.name}, output {self.out.name});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_declaration_v()}{self.b.get_declaration_v()}{self.out.get_declaration_v()}"
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def get_init_v_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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def get_assign_v_flat(self, prefix_a: str = "a", prefix_b: str = "b", offset: int = 0, array: bool = False):
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return f" assign {self.a.name} = {self.a.get_wire_value_v(prefix=prefix_a, offset=offset, array=array)};\n" + \
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f" assign {self.b.name} = {self.b.get_wire_value_v(prefix=prefix_b, offset=offset, array=array)};\n" + \
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f" assign {self.out.prefix} = {self.a.name} {self.operator} {self.b.name};"
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# Generating flat Verilog code representation of the logic gate itself
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# (i.e. not as a component of bigger circuit)
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def get_v_code(self, file_object):
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file_object.write(self.get_prototype_v())
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file_object.write(f" assign {self.out.name} = {self.get_init_v_flat()};\n")
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file_object.write(f"endmodule")
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file_object.close()
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# HIERARCHICAL VERILOG #
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def get_function_block_v(self):
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return f"{self.get_prototype_v()}" + \
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f" assign {self.out.name} = {self.get_init_v_flat()};\n" + \
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f"endmodule\n\n"
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def get_gate_invocation_v(self, a: wire, b: wire, out: wire, sign: bool = False, get_index: bool = False, out_array: bool = False, offset: int = 0):
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a_name = a.prefix if sign is False else a.name
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b_name = b.prefix if sign is False else b.name
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a_name = a_name if get_index is False else "a" + a.name[a.name.rfind("_"):]
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b_name = b_name if get_index is False else "b" + b.name[b.name.rfind("_"):]
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return f" {self.gate_type} {self.gate_type}_{out.name}({a_name}, {b_name}, {out.get_wire_value_v(offset=offset, array=out_array)});"
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""" CGP CODE GENERATION """
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# FLAT CGP #
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@staticmethod
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def get_parameters_cgp():
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return "{1,1,2,1,0}"
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def get_triplet_cgp(self, a_index: int = 0, b_index: int = 1):
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return f"({a_index},{b_index},{self.cgp_function})"
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@staticmethod
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def get_output_cgp(out_index: int = 2):
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return f"({out_index})"
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def get_cgp_code(self, file_object):
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file_object.write(self.get_parameters_cgp())
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file_object.write(self.get_triplet_cgp())
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file_object.write(self.get_output_cgp())
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file_object.close()
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class inverted_logic_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "gate"):
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super().__init__(a, b, prefix)
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""" C CODE GENERATION """
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# FLAT C #
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def get_function_c(self):
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return "~("+(super().get_function_c())+") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_init_v_flat(self):
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return "~("+(super().get_init_v_flat())+")"
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class and_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "and_gate"
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self.cgp_function = 2
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self.operator = "&"
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self.out = wire(name=prefix+"_y"+str(outid))
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""" C CODE GENERATION """
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# FLAT C #
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def get_assign_c_flat(self, prefix_a: str = "a", prefix_b: str = "b"):
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indexes = self.prefix[self.prefix.rfind("_", 0, self.prefix.rfind("_"))+1:]
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offset_a = indexes[:indexes.rfind("_")]
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offset_b = indexes[indexes.rfind("_")+1:]
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return f" {self.a.name} = {self.a.get_wire_value_c(prefix=prefix_a, offset=offset_a)};\n" + \
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f" {self.b.name} = {self.b.get_wire_value_c(prefix=prefix_b, offset=offset_b)};\n" + \
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f" {self.out.prefix} = {self.a.name} {self.operator} {self.b.name};\n"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_assign_v_flat(self, prefix_a: str = "a", prefix_b: str = "b", offset: int = 0, array: bool = False):
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indexes = self.prefix[self.prefix.rfind("_", 0, self.prefix.rfind("_"))+1:]
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offset_a = indexes[:indexes.rfind("_")]
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offset_b = indexes[indexes.rfind("_")+1:]
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return f" assign {self.a.name} = {self.a.get_wire_value_v(prefix=prefix_a, offset=offset_a, array=array)};\n" + \
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f" assign {self.b.name} = {self.b.get_wire_value_v(prefix=prefix_b, offset=offset_b, array=array)};\n" + \
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f" assign {self.out.prefix} = {self.a.name} {self.operator} {self.b.name};"
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class nand_gate(inverted_logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "nand_gate"
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self.cgp_function = 5
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self.operator = "&"
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self.out = wire(name=prefix+"_y"+str(outid))
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""" C CODE GENERATION """
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# FLAT C #
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def get_assign_c_flat(self, prefix_a: str = "a", prefix_b: str = "b"):
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indexes = self.prefix[self.prefix.rfind("_", 0, self.prefix.rfind("_"))+1:]
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offset_a = indexes[:indexes.rfind("_")]
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offset_b = indexes[indexes.rfind("_")+1:]
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return f" {self.a.name} = {self.a.get_wire_value_c(prefix=prefix_a, offset=offset_a)};\n" + \
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f" {self.b.name} = {self.b.get_wire_value_c(prefix=prefix_b, offset=offset_b)};\n" + \
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f" {self.out.prefix} = ~({self.a.name} {self.operator} {self.b.name});\n"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_assign_v_flat(self, prefix_a: str = "a", prefix_b: str = "b", offset: int = 0, array: bool = False):
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indexes = self.prefix[self.prefix.rfind("_", 0, self.prefix.rfind("_"))+1:]
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offset_a = indexes[:indexes.rfind("_")]
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offset_b = indexes[indexes.rfind("_")+1:]
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return f" assign {self.a.name} = {self.a.get_wire_value_v(prefix=prefix_a, offset=offset_a, array=array)};\n" + \
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f" assign {self.b.name} = {self.b.get_wire_value_v(prefix=prefix_b, offset=offset_b, array=array)};\n" + \
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f" assign {self.out.prefix} = ~({self.a.name} {self.operator} {self.b.name});"
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class or_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "or_gate"
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self.cgp_function = 3
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self.operator = "|"
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self.out = wire(name=prefix+"_y"+str(outid))
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class nor_gate(inverted_logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "nor_gate"
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self.cgp_function = 6
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self.operator = "|"
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self.out = wire(name=prefix+"_y"+str(outid))
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class xor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "xor_gate"
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self.cgp_function = 4
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self.operator = "^"
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self.out = wire(name=prefix+"_y"+str(outid))
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class xnor_gate(inverted_logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "xnor_gate"
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self.cgp_function = 7
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self.operator = "^"
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self.out = wire(name=prefix+"_y"+str(outid))
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# Single-input #
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class not_gate(inverted_logic_gate):
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def __init__(self, a: wire, prefix: str = "", outid: int = 0):
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self.gate_type = "not_gate"
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self.cgp_function = 1
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self.operator = "~"
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.prefix = prefix
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self.out = wire(name=prefix+"_y"+str(outid))
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""" C CODE GENERATION """
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# FLAT C #
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def get_prototype_c(self):
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return f"uint8_t {self.gate_type}(uint8_t {self.a.name})" + "{" + "\n"
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def get_function_c(self):
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return f"{self.operator}{self.a.get_wire_value_c()} & 0x01 << 0"
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def get_declaration_c(self):
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return f"{self.a.get_declaration_c()}{self.out.get_declaration_c()}"
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def get_init_c_flat(self):
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return f"{self.operator}{self.a.name}"
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def get_assign_c_flat(self, prefix_a: str = "a", offset: int = 0):
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return f" {self.a.name} = {self.a.get_wire_value_c(prefix=prefix_a, offset=offset)};\n" + \
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f" {self.out.prefix} = {self.operator}{self.a.name};\n"
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# HIERARCHICAL C #
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def get_gate_invocation_c(self, a: wire, sign: bool = False, get_index: bool = False):
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a_name = a.prefix if sign is False else a.name
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a_name = a_name if get_index is False else "a" + a.name[a.name.rfind("_"):]
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return f"{self.gate_type}({a_name});"
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def get_gate_output_c(self, a: wire, offset: int = 0, sign: bool = False):
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a_name = a.prefix if sign is False else a.name
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return f"({self.gate_type}({a_name}) & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.gate_type}(input {self.a.name}, output {self.out.name});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_declaration_v()}{self.out.get_declaration_v()}"
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def get_init_v_flat(self):
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return f"{self.operator}{self.a.name}"
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def get_assign_v_flat(self, prefix_a: str = "a", offset: int = 0, array: bool = False):
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return f" assign {self.a.name} = {self.a.get_wire_value_v(prefix=prefix_a, offset=offset, array=array)};\n" + \
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f" assign {self.out.prefix} = {self.operator}{self.a.name};"
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# HIERARCHICAL VERILOG #
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def get_gate_invocation_v(self, a: wire, out: wire, sign: bool = False, get_index: bool = False, out_array: bool = False, offset: int = 0):
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a_name = a.prefix if sign is False else a.name
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a_name = a_name if get_index is False else "a" + a.name[a.name.rfind("_"):]
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return f" {self.gate_type} {self.gate_type}_{out.name}({a_name}, {out.get_wire_value_v(offset=offset, array=out_array)});"
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""" CGP CODE GENERATION """
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# FLAT CGP #
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@staticmethod
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def get_parameters_cgp():
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return "{1,1,1,1,0}"
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def get_triplet_cgp(self, a_index: int = 0):
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return f"({a_index},{self.cgp_function})"
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@staticmethod
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def get_output_cgp(out_index: int = 1):
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return f"({out_index})"
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