173 lines
9.6 KiB
Verilog
173 lines
9.6 KiB
Verilog
module or_gate(input a, input b, output out);
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assign out = a | b;
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endmodule
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module and_gate(input a, input b, output out);
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assign out = a & b;
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endmodule
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module xor_gate(input a, input b, output out);
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assign out = a ^ b;
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endmodule
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module pg_logic(input [0:0] a, input [0:0] b, output [0:0] pg_logic_or0, output [0:0] pg_logic_and0, output [0:0] pg_logic_xor0);
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or_gate or_gate_pg_logic_or0(a[0], b[0], pg_logic_or0);
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and_gate and_gate_pg_logic_and0(a[0], b[0], pg_logic_and0);
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xor_gate xor_gate_pg_logic_xor0(a[0], b[0], pg_logic_xor0);
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endmodule
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module h_u_cla8(input [7:0] a, input [7:0] b, output [8:0] h_u_cla8_out);
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wire [0:0] h_u_cla8_pg_logic0_or0;
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wire [0:0] h_u_cla8_pg_logic0_and0;
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wire [0:0] h_u_cla8_pg_logic0_xor0;
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wire [0:0] h_u_cla8_pg_logic1_or0;
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wire [0:0] h_u_cla8_pg_logic1_and0;
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wire [0:0] h_u_cla8_pg_logic1_xor0;
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wire [0:0] h_u_cla8_xor1;
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wire [0:0] h_u_cla8_and0;
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wire [0:0] h_u_cla8_or0;
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wire [0:0] h_u_cla8_pg_logic2_or0;
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wire [0:0] h_u_cla8_pg_logic2_and0;
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wire [0:0] h_u_cla8_pg_logic2_xor0;
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wire [0:0] h_u_cla8_xor2;
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wire [0:0] h_u_cla8_and1;
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wire [0:0] h_u_cla8_and2;
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wire [0:0] h_u_cla8_and3;
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wire [0:0] h_u_cla8_and4;
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wire [0:0] h_u_cla8_or1;
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wire [0:0] h_u_cla8_or2;
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wire [0:0] h_u_cla8_pg_logic3_or0;
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wire [0:0] h_u_cla8_pg_logic3_and0;
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wire [0:0] h_u_cla8_pg_logic3_xor0;
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wire [0:0] h_u_cla8_xor3;
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wire [0:0] h_u_cla8_and5;
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wire [0:0] h_u_cla8_and6;
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wire [0:0] h_u_cla8_and7;
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wire [0:0] h_u_cla8_and8;
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wire [0:0] h_u_cla8_and9;
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wire [0:0] h_u_cla8_and10;
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wire [0:0] h_u_cla8_and11;
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wire [0:0] h_u_cla8_or3;
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wire [0:0] h_u_cla8_or4;
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wire [0:0] h_u_cla8_or5;
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wire [0:0] h_u_cla8_pg_logic4_or0;
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wire [0:0] h_u_cla8_pg_logic4_and0;
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wire [0:0] h_u_cla8_pg_logic4_xor0;
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wire [0:0] h_u_cla8_xor4;
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wire [0:0] h_u_cla8_and12;
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wire [0:0] h_u_cla8_or6;
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wire [0:0] h_u_cla8_pg_logic5_or0;
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wire [0:0] h_u_cla8_pg_logic5_and0;
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wire [0:0] h_u_cla8_pg_logic5_xor0;
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wire [0:0] h_u_cla8_xor5;
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wire [0:0] h_u_cla8_and13;
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wire [0:0] h_u_cla8_and14;
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wire [0:0] h_u_cla8_and15;
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wire [0:0] h_u_cla8_or7;
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wire [0:0] h_u_cla8_or8;
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wire [0:0] h_u_cla8_pg_logic6_or0;
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wire [0:0] h_u_cla8_pg_logic6_and0;
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wire [0:0] h_u_cla8_pg_logic6_xor0;
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wire [0:0] h_u_cla8_xor6;
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wire [0:0] h_u_cla8_and16;
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wire [0:0] h_u_cla8_and17;
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wire [0:0] h_u_cla8_and18;
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wire [0:0] h_u_cla8_and19;
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wire [0:0] h_u_cla8_and20;
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wire [0:0] h_u_cla8_and21;
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wire [0:0] h_u_cla8_or9;
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wire [0:0] h_u_cla8_or10;
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wire [0:0] h_u_cla8_or11;
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wire [0:0] h_u_cla8_pg_logic7_or0;
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wire [0:0] h_u_cla8_pg_logic7_and0;
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wire [0:0] h_u_cla8_pg_logic7_xor0;
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wire [0:0] h_u_cla8_xor7;
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wire [0:0] h_u_cla8_and22;
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wire [0:0] h_u_cla8_and23;
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wire [0:0] h_u_cla8_and24;
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wire [0:0] h_u_cla8_and25;
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wire [0:0] h_u_cla8_and26;
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wire [0:0] h_u_cla8_and27;
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wire [0:0] h_u_cla8_and28;
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wire [0:0] h_u_cla8_and29;
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wire [0:0] h_u_cla8_and30;
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wire [0:0] h_u_cla8_and31;
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wire [0:0] h_u_cla8_or12;
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wire [0:0] h_u_cla8_or13;
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wire [0:0] h_u_cla8_or14;
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wire [0:0] h_u_cla8_or15;
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pg_logic pg_logic_h_u_cla8_pg_logic0_out(a[0], b[0], h_u_cla8_pg_logic0_or0, h_u_cla8_pg_logic0_and0, h_u_cla8_pg_logic0_xor0);
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pg_logic pg_logic_h_u_cla8_pg_logic1_out(a[1], b[1], h_u_cla8_pg_logic1_or0, h_u_cla8_pg_logic1_and0, h_u_cla8_pg_logic1_xor0);
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xor_gate xor_gate_h_u_cla8_xor1(h_u_cla8_pg_logic1_xor0[0], h_u_cla8_pg_logic0_and0[0], h_u_cla8_xor1);
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and_gate and_gate_h_u_cla8_and0(h_u_cla8_pg_logic0_and0[0], h_u_cla8_pg_logic1_or0[0], h_u_cla8_and0);
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or_gate or_gate_h_u_cla8_or0(h_u_cla8_pg_logic1_and0[0], h_u_cla8_and0[0], h_u_cla8_or0);
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pg_logic pg_logic_h_u_cla8_pg_logic2_out(a[2], b[2], h_u_cla8_pg_logic2_or0, h_u_cla8_pg_logic2_and0, h_u_cla8_pg_logic2_xor0);
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xor_gate xor_gate_h_u_cla8_xor2(h_u_cla8_pg_logic2_xor0[0], h_u_cla8_or0[0], h_u_cla8_xor2);
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and_gate and_gate_h_u_cla8_and1(h_u_cla8_pg_logic2_or0[0], h_u_cla8_pg_logic0_or0[0], h_u_cla8_and1);
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and_gate and_gate_h_u_cla8_and2(h_u_cla8_pg_logic0_and0[0], h_u_cla8_pg_logic2_or0[0], h_u_cla8_and2);
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and_gate and_gate_h_u_cla8_and3(h_u_cla8_and2[0], h_u_cla8_pg_logic1_or0[0], h_u_cla8_and3);
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and_gate and_gate_h_u_cla8_and4(h_u_cla8_pg_logic1_and0[0], h_u_cla8_pg_logic2_or0[0], h_u_cla8_and4);
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or_gate or_gate_h_u_cla8_or1(h_u_cla8_and3[0], h_u_cla8_and4[0], h_u_cla8_or1);
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or_gate or_gate_h_u_cla8_or2(h_u_cla8_pg_logic2_and0[0], h_u_cla8_or1[0], h_u_cla8_or2);
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pg_logic pg_logic_h_u_cla8_pg_logic3_out(a[3], b[3], h_u_cla8_pg_logic3_or0, h_u_cla8_pg_logic3_and0, h_u_cla8_pg_logic3_xor0);
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xor_gate xor_gate_h_u_cla8_xor3(h_u_cla8_pg_logic3_xor0[0], h_u_cla8_or2[0], h_u_cla8_xor3);
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and_gate and_gate_h_u_cla8_and5(h_u_cla8_pg_logic3_or0[0], h_u_cla8_pg_logic1_or0[0], h_u_cla8_and5);
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and_gate and_gate_h_u_cla8_and6(h_u_cla8_pg_logic0_and0[0], h_u_cla8_pg_logic2_or0[0], h_u_cla8_and6);
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and_gate and_gate_h_u_cla8_and7(h_u_cla8_pg_logic3_or0[0], h_u_cla8_pg_logic1_or0[0], h_u_cla8_and7);
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and_gate and_gate_h_u_cla8_and8(h_u_cla8_and6[0], h_u_cla8_and7[0], h_u_cla8_and8);
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and_gate and_gate_h_u_cla8_and9(h_u_cla8_pg_logic1_and0[0], h_u_cla8_pg_logic3_or0[0], h_u_cla8_and9);
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and_gate and_gate_h_u_cla8_and10(h_u_cla8_and9[0], h_u_cla8_pg_logic2_or0[0], h_u_cla8_and10);
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and_gate and_gate_h_u_cla8_and11(h_u_cla8_pg_logic2_and0[0], h_u_cla8_pg_logic3_or0[0], h_u_cla8_and11);
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or_gate or_gate_h_u_cla8_or3(h_u_cla8_and8[0], h_u_cla8_and11[0], h_u_cla8_or3);
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or_gate or_gate_h_u_cla8_or4(h_u_cla8_and10[0], h_u_cla8_or3[0], h_u_cla8_or4);
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or_gate or_gate_h_u_cla8_or5(h_u_cla8_pg_logic3_and0[0], h_u_cla8_or4[0], h_u_cla8_or5);
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pg_logic pg_logic_h_u_cla8_pg_logic4_out(a[4], b[4], h_u_cla8_pg_logic4_or0, h_u_cla8_pg_logic4_and0, h_u_cla8_pg_logic4_xor0);
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xor_gate xor_gate_h_u_cla8_xor4(h_u_cla8_pg_logic4_xor0[0], h_u_cla8_or5[0], h_u_cla8_xor4);
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and_gate and_gate_h_u_cla8_and12(h_u_cla8_or5[0], h_u_cla8_pg_logic4_or0[0], h_u_cla8_and12);
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or_gate or_gate_h_u_cla8_or6(h_u_cla8_pg_logic4_and0[0], h_u_cla8_and12[0], h_u_cla8_or6);
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pg_logic pg_logic_h_u_cla8_pg_logic5_out(a[5], b[5], h_u_cla8_pg_logic5_or0, h_u_cla8_pg_logic5_and0, h_u_cla8_pg_logic5_xor0);
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xor_gate xor_gate_h_u_cla8_xor5(h_u_cla8_pg_logic5_xor0[0], h_u_cla8_or6[0], h_u_cla8_xor5);
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and_gate and_gate_h_u_cla8_and13(h_u_cla8_or5[0], h_u_cla8_pg_logic5_or0[0], h_u_cla8_and13);
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and_gate and_gate_h_u_cla8_and14(h_u_cla8_and13[0], h_u_cla8_pg_logic4_or0[0], h_u_cla8_and14);
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and_gate and_gate_h_u_cla8_and15(h_u_cla8_pg_logic4_and0[0], h_u_cla8_pg_logic5_or0[0], h_u_cla8_and15);
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or_gate or_gate_h_u_cla8_or7(h_u_cla8_and14[0], h_u_cla8_and15[0], h_u_cla8_or7);
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or_gate or_gate_h_u_cla8_or8(h_u_cla8_pg_logic5_and0[0], h_u_cla8_or7[0], h_u_cla8_or8);
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pg_logic pg_logic_h_u_cla8_pg_logic6_out(a[6], b[6], h_u_cla8_pg_logic6_or0, h_u_cla8_pg_logic6_and0, h_u_cla8_pg_logic6_xor0);
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xor_gate xor_gate_h_u_cla8_xor6(h_u_cla8_pg_logic6_xor0[0], h_u_cla8_or8[0], h_u_cla8_xor6);
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and_gate and_gate_h_u_cla8_and16(h_u_cla8_or5[0], h_u_cla8_pg_logic5_or0[0], h_u_cla8_and16);
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and_gate and_gate_h_u_cla8_and17(h_u_cla8_pg_logic6_or0[0], h_u_cla8_pg_logic4_or0[0], h_u_cla8_and17);
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and_gate and_gate_h_u_cla8_and18(h_u_cla8_and16[0], h_u_cla8_and17[0], h_u_cla8_and18);
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and_gate and_gate_h_u_cla8_and19(h_u_cla8_pg_logic4_and0[0], h_u_cla8_pg_logic6_or0[0], h_u_cla8_and19);
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and_gate and_gate_h_u_cla8_and20(h_u_cla8_and19[0], h_u_cla8_pg_logic5_or0[0], h_u_cla8_and20);
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and_gate and_gate_h_u_cla8_and21(h_u_cla8_pg_logic5_and0[0], h_u_cla8_pg_logic6_or0[0], h_u_cla8_and21);
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or_gate or_gate_h_u_cla8_or9(h_u_cla8_and18[0], h_u_cla8_and20[0], h_u_cla8_or9);
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or_gate or_gate_h_u_cla8_or10(h_u_cla8_or9[0], h_u_cla8_and21[0], h_u_cla8_or10);
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or_gate or_gate_h_u_cla8_or11(h_u_cla8_pg_logic6_and0[0], h_u_cla8_or10[0], h_u_cla8_or11);
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pg_logic pg_logic_h_u_cla8_pg_logic7_out(a[7], b[7], h_u_cla8_pg_logic7_or0, h_u_cla8_pg_logic7_and0, h_u_cla8_pg_logic7_xor0);
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xor_gate xor_gate_h_u_cla8_xor7(h_u_cla8_pg_logic7_xor0[0], h_u_cla8_or11[0], h_u_cla8_xor7);
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and_gate and_gate_h_u_cla8_and22(h_u_cla8_or5[0], h_u_cla8_pg_logic6_or0[0], h_u_cla8_and22);
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and_gate and_gate_h_u_cla8_and23(h_u_cla8_pg_logic7_or0[0], h_u_cla8_pg_logic5_or0[0], h_u_cla8_and23);
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and_gate and_gate_h_u_cla8_and24(h_u_cla8_and22[0], h_u_cla8_and23[0], h_u_cla8_and24);
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and_gate and_gate_h_u_cla8_and25(h_u_cla8_and24[0], h_u_cla8_pg_logic4_or0[0], h_u_cla8_and25);
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and_gate and_gate_h_u_cla8_and26(h_u_cla8_pg_logic4_and0[0], h_u_cla8_pg_logic6_or0[0], h_u_cla8_and26);
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and_gate and_gate_h_u_cla8_and27(h_u_cla8_pg_logic7_or0[0], h_u_cla8_pg_logic5_or0[0], h_u_cla8_and27);
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and_gate and_gate_h_u_cla8_and28(h_u_cla8_and26[0], h_u_cla8_and27[0], h_u_cla8_and28);
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and_gate and_gate_h_u_cla8_and29(h_u_cla8_pg_logic5_and0[0], h_u_cla8_pg_logic7_or0[0], h_u_cla8_and29);
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and_gate and_gate_h_u_cla8_and30(h_u_cla8_and29[0], h_u_cla8_pg_logic6_or0[0], h_u_cla8_and30);
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and_gate and_gate_h_u_cla8_and31(h_u_cla8_pg_logic6_and0[0], h_u_cla8_pg_logic7_or0[0], h_u_cla8_and31);
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or_gate or_gate_h_u_cla8_or12(h_u_cla8_and25[0], h_u_cla8_and30[0], h_u_cla8_or12);
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or_gate or_gate_h_u_cla8_or13(h_u_cla8_and28[0], h_u_cla8_and31[0], h_u_cla8_or13);
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or_gate or_gate_h_u_cla8_or14(h_u_cla8_or12[0], h_u_cla8_or13[0], h_u_cla8_or14);
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or_gate or_gate_h_u_cla8_or15(h_u_cla8_pg_logic7_and0[0], h_u_cla8_or14[0], h_u_cla8_or15);
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assign h_u_cla8_out[0] = h_u_cla8_pg_logic0_xor0[0];
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assign h_u_cla8_out[1] = h_u_cla8_xor1[0];
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assign h_u_cla8_out[2] = h_u_cla8_xor2[0];
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assign h_u_cla8_out[3] = h_u_cla8_xor3[0];
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assign h_u_cla8_out[4] = h_u_cla8_xor4[0];
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assign h_u_cla8_out[5] = h_u_cla8_xor5[0];
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assign h_u_cla8_out[6] = h_u_cla8_xor6[0];
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assign h_u_cla8_out[7] = h_u_cla8_xor7[0];
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assign h_u_cla8_out[8] = h_u_cla8_or15[0];
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endmodule |