181 lines
8.3 KiB
Verilog
181 lines
8.3 KiB
Verilog
module xor_gate(input _a, input _b, output _y0);
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assign _y0 = _a ^ _b;
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endmodule
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module xnor_gate(input _a, input _b, output _y0);
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assign _y0 = ~(_a ^ _b);
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endmodule
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module nor_gate(input _a, input _b, output _y0);
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assign _y0 = ~(_a | _b);
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endmodule
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module or_gate(input _a, input _b, output _y0);
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assign _y0 = _a | _b;
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endmodule
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module and_gate(input _a, input _b, output _y0);
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assign _y0 = _a & _b;
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endmodule
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module constant_wire_value_0(input a, input b, output constant_wire_0);
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wire constant_wire_value_0_a;
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wire constant_wire_value_0_b;
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wire constant_wire_value_0_y0;
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wire constant_wire_value_0_y1;
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assign constant_wire_value_0_a = a;
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assign constant_wire_value_0_b = b;
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xor_gate xor_gate_constant_wire_value_0_y0(constant_wire_value_0_a, constant_wire_value_0_b, constant_wire_value_0_y0);
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xnor_gate xnor_gate_constant_wire_value_0_y1(constant_wire_value_0_a, constant_wire_value_0_b, constant_wire_value_0_y1);
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nor_gate nor_gate_constant_wire_0(constant_wire_value_0_y0, constant_wire_value_0_y1, constant_wire_0);
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endmodule
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module pg_logic(input a, input b, output pg_logic_y0, output pg_logic_y1, output pg_logic_y2);
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wire pg_logic_a;
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wire pg_logic_b;
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assign pg_logic_a = a;
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assign pg_logic_b = b;
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or_gate or_gate_pg_logic_y0(pg_logic_a, pg_logic_b, pg_logic_y0);
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and_gate and_gate_pg_logic_y1(pg_logic_a, pg_logic_b, pg_logic_y1);
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xor_gate xor_gate_pg_logic_y2(pg_logic_a, pg_logic_b, pg_logic_y2);
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endmodule
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module h_s_cla4(input [3:0] a, input [3:0] b, output [4:0] out);
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wire a_0;
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wire a_1;
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wire a_2;
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wire a_3;
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wire b_0;
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wire b_1;
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wire b_2;
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wire b_3;
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wire constant_wire_0;
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wire h_s_cla4_pg_logic0_y0;
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wire h_s_cla4_pg_logic0_y1;
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wire h_s_cla4_pg_logic0_y2;
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wire h_s_cla4_xor0_y0;
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wire h_s_cla4_and0_y0;
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wire h_s_cla4_or0_y0;
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wire h_s_cla4_pg_logic1_y0;
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wire h_s_cla4_pg_logic1_y1;
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wire h_s_cla4_pg_logic1_y2;
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wire h_s_cla4_xor1_y0;
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wire h_s_cla4_and1_y0;
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wire h_s_cla4_and2_y0;
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wire h_s_cla4_and3_y0;
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wire h_s_cla4_and4_y0;
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wire h_s_cla4_or1_y0;
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wire h_s_cla4_or2_y0;
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wire h_s_cla4_pg_logic2_y0;
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wire h_s_cla4_pg_logic2_y1;
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wire h_s_cla4_pg_logic2_y2;
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wire h_s_cla4_xor2_y0;
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wire h_s_cla4_and5_y0;
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wire h_s_cla4_and6_y0;
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wire h_s_cla4_and7_y0;
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wire h_s_cla4_and8_y0;
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wire h_s_cla4_and9_y0;
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wire h_s_cla4_and10_y0;
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wire h_s_cla4_and11_y0;
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wire h_s_cla4_and12_y0;
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wire h_s_cla4_and13_y0;
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wire h_s_cla4_or3_y0;
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wire h_s_cla4_or4_y0;
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wire h_s_cla4_or5_y0;
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wire h_s_cla4_pg_logic3_y0;
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wire h_s_cla4_pg_logic3_y1;
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wire h_s_cla4_pg_logic3_y2;
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wire h_s_cla4_xor3_y0;
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wire h_s_cla4_and14_y0;
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wire h_s_cla4_and15_y0;
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wire h_s_cla4_and16_y0;
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wire h_s_cla4_and17_y0;
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wire h_s_cla4_and18_y0;
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wire h_s_cla4_and19_y0;
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wire h_s_cla4_and20_y0;
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wire h_s_cla4_and21_y0;
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wire h_s_cla4_and22_y0;
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wire h_s_cla4_and23_y0;
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wire h_s_cla4_and24_y0;
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wire h_s_cla4_and25_y0;
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wire h_s_cla4_and26_y0;
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wire h_s_cla4_and27_y0;
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wire h_s_cla4_and28_y0;
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wire h_s_cla4_and29_y0;
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wire h_s_cla4_or6_y0;
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wire h_s_cla4_or7_y0;
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wire h_s_cla4_or8_y0;
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wire h_s_cla4_or9_y0;
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wire h_s_cla4_xor4_y0;
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wire h_s_cla4_xor5_y0;
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assign a_0 = a[0];
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assign a_1 = a[1];
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assign a_2 = a[2];
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assign a_3 = a[3];
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assign b_0 = b[0];
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assign b_1 = b[1];
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assign b_2 = b[2];
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assign b_3 = b[3];
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constant_wire_value_0 constant_wire_value_0_constant_wire_0(a_0, b_0, constant_wire_0);
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pg_logic pg_logic_h_s_cla4_pg_logic0_y0(a_0, b_0, h_s_cla4_pg_logic0_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_pg_logic0_y2);
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xor_gate xor_gate_h_s_cla4_xor0_y0(h_s_cla4_pg_logic0_y2, constant_wire_0, h_s_cla4_xor0_y0);
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and_gate and_gate_h_s_cla4_and0_y0(h_s_cla4_pg_logic0_y0, constant_wire_0, h_s_cla4_and0_y0);
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or_gate or_gate_h_s_cla4_or0_y0(h_s_cla4_pg_logic0_y1, h_s_cla4_and0_y0, h_s_cla4_or0_y0);
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pg_logic pg_logic_h_s_cla4_pg_logic1_y0(a_1, b_1, h_s_cla4_pg_logic1_y0, h_s_cla4_pg_logic1_y1, h_s_cla4_pg_logic1_y2);
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xor_gate xor_gate_h_s_cla4_xor1_y0(h_s_cla4_pg_logic1_y2, h_s_cla4_or0_y0, h_s_cla4_xor1_y0);
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and_gate and_gate_h_s_cla4_and1_y0(h_s_cla4_pg_logic0_y0, constant_wire_0, h_s_cla4_and1_y0);
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and_gate and_gate_h_s_cla4_and2_y0(h_s_cla4_pg_logic1_y0, constant_wire_0, h_s_cla4_and2_y0);
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and_gate and_gate_h_s_cla4_and3_y0(h_s_cla4_and2_y0, h_s_cla4_and1_y0, h_s_cla4_and3_y0);
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and_gate and_gate_h_s_cla4_and4_y0(h_s_cla4_pg_logic1_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_and4_y0);
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or_gate or_gate_h_s_cla4_or1_y0(h_s_cla4_and4_y0, h_s_cla4_and3_y0, h_s_cla4_or1_y0);
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or_gate or_gate_h_s_cla4_or2_y0(h_s_cla4_pg_logic1_y1, h_s_cla4_or1_y0, h_s_cla4_or2_y0);
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pg_logic pg_logic_h_s_cla4_pg_logic2_y0(a_2, b_2, h_s_cla4_pg_logic2_y0, h_s_cla4_pg_logic2_y1, h_s_cla4_pg_logic2_y2);
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xor_gate xor_gate_h_s_cla4_xor2_y0(h_s_cla4_pg_logic2_y2, h_s_cla4_or2_y0, h_s_cla4_xor2_y0);
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and_gate and_gate_h_s_cla4_and5_y0(h_s_cla4_pg_logic0_y0, constant_wire_0, h_s_cla4_and5_y0);
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and_gate and_gate_h_s_cla4_and6_y0(h_s_cla4_pg_logic1_y0, constant_wire_0, h_s_cla4_and6_y0);
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and_gate and_gate_h_s_cla4_and7_y0(h_s_cla4_and6_y0, h_s_cla4_and5_y0, h_s_cla4_and7_y0);
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and_gate and_gate_h_s_cla4_and8_y0(h_s_cla4_pg_logic2_y0, constant_wire_0, h_s_cla4_and8_y0);
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and_gate and_gate_h_s_cla4_and9_y0(h_s_cla4_and8_y0, h_s_cla4_and7_y0, h_s_cla4_and9_y0);
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and_gate and_gate_h_s_cla4_and10_y0(h_s_cla4_pg_logic1_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_and10_y0);
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and_gate and_gate_h_s_cla4_and11_y0(h_s_cla4_pg_logic2_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_and11_y0);
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and_gate and_gate_h_s_cla4_and12_y0(h_s_cla4_and11_y0, h_s_cla4_and10_y0, h_s_cla4_and12_y0);
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and_gate and_gate_h_s_cla4_and13_y0(h_s_cla4_pg_logic2_y0, h_s_cla4_pg_logic1_y1, h_s_cla4_and13_y0);
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or_gate or_gate_h_s_cla4_or3_y0(h_s_cla4_and13_y0, h_s_cla4_and9_y0, h_s_cla4_or3_y0);
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or_gate or_gate_h_s_cla4_or4_y0(h_s_cla4_or3_y0, h_s_cla4_and12_y0, h_s_cla4_or4_y0);
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or_gate or_gate_h_s_cla4_or5_y0(h_s_cla4_pg_logic2_y1, h_s_cla4_or4_y0, h_s_cla4_or5_y0);
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pg_logic pg_logic_h_s_cla4_pg_logic3_y0(a_3, b_3, h_s_cla4_pg_logic3_y0, h_s_cla4_pg_logic3_y1, h_s_cla4_pg_logic3_y2);
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xor_gate xor_gate_h_s_cla4_xor3_y0(h_s_cla4_pg_logic3_y2, h_s_cla4_or5_y0, h_s_cla4_xor3_y0);
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and_gate and_gate_h_s_cla4_and14_y0(h_s_cla4_pg_logic0_y0, constant_wire_0, h_s_cla4_and14_y0);
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and_gate and_gate_h_s_cla4_and15_y0(h_s_cla4_pg_logic1_y0, constant_wire_0, h_s_cla4_and15_y0);
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and_gate and_gate_h_s_cla4_and16_y0(h_s_cla4_and15_y0, h_s_cla4_and14_y0, h_s_cla4_and16_y0);
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and_gate and_gate_h_s_cla4_and17_y0(h_s_cla4_pg_logic2_y0, constant_wire_0, h_s_cla4_and17_y0);
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and_gate and_gate_h_s_cla4_and18_y0(h_s_cla4_and17_y0, h_s_cla4_and16_y0, h_s_cla4_and18_y0);
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and_gate and_gate_h_s_cla4_and19_y0(h_s_cla4_pg_logic3_y0, constant_wire_0, h_s_cla4_and19_y0);
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and_gate and_gate_h_s_cla4_and20_y0(h_s_cla4_and19_y0, h_s_cla4_and18_y0, h_s_cla4_and20_y0);
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and_gate and_gate_h_s_cla4_and21_y0(h_s_cla4_pg_logic1_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_and21_y0);
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and_gate and_gate_h_s_cla4_and22_y0(h_s_cla4_pg_logic2_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_and22_y0);
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and_gate and_gate_h_s_cla4_and23_y0(h_s_cla4_and22_y0, h_s_cla4_and21_y0, h_s_cla4_and23_y0);
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and_gate and_gate_h_s_cla4_and24_y0(h_s_cla4_pg_logic3_y0, h_s_cla4_pg_logic0_y1, h_s_cla4_and24_y0);
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and_gate and_gate_h_s_cla4_and25_y0(h_s_cla4_and24_y0, h_s_cla4_and23_y0, h_s_cla4_and25_y0);
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and_gate and_gate_h_s_cla4_and26_y0(h_s_cla4_pg_logic2_y0, h_s_cla4_pg_logic1_y1, h_s_cla4_and26_y0);
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and_gate and_gate_h_s_cla4_and27_y0(h_s_cla4_pg_logic3_y0, h_s_cla4_pg_logic1_y1, h_s_cla4_and27_y0);
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and_gate and_gate_h_s_cla4_and28_y0(h_s_cla4_and27_y0, h_s_cla4_and26_y0, h_s_cla4_and28_y0);
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and_gate and_gate_h_s_cla4_and29_y0(h_s_cla4_pg_logic3_y0, h_s_cla4_pg_logic2_y1, h_s_cla4_and29_y0);
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or_gate or_gate_h_s_cla4_or6_y0(h_s_cla4_and29_y0, h_s_cla4_and20_y0, h_s_cla4_or6_y0);
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or_gate or_gate_h_s_cla4_or7_y0(h_s_cla4_or6_y0, h_s_cla4_and25_y0, h_s_cla4_or7_y0);
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or_gate or_gate_h_s_cla4_or8_y0(h_s_cla4_or7_y0, h_s_cla4_and28_y0, h_s_cla4_or8_y0);
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or_gate or_gate_h_s_cla4_or9_y0(h_s_cla4_pg_logic3_y1, h_s_cla4_or8_y0, h_s_cla4_or9_y0);
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xor_gate xor_gate_h_s_cla4_xor4_y0(a_3, b_3, h_s_cla4_xor4_y0);
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xor_gate xor_gate_h_s_cla4_xor5_y0(h_s_cla4_xor4_y0, h_s_cla4_or9_y0, h_s_cla4_xor5_y0);
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assign out[0] = h_s_cla4_xor0_y0;
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assign out[1] = h_s_cla4_xor1_y0;
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assign out[2] = h_s_cla4_xor2_y0;
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assign out[3] = h_s_cla4_xor3_y0;
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assign out[4] = h_s_cla4_xor5_y0;
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endmodule |