268 lines
9.9 KiB
Python
268 lines
9.9 KiB
Python
from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder,
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PGLogicBlock,
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FullAdderPG,
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TwoOneMultiplexer,
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HalfSubtractor,
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FullSubtractor
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)
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from ariths_gen.multi_bit_circuits.adders import (
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UnsignedCarryLookaheadAdder,
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UnsignedPGRippleCarryAdder,
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UnsignedRippleCarryAdder,
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SignedCarryLookaheadAdder,
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SignedPGRippleCarryAdder,
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SignedRippleCarryAdder,
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UnsignedCarrySkipAdder,
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SignedCarrySkipAdder,
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)
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from ariths_gen.multi_bit_circuits.multipliers import (
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UnsignedDaddaMultiplier,
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UnsignedArrayMultiplier,
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UnsignedWallaceMultiplier,
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UnsignedCarrySaveMultiplier,
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SignedArrayMultiplier,
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SignedDaddaMultiplier,
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SignedWallaceMultiplier,
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SignedCarrySaveMultiplier
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)
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from ariths_gen.multi_bit_circuits.dividers import (
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ArrayDivider
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)
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import sys
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import os
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def prepare_directory(path):
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os.makedirs(os.path.dirname(path), exist_ok=True)
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return open(path, "w")
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def export_circuit(circuit, name):
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directory = "test_circuits"
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print(f"# exporting {name}")
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circuit.get_v_code_flat(prepare_directory(f"{directory}/verilog_circuits/flat/{name}.v"))
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circuit.get_v_code_hier(prepare_directory(f"{directory}/verilog_circuits/hier/{name}.v"))
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circuit.get_c_code_hier(prepare_directory(f"{directory}/c_circuits/hier/{name}.c"))
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circuit.get_c_code_flat(prepare_directory(f"{directory}/c_circuits/flat/{name}.c"))
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circuit.get_blif_code_hier(prepare_directory(f"{directory}/blif_circuits/hier/{name}.blif"))
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circuit.get_blif_code_flat(prepare_directory(f"{directory}/blif_circuits/flat/{name}.blif"))
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circuit.get_cgp_code_flat(prepare_directory(f"{directory}/cgp_circuits/flat/{name}.cgp"))
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""" Generation of circuits """
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if __name__ == "__main__":
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for N in [8]:
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a = Bus(N=N, prefix="a")
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b = Bus(N=N, prefix="b")
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representation = "h"
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""" ADDERS """
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# RCA
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name = f"u_rca{N}"
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circuit = UnsignedRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_rca{N}"
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circuit = SignedRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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# RCA with PG
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name = f"u_pg_rca{N}"
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circuit = UnsignedPGRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_pg_rca{N}"
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circuit = SignedPGRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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# CSKA with 4 bit CSKA blocks (default)
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name = f"u_cska{N}"
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circuit = UnsignedCarrySkipAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_cska{N}"
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circuit = SignedCarrySkipAdder(a, b, name=name)
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export_circuit(circuit, name)
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# CLA with 4 bit CLA blocks (default)
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name = f"u_cla{N}"
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circuit = UnsignedCarryLookaheadAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_cla{N}"
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circuit = SignedCarryLookaheadAdder(a, b, name=name)
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export_circuit(circuit, name)
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""" MULTIPLIERS """
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# Arrmul
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name = f"u_arrmul{N}"
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circuit = UnsignedArrayMultiplier(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_arrmul{N}"
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circuit = SignedArrayMultiplier(a, b, name=name)
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export_circuit(circuit, name)
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# Csamul (Braun multiplier)
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name = f"u_csamul_cla{N}"
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circuit = UnsignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"s_csamul_cla{N}"
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circuit = SignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"u_csamul_rca{N}"
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circuit = UnsignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_csamul_rca{N}"
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circuit = SignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_csamul_pg_rca{N}"
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circuit = UnsignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_csamul_pg_rca{N}"
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circuit = SignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_csamul_cska{N}"
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circuit = UnsignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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name = f"s_csamul_cska{N}"
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circuit = SignedCarrySaveMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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# Wallace implemented with interconnected HAs/FAs
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name = f"u_wallace_cla{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_cla{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"u_wallace_rca{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_rca{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_wallace_pg_rca{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_pg_rca{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_wallace_cska{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_cska{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, use_csa=False, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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# Wallace implemented with interconnected CSAs (default choice)
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name = f"u_CSAwallace_cla{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"s_CSAwallace_cla{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"u_CSAwallace_rca{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_CSAwallace_rca{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_CSAwallace_pg_rca{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_CSAwallace_pg_rca{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_CSAwallace_cska{N}"
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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name = f"s_CSAwallace_cska{N}"
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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# Dadda with interconnected HAs/FAs
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name = f"u_dadda_cla{N}"
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_cla{N}"
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"u_dadda_rca{N}"
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_rca{N}"
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_dadda_pg_rca{N}"
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_pg_rca{N}"
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_dadda_cska{N}"
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_cska{N}"
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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""" DIVIDERS """
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# Arrdiv
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name = f"arrdiv{N}"
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circuit = ArrayDivider(a, b, name=name)
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export_circuit(circuit, name)
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