83 lines
2.0 KiB
Python
83 lines
2.0 KiB
Python
"""
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"""
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus,
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wires
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)
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from ariths_gen.core.arithmetic_circuits import (
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ArithmeticCircuit,
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GeneralCircuit,
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MultiplierCircuit
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)
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from ariths_gen.core.logic_gate_circuits import (
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MultipleInputLogicGate
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder,
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FullAdderP,
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TwoOneMultiplexer
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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from ariths_gen.multi_bit_circuits.others import OrReduce
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from math import log2, ceil
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class UnsignedCompareLT(GeneralCircuit):
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"""Class representing unsigned compare
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Returns true if a < b
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"""
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def __init__(self, a: Bus, b: Bus, prefix : str = "", name : str = "cmp_lt", **kwargs):
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self.a = a
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self.b = b
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self.N = max(a.N, b.N)
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#print("outc", outc)
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super().__init__(name=name, prefix=prefix,
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inputs = [self.a, self.b], out_N=1)
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self.a.bus_extend(self.N, prefix=a.prefix)
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self.b.bus_extend(self.N, prefix=b.prefix)
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# create wires
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psum = ConstantWireValue1()
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res = Bus(N = self.N, prefix=self.prefix + "res")
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for i in reversed(range(self.N)):
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i1 = self.add_component(NotGate(self.a[i], f"{self.prefix}_i1_{i}")).out
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i2 = self.b[i]
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and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
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res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
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pi = self.add_component(XnorGate(self.a[i], self.b[i], f"{self.prefix}_pi_{i}")).out
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psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
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self.out = self.add_component(OrReduce(res, prefix=f"{self.prefix}_orred")).out
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#self.out.connect_bus(sumbus ) |