89 lines
2.5 KiB
Python
89 lines
2.5 KiB
Python
"""
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"""
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus,
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wires
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)
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from ariths_gen.core.arithmetic_circuits import (
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ArithmeticCircuit,
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GeneralCircuit,
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MultiplierCircuit
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)
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from ariths_gen.core.logic_gate_circuits import (
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MultipleInputLogicGate
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder,
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FullAdderP,
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TwoOneMultiplexer
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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from ariths_gen.core.logic_gate_circuits import TwoInputLogicGate, TwoInputInvertedLogicGate, OneInputLogicGate
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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from math import log2, ceil
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class BitReduce(GeneralCircuit):
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"""Class representing tree reducer circuit. Doent work for NAND gate!
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"""
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def __init__(self, a: Bus, gate : TwoInputLogicGate, prefix : str = "", name : str = "bitreduce", **kwargs):
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self.N = a.N
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self.a = a
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outc = 1
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super().__init__(name=name, prefix=prefix, inputs = [self.a], out_N=outc)
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# tree reduction
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def create_tree(a: Bus, depth: int, branch="A"):
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#print(a)
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if a.N == 1:
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return a[0]
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else:
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half = a.N // 2
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b_in = Bus(N=half, prefix=f"b_inn{depth}A")
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c_in = Bus(N=a.N - half, prefix=f"b_inn{depth}B")
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#print(a, half, a.N)
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for i, j in enumerate(range(half)):
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b_in[i] = a[j]
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for i, j in enumerate(range(half, a.N)):
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c_in[i] = a[j]
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b = create_tree(b_in, depth=depth + 1, branch = "A")
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c = create_tree(c_in, depth= depth + 1, branch = "B")
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d = gate(a=b, b=c, prefix = f"{self.prefix}_red_{branch}_{depth}")
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self.add_component(d)
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return d.out
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sumwire = create_tree(self.a, 0, "X")
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#print(sumbus)
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self.out[0] = sumwire
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class OrReduce(BitReduce):
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def __init__(self, a: Bus, prefix : str = "", name : str = "orreduce", **kwargs):
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super().__init__(a=a, gate=OrGate, prefix=prefix, name=name, **kwargs)
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class AndReduce(BitReduce):
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def __init__(self, a: Bus, prefix : str = "", name : str = "orreduce", **kwargs):
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super().__init__(a=a, gate=AndGate, prefix=prefix, name=name, **kwargs) |