56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
26 lines
1.3 KiB
Python
26 lines
1.3 KiB
Python
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from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.wire_components import Bus, Wire
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier
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import os
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class MAC(GeneralCircuit):
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def __init__(self, a: Bus, b: Bus, r: Bus, prefix: str = "", name: str = "mac", **kwargs):
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super().__init__(prefix=prefix, name=name, out_N=2*a.N+1, inputs=[a, b, r], **kwargs)
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assert a.N == b.N
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assert r.N == 2 * a.N
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self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
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self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
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self.out.connect_bus(connecting_bus=self.add.out)
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# usage
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if __name__ == "__main__":
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os.makedirs("test_circuits/mac", exist_ok=True)
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mymac = MAC(Bus("a", 8), Bus("b", 8), Bus("acc", 16), outname="mac_output")
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mymac.get_v_code_hier(open("test_circuits/mac/mac_hier.v", "w"))
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mymac.get_c_code_hier(open("test_circuits/mac/mac_hier.c", "w"))
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mymac.get_c_code_flat(open("test_circuits/mac/mac_flat.c", "w"))
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