751 lines
34 KiB
Verilog
751 lines
34 KiB
Verilog
module f_s_cla32(input [31:0] a, input [31:0] b, output [32:0] f_s_cla32_out);
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wire f_s_cla32_pg_logic0_or0;
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wire f_s_cla32_pg_logic0_and0;
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wire f_s_cla32_pg_logic0_xor0;
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wire f_s_cla32_pg_logic1_or0;
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wire f_s_cla32_pg_logic1_and0;
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wire f_s_cla32_pg_logic1_xor0;
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wire f_s_cla32_xor1;
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wire f_s_cla32_and0;
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wire f_s_cla32_or0;
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wire f_s_cla32_pg_logic2_or0;
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wire f_s_cla32_pg_logic2_and0;
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wire f_s_cla32_pg_logic2_xor0;
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wire f_s_cla32_xor2;
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wire f_s_cla32_and1;
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wire f_s_cla32_and2;
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wire f_s_cla32_and3;
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wire f_s_cla32_and4;
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wire f_s_cla32_or1;
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wire f_s_cla32_or2;
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wire f_s_cla32_pg_logic3_or0;
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wire f_s_cla32_pg_logic3_and0;
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wire f_s_cla32_pg_logic3_xor0;
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wire f_s_cla32_xor3;
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wire f_s_cla32_and5;
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wire f_s_cla32_and6;
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wire f_s_cla32_and7;
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wire f_s_cla32_and8;
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wire f_s_cla32_and9;
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wire f_s_cla32_and10;
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wire f_s_cla32_and11;
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wire f_s_cla32_or3;
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wire f_s_cla32_or4;
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wire f_s_cla32_or5;
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wire f_s_cla32_pg_logic4_or0;
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wire f_s_cla32_pg_logic4_and0;
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wire f_s_cla32_pg_logic4_xor0;
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wire f_s_cla32_xor4;
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wire f_s_cla32_and12;
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wire f_s_cla32_or6;
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wire f_s_cla32_pg_logic5_or0;
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wire f_s_cla32_pg_logic5_and0;
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wire f_s_cla32_pg_logic5_xor0;
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wire f_s_cla32_xor5;
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wire f_s_cla32_and13;
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wire f_s_cla32_and14;
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wire f_s_cla32_and15;
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wire f_s_cla32_or7;
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wire f_s_cla32_or8;
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wire f_s_cla32_pg_logic6_or0;
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wire f_s_cla32_pg_logic6_and0;
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wire f_s_cla32_pg_logic6_xor0;
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wire f_s_cla32_xor6;
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wire f_s_cla32_and16;
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wire f_s_cla32_and17;
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wire f_s_cla32_and18;
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wire f_s_cla32_and19;
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wire f_s_cla32_and20;
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wire f_s_cla32_and21;
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wire f_s_cla32_or9;
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wire f_s_cla32_or10;
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wire f_s_cla32_or11;
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wire f_s_cla32_pg_logic7_or0;
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wire f_s_cla32_pg_logic7_and0;
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wire f_s_cla32_pg_logic7_xor0;
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wire f_s_cla32_xor7;
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wire f_s_cla32_and22;
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wire f_s_cla32_and23;
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wire f_s_cla32_and24;
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wire f_s_cla32_and25;
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wire f_s_cla32_and26;
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wire f_s_cla32_and27;
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wire f_s_cla32_and28;
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wire f_s_cla32_and29;
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wire f_s_cla32_and30;
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wire f_s_cla32_and31;
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wire f_s_cla32_or12;
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wire f_s_cla32_or13;
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wire f_s_cla32_or14;
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wire f_s_cla32_or15;
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wire f_s_cla32_pg_logic8_or0;
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wire f_s_cla32_pg_logic8_and0;
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wire f_s_cla32_pg_logic8_xor0;
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wire f_s_cla32_xor8;
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wire f_s_cla32_and32;
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wire f_s_cla32_or16;
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wire f_s_cla32_pg_logic9_or0;
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wire f_s_cla32_pg_logic9_and0;
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wire f_s_cla32_pg_logic9_xor0;
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wire f_s_cla32_xor9;
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wire f_s_cla32_and33;
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wire f_s_cla32_and34;
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wire f_s_cla32_and35;
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wire f_s_cla32_or17;
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wire f_s_cla32_or18;
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wire f_s_cla32_pg_logic10_or0;
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wire f_s_cla32_pg_logic10_and0;
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wire f_s_cla32_pg_logic10_xor0;
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wire f_s_cla32_xor10;
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wire f_s_cla32_and36;
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wire f_s_cla32_and37;
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wire f_s_cla32_and38;
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wire f_s_cla32_and39;
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wire f_s_cla32_and40;
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wire f_s_cla32_and41;
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wire f_s_cla32_or19;
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wire f_s_cla32_or20;
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wire f_s_cla32_or21;
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wire f_s_cla32_pg_logic11_or0;
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wire f_s_cla32_pg_logic11_and0;
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wire f_s_cla32_pg_logic11_xor0;
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wire f_s_cla32_xor11;
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wire f_s_cla32_and42;
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wire f_s_cla32_and43;
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wire f_s_cla32_and44;
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wire f_s_cla32_and45;
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wire f_s_cla32_and46;
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wire f_s_cla32_and47;
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wire f_s_cla32_and48;
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wire f_s_cla32_and49;
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wire f_s_cla32_and50;
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wire f_s_cla32_and51;
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wire f_s_cla32_or22;
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wire f_s_cla32_or23;
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wire f_s_cla32_or24;
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wire f_s_cla32_or25;
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wire f_s_cla32_pg_logic12_or0;
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wire f_s_cla32_pg_logic12_and0;
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wire f_s_cla32_pg_logic12_xor0;
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wire f_s_cla32_xor12;
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wire f_s_cla32_and52;
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wire f_s_cla32_or26;
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wire f_s_cla32_pg_logic13_or0;
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wire f_s_cla32_pg_logic13_and0;
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wire f_s_cla32_pg_logic13_xor0;
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wire f_s_cla32_xor13;
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wire f_s_cla32_and53;
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wire f_s_cla32_and54;
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wire f_s_cla32_and55;
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wire f_s_cla32_or27;
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wire f_s_cla32_or28;
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wire f_s_cla32_pg_logic14_or0;
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wire f_s_cla32_pg_logic14_and0;
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wire f_s_cla32_pg_logic14_xor0;
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wire f_s_cla32_xor14;
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wire f_s_cla32_and56;
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wire f_s_cla32_and57;
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wire f_s_cla32_and58;
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wire f_s_cla32_and59;
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wire f_s_cla32_and60;
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wire f_s_cla32_and61;
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wire f_s_cla32_or29;
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wire f_s_cla32_or30;
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wire f_s_cla32_or31;
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wire f_s_cla32_pg_logic15_or0;
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wire f_s_cla32_pg_logic15_and0;
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wire f_s_cla32_pg_logic15_xor0;
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wire f_s_cla32_xor15;
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wire f_s_cla32_and62;
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wire f_s_cla32_and63;
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wire f_s_cla32_and64;
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wire f_s_cla32_and65;
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wire f_s_cla32_and66;
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wire f_s_cla32_and67;
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wire f_s_cla32_and68;
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wire f_s_cla32_and69;
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wire f_s_cla32_and70;
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wire f_s_cla32_and71;
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wire f_s_cla32_or32;
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wire f_s_cla32_or33;
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wire f_s_cla32_or34;
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wire f_s_cla32_or35;
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wire f_s_cla32_pg_logic16_or0;
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wire f_s_cla32_pg_logic16_and0;
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wire f_s_cla32_pg_logic16_xor0;
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wire f_s_cla32_xor16;
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wire f_s_cla32_and72;
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wire f_s_cla32_or36;
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wire f_s_cla32_pg_logic17_or0;
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wire f_s_cla32_pg_logic17_and0;
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wire f_s_cla32_pg_logic17_xor0;
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wire f_s_cla32_xor17;
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wire f_s_cla32_and73;
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wire f_s_cla32_and74;
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wire f_s_cla32_and75;
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wire f_s_cla32_or37;
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wire f_s_cla32_or38;
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wire f_s_cla32_pg_logic18_or0;
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wire f_s_cla32_pg_logic18_and0;
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wire f_s_cla32_pg_logic18_xor0;
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wire f_s_cla32_xor18;
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wire f_s_cla32_and76;
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wire f_s_cla32_and77;
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wire f_s_cla32_and78;
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wire f_s_cla32_and79;
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wire f_s_cla32_and80;
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wire f_s_cla32_and81;
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wire f_s_cla32_or39;
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wire f_s_cla32_or40;
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wire f_s_cla32_or41;
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wire f_s_cla32_pg_logic19_or0;
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wire f_s_cla32_pg_logic19_and0;
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wire f_s_cla32_pg_logic19_xor0;
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wire f_s_cla32_xor19;
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wire f_s_cla32_and82;
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wire f_s_cla32_and83;
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wire f_s_cla32_and84;
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wire f_s_cla32_and85;
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wire f_s_cla32_and86;
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wire f_s_cla32_and87;
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wire f_s_cla32_and88;
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wire f_s_cla32_and89;
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wire f_s_cla32_and90;
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wire f_s_cla32_and91;
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wire f_s_cla32_or42;
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wire f_s_cla32_or43;
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wire f_s_cla32_or44;
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wire f_s_cla32_or45;
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wire f_s_cla32_pg_logic20_or0;
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wire f_s_cla32_pg_logic20_and0;
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wire f_s_cla32_pg_logic20_xor0;
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wire f_s_cla32_xor20;
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wire f_s_cla32_and92;
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wire f_s_cla32_or46;
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wire f_s_cla32_pg_logic21_or0;
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wire f_s_cla32_pg_logic21_and0;
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wire f_s_cla32_pg_logic21_xor0;
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wire f_s_cla32_xor21;
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wire f_s_cla32_and93;
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wire f_s_cla32_and94;
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wire f_s_cla32_and95;
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wire f_s_cla32_or47;
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wire f_s_cla32_or48;
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wire f_s_cla32_pg_logic22_or0;
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wire f_s_cla32_pg_logic22_and0;
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wire f_s_cla32_pg_logic22_xor0;
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wire f_s_cla32_xor22;
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wire f_s_cla32_and96;
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wire f_s_cla32_and97;
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wire f_s_cla32_and98;
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wire f_s_cla32_and99;
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wire f_s_cla32_and100;
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wire f_s_cla32_and101;
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wire f_s_cla32_or49;
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wire f_s_cla32_or50;
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wire f_s_cla32_or51;
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wire f_s_cla32_pg_logic23_or0;
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wire f_s_cla32_pg_logic23_and0;
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wire f_s_cla32_pg_logic23_xor0;
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wire f_s_cla32_xor23;
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wire f_s_cla32_and102;
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wire f_s_cla32_and103;
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wire f_s_cla32_and104;
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wire f_s_cla32_and105;
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wire f_s_cla32_and106;
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wire f_s_cla32_and107;
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wire f_s_cla32_and108;
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wire f_s_cla32_and109;
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wire f_s_cla32_and110;
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wire f_s_cla32_and111;
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wire f_s_cla32_or52;
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wire f_s_cla32_or53;
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wire f_s_cla32_or54;
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wire f_s_cla32_or55;
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wire f_s_cla32_pg_logic24_or0;
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wire f_s_cla32_pg_logic24_and0;
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wire f_s_cla32_pg_logic24_xor0;
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wire f_s_cla32_xor24;
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wire f_s_cla32_and112;
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wire f_s_cla32_or56;
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wire f_s_cla32_pg_logic25_or0;
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wire f_s_cla32_pg_logic25_and0;
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wire f_s_cla32_pg_logic25_xor0;
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wire f_s_cla32_xor25;
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wire f_s_cla32_and113;
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wire f_s_cla32_and114;
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wire f_s_cla32_and115;
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wire f_s_cla32_or57;
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wire f_s_cla32_or58;
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wire f_s_cla32_pg_logic26_or0;
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wire f_s_cla32_pg_logic26_and0;
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wire f_s_cla32_pg_logic26_xor0;
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wire f_s_cla32_xor26;
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wire f_s_cla32_and116;
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wire f_s_cla32_and117;
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wire f_s_cla32_and118;
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wire f_s_cla32_and119;
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wire f_s_cla32_and120;
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wire f_s_cla32_and121;
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wire f_s_cla32_or59;
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wire f_s_cla32_or60;
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wire f_s_cla32_or61;
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wire f_s_cla32_pg_logic27_or0;
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wire f_s_cla32_pg_logic27_and0;
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wire f_s_cla32_pg_logic27_xor0;
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wire f_s_cla32_xor27;
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wire f_s_cla32_and122;
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wire f_s_cla32_and123;
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wire f_s_cla32_and124;
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wire f_s_cla32_and125;
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wire f_s_cla32_and126;
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wire f_s_cla32_and127;
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wire f_s_cla32_and128;
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wire f_s_cla32_and129;
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wire f_s_cla32_and130;
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wire f_s_cla32_and131;
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wire f_s_cla32_or62;
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wire f_s_cla32_or63;
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wire f_s_cla32_or64;
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wire f_s_cla32_or65;
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wire f_s_cla32_pg_logic28_or0;
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wire f_s_cla32_pg_logic28_and0;
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wire f_s_cla32_pg_logic28_xor0;
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wire f_s_cla32_xor28;
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wire f_s_cla32_and132;
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wire f_s_cla32_or66;
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wire f_s_cla32_pg_logic29_or0;
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wire f_s_cla32_pg_logic29_and0;
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wire f_s_cla32_pg_logic29_xor0;
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wire f_s_cla32_xor29;
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wire f_s_cla32_and133;
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wire f_s_cla32_and134;
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wire f_s_cla32_and135;
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wire f_s_cla32_or67;
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wire f_s_cla32_or68;
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wire f_s_cla32_pg_logic30_or0;
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wire f_s_cla32_pg_logic30_and0;
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wire f_s_cla32_pg_logic30_xor0;
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wire f_s_cla32_xor30;
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wire f_s_cla32_and136;
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wire f_s_cla32_and137;
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wire f_s_cla32_and138;
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wire f_s_cla32_and139;
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wire f_s_cla32_and140;
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wire f_s_cla32_and141;
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wire f_s_cla32_or69;
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wire f_s_cla32_or70;
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wire f_s_cla32_or71;
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wire f_s_cla32_pg_logic31_or0;
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wire f_s_cla32_pg_logic31_and0;
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wire f_s_cla32_pg_logic31_xor0;
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wire f_s_cla32_xor31;
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wire f_s_cla32_and142;
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wire f_s_cla32_and143;
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wire f_s_cla32_and144;
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wire f_s_cla32_and145;
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wire f_s_cla32_and146;
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wire f_s_cla32_and147;
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wire f_s_cla32_and148;
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wire f_s_cla32_and149;
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wire f_s_cla32_and150;
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wire f_s_cla32_and151;
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wire f_s_cla32_or72;
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wire f_s_cla32_or73;
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wire f_s_cla32_or74;
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wire f_s_cla32_or75;
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wire f_s_cla32_xor32;
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wire f_s_cla32_xor33;
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assign f_s_cla32_pg_logic0_or0 = a[0] | b[0];
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assign f_s_cla32_pg_logic0_and0 = a[0] & b[0];
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assign f_s_cla32_pg_logic0_xor0 = a[0] ^ b[0];
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assign f_s_cla32_pg_logic1_or0 = a[1] | b[1];
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assign f_s_cla32_pg_logic1_and0 = a[1] & b[1];
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assign f_s_cla32_pg_logic1_xor0 = a[1] ^ b[1];
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assign f_s_cla32_xor1 = f_s_cla32_pg_logic1_xor0 ^ f_s_cla32_pg_logic0_and0;
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assign f_s_cla32_and0 = f_s_cla32_pg_logic0_and0 & f_s_cla32_pg_logic1_or0;
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assign f_s_cla32_or0 = f_s_cla32_pg_logic1_and0 | f_s_cla32_and0;
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assign f_s_cla32_pg_logic2_or0 = a[2] | b[2];
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assign f_s_cla32_pg_logic2_and0 = a[2] & b[2];
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assign f_s_cla32_pg_logic2_xor0 = a[2] ^ b[2];
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assign f_s_cla32_xor2 = f_s_cla32_pg_logic2_xor0 ^ f_s_cla32_or0;
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assign f_s_cla32_and1 = f_s_cla32_pg_logic2_or0 & f_s_cla32_pg_logic0_or0;
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assign f_s_cla32_and2 = f_s_cla32_pg_logic0_and0 & f_s_cla32_pg_logic2_or0;
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assign f_s_cla32_and3 = f_s_cla32_and2 & f_s_cla32_pg_logic1_or0;
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assign f_s_cla32_and4 = f_s_cla32_pg_logic1_and0 & f_s_cla32_pg_logic2_or0;
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assign f_s_cla32_or1 = f_s_cla32_and3 | f_s_cla32_and4;
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assign f_s_cla32_or2 = f_s_cla32_pg_logic2_and0 | f_s_cla32_or1;
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assign f_s_cla32_pg_logic3_or0 = a[3] | b[3];
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assign f_s_cla32_pg_logic3_and0 = a[3] & b[3];
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assign f_s_cla32_pg_logic3_xor0 = a[3] ^ b[3];
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assign f_s_cla32_xor3 = f_s_cla32_pg_logic3_xor0 ^ f_s_cla32_or2;
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assign f_s_cla32_and5 = f_s_cla32_pg_logic3_or0 & f_s_cla32_pg_logic1_or0;
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assign f_s_cla32_and6 = f_s_cla32_pg_logic0_and0 & f_s_cla32_pg_logic2_or0;
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assign f_s_cla32_and7 = f_s_cla32_pg_logic3_or0 & f_s_cla32_pg_logic1_or0;
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assign f_s_cla32_and8 = f_s_cla32_and6 & f_s_cla32_and7;
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assign f_s_cla32_and9 = f_s_cla32_pg_logic1_and0 & f_s_cla32_pg_logic3_or0;
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assign f_s_cla32_and10 = f_s_cla32_and9 & f_s_cla32_pg_logic2_or0;
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assign f_s_cla32_and11 = f_s_cla32_pg_logic2_and0 & f_s_cla32_pg_logic3_or0;
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assign f_s_cla32_or3 = f_s_cla32_and8 | f_s_cla32_and11;
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assign f_s_cla32_or4 = f_s_cla32_and10 | f_s_cla32_or3;
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assign f_s_cla32_or5 = f_s_cla32_pg_logic3_and0 | f_s_cla32_or4;
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assign f_s_cla32_pg_logic4_or0 = a[4] | b[4];
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assign f_s_cla32_pg_logic4_and0 = a[4] & b[4];
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assign f_s_cla32_pg_logic4_xor0 = a[4] ^ b[4];
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assign f_s_cla32_xor4 = f_s_cla32_pg_logic4_xor0 ^ f_s_cla32_or5;
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assign f_s_cla32_and12 = f_s_cla32_or5 & f_s_cla32_pg_logic4_or0;
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assign f_s_cla32_or6 = f_s_cla32_pg_logic4_and0 | f_s_cla32_and12;
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assign f_s_cla32_pg_logic5_or0 = a[5] | b[5];
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assign f_s_cla32_pg_logic5_and0 = a[5] & b[5];
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assign f_s_cla32_pg_logic5_xor0 = a[5] ^ b[5];
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assign f_s_cla32_xor5 = f_s_cla32_pg_logic5_xor0 ^ f_s_cla32_or6;
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assign f_s_cla32_and13 = f_s_cla32_or5 & f_s_cla32_pg_logic5_or0;
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assign f_s_cla32_and14 = f_s_cla32_and13 & f_s_cla32_pg_logic4_or0;
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assign f_s_cla32_and15 = f_s_cla32_pg_logic4_and0 & f_s_cla32_pg_logic5_or0;
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assign f_s_cla32_or7 = f_s_cla32_and14 | f_s_cla32_and15;
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assign f_s_cla32_or8 = f_s_cla32_pg_logic5_and0 | f_s_cla32_or7;
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assign f_s_cla32_pg_logic6_or0 = a[6] | b[6];
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assign f_s_cla32_pg_logic6_and0 = a[6] & b[6];
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assign f_s_cla32_pg_logic6_xor0 = a[6] ^ b[6];
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assign f_s_cla32_xor6 = f_s_cla32_pg_logic6_xor0 ^ f_s_cla32_or8;
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assign f_s_cla32_and16 = f_s_cla32_or5 & f_s_cla32_pg_logic5_or0;
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assign f_s_cla32_and17 = f_s_cla32_pg_logic6_or0 & f_s_cla32_pg_logic4_or0;
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assign f_s_cla32_and18 = f_s_cla32_and16 & f_s_cla32_and17;
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assign f_s_cla32_and19 = f_s_cla32_pg_logic4_and0 & f_s_cla32_pg_logic6_or0;
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assign f_s_cla32_and20 = f_s_cla32_and19 & f_s_cla32_pg_logic5_or0;
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assign f_s_cla32_and21 = f_s_cla32_pg_logic5_and0 & f_s_cla32_pg_logic6_or0;
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assign f_s_cla32_or9 = f_s_cla32_and18 | f_s_cla32_and20;
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assign f_s_cla32_or10 = f_s_cla32_or9 | f_s_cla32_and21;
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assign f_s_cla32_or11 = f_s_cla32_pg_logic6_and0 | f_s_cla32_or10;
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assign f_s_cla32_pg_logic7_or0 = a[7] | b[7];
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assign f_s_cla32_pg_logic7_and0 = a[7] & b[7];
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assign f_s_cla32_pg_logic7_xor0 = a[7] ^ b[7];
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assign f_s_cla32_xor7 = f_s_cla32_pg_logic7_xor0 ^ f_s_cla32_or11;
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assign f_s_cla32_and22 = f_s_cla32_or5 & f_s_cla32_pg_logic6_or0;
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assign f_s_cla32_and23 = f_s_cla32_pg_logic7_or0 & f_s_cla32_pg_logic5_or0;
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assign f_s_cla32_and24 = f_s_cla32_and22 & f_s_cla32_and23;
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assign f_s_cla32_and25 = f_s_cla32_and24 & f_s_cla32_pg_logic4_or0;
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assign f_s_cla32_and26 = f_s_cla32_pg_logic4_and0 & f_s_cla32_pg_logic6_or0;
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assign f_s_cla32_and27 = f_s_cla32_pg_logic7_or0 & f_s_cla32_pg_logic5_or0;
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assign f_s_cla32_and28 = f_s_cla32_and26 & f_s_cla32_and27;
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assign f_s_cla32_and29 = f_s_cla32_pg_logic5_and0 & f_s_cla32_pg_logic7_or0;
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assign f_s_cla32_and30 = f_s_cla32_and29 & f_s_cla32_pg_logic6_or0;
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assign f_s_cla32_and31 = f_s_cla32_pg_logic6_and0 & f_s_cla32_pg_logic7_or0;
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assign f_s_cla32_or12 = f_s_cla32_and25 | f_s_cla32_and30;
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assign f_s_cla32_or13 = f_s_cla32_and28 | f_s_cla32_and31;
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assign f_s_cla32_or14 = f_s_cla32_or12 | f_s_cla32_or13;
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assign f_s_cla32_or15 = f_s_cla32_pg_logic7_and0 | f_s_cla32_or14;
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assign f_s_cla32_pg_logic8_or0 = a[8] | b[8];
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assign f_s_cla32_pg_logic8_and0 = a[8] & b[8];
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assign f_s_cla32_pg_logic8_xor0 = a[8] ^ b[8];
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assign f_s_cla32_xor8 = f_s_cla32_pg_logic8_xor0 ^ f_s_cla32_or15;
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assign f_s_cla32_and32 = f_s_cla32_or15 & f_s_cla32_pg_logic8_or0;
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|
assign f_s_cla32_or16 = f_s_cla32_pg_logic8_and0 | f_s_cla32_and32;
|
|
assign f_s_cla32_pg_logic9_or0 = a[9] | b[9];
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|
assign f_s_cla32_pg_logic9_and0 = a[9] & b[9];
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assign f_s_cla32_pg_logic9_xor0 = a[9] ^ b[9];
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assign f_s_cla32_xor9 = f_s_cla32_pg_logic9_xor0 ^ f_s_cla32_or16;
|
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assign f_s_cla32_and33 = f_s_cla32_or15 & f_s_cla32_pg_logic9_or0;
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|
assign f_s_cla32_and34 = f_s_cla32_and33 & f_s_cla32_pg_logic8_or0;
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assign f_s_cla32_and35 = f_s_cla32_pg_logic8_and0 & f_s_cla32_pg_logic9_or0;
|
|
assign f_s_cla32_or17 = f_s_cla32_and34 | f_s_cla32_and35;
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|
assign f_s_cla32_or18 = f_s_cla32_pg_logic9_and0 | f_s_cla32_or17;
|
|
assign f_s_cla32_pg_logic10_or0 = a[10] | b[10];
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assign f_s_cla32_pg_logic10_and0 = a[10] & b[10];
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assign f_s_cla32_pg_logic10_xor0 = a[10] ^ b[10];
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|
assign f_s_cla32_xor10 = f_s_cla32_pg_logic10_xor0 ^ f_s_cla32_or18;
|
|
assign f_s_cla32_and36 = f_s_cla32_or15 & f_s_cla32_pg_logic9_or0;
|
|
assign f_s_cla32_and37 = f_s_cla32_pg_logic10_or0 & f_s_cla32_pg_logic8_or0;
|
|
assign f_s_cla32_and38 = f_s_cla32_and36 & f_s_cla32_and37;
|
|
assign f_s_cla32_and39 = f_s_cla32_pg_logic8_and0 & f_s_cla32_pg_logic10_or0;
|
|
assign f_s_cla32_and40 = f_s_cla32_and39 & f_s_cla32_pg_logic9_or0;
|
|
assign f_s_cla32_and41 = f_s_cla32_pg_logic9_and0 & f_s_cla32_pg_logic10_or0;
|
|
assign f_s_cla32_or19 = f_s_cla32_and38 | f_s_cla32_and40;
|
|
assign f_s_cla32_or20 = f_s_cla32_or19 | f_s_cla32_and41;
|
|
assign f_s_cla32_or21 = f_s_cla32_pg_logic10_and0 | f_s_cla32_or20;
|
|
assign f_s_cla32_pg_logic11_or0 = a[11] | b[11];
|
|
assign f_s_cla32_pg_logic11_and0 = a[11] & b[11];
|
|
assign f_s_cla32_pg_logic11_xor0 = a[11] ^ b[11];
|
|
assign f_s_cla32_xor11 = f_s_cla32_pg_logic11_xor0 ^ f_s_cla32_or21;
|
|
assign f_s_cla32_and42 = f_s_cla32_or15 & f_s_cla32_pg_logic10_or0;
|
|
assign f_s_cla32_and43 = f_s_cla32_pg_logic11_or0 & f_s_cla32_pg_logic9_or0;
|
|
assign f_s_cla32_and44 = f_s_cla32_and42 & f_s_cla32_and43;
|
|
assign f_s_cla32_and45 = f_s_cla32_and44 & f_s_cla32_pg_logic8_or0;
|
|
assign f_s_cla32_and46 = f_s_cla32_pg_logic8_and0 & f_s_cla32_pg_logic10_or0;
|
|
assign f_s_cla32_and47 = f_s_cla32_pg_logic11_or0 & f_s_cla32_pg_logic9_or0;
|
|
assign f_s_cla32_and48 = f_s_cla32_and46 & f_s_cla32_and47;
|
|
assign f_s_cla32_and49 = f_s_cla32_pg_logic9_and0 & f_s_cla32_pg_logic11_or0;
|
|
assign f_s_cla32_and50 = f_s_cla32_and49 & f_s_cla32_pg_logic10_or0;
|
|
assign f_s_cla32_and51 = f_s_cla32_pg_logic10_and0 & f_s_cla32_pg_logic11_or0;
|
|
assign f_s_cla32_or22 = f_s_cla32_and45 | f_s_cla32_and50;
|
|
assign f_s_cla32_or23 = f_s_cla32_and48 | f_s_cla32_and51;
|
|
assign f_s_cla32_or24 = f_s_cla32_or22 | f_s_cla32_or23;
|
|
assign f_s_cla32_or25 = f_s_cla32_pg_logic11_and0 | f_s_cla32_or24;
|
|
assign f_s_cla32_pg_logic12_or0 = a[12] | b[12];
|
|
assign f_s_cla32_pg_logic12_and0 = a[12] & b[12];
|
|
assign f_s_cla32_pg_logic12_xor0 = a[12] ^ b[12];
|
|
assign f_s_cla32_xor12 = f_s_cla32_pg_logic12_xor0 ^ f_s_cla32_or25;
|
|
assign f_s_cla32_and52 = f_s_cla32_or25 & f_s_cla32_pg_logic12_or0;
|
|
assign f_s_cla32_or26 = f_s_cla32_pg_logic12_and0 | f_s_cla32_and52;
|
|
assign f_s_cla32_pg_logic13_or0 = a[13] | b[13];
|
|
assign f_s_cla32_pg_logic13_and0 = a[13] & b[13];
|
|
assign f_s_cla32_pg_logic13_xor0 = a[13] ^ b[13];
|
|
assign f_s_cla32_xor13 = f_s_cla32_pg_logic13_xor0 ^ f_s_cla32_or26;
|
|
assign f_s_cla32_and53 = f_s_cla32_or25 & f_s_cla32_pg_logic13_or0;
|
|
assign f_s_cla32_and54 = f_s_cla32_and53 & f_s_cla32_pg_logic12_or0;
|
|
assign f_s_cla32_and55 = f_s_cla32_pg_logic12_and0 & f_s_cla32_pg_logic13_or0;
|
|
assign f_s_cla32_or27 = f_s_cla32_and54 | f_s_cla32_and55;
|
|
assign f_s_cla32_or28 = f_s_cla32_pg_logic13_and0 | f_s_cla32_or27;
|
|
assign f_s_cla32_pg_logic14_or0 = a[14] | b[14];
|
|
assign f_s_cla32_pg_logic14_and0 = a[14] & b[14];
|
|
assign f_s_cla32_pg_logic14_xor0 = a[14] ^ b[14];
|
|
assign f_s_cla32_xor14 = f_s_cla32_pg_logic14_xor0 ^ f_s_cla32_or28;
|
|
assign f_s_cla32_and56 = f_s_cla32_or25 & f_s_cla32_pg_logic13_or0;
|
|
assign f_s_cla32_and57 = f_s_cla32_pg_logic14_or0 & f_s_cla32_pg_logic12_or0;
|
|
assign f_s_cla32_and58 = f_s_cla32_and56 & f_s_cla32_and57;
|
|
assign f_s_cla32_and59 = f_s_cla32_pg_logic12_and0 & f_s_cla32_pg_logic14_or0;
|
|
assign f_s_cla32_and60 = f_s_cla32_and59 & f_s_cla32_pg_logic13_or0;
|
|
assign f_s_cla32_and61 = f_s_cla32_pg_logic13_and0 & f_s_cla32_pg_logic14_or0;
|
|
assign f_s_cla32_or29 = f_s_cla32_and58 | f_s_cla32_and60;
|
|
assign f_s_cla32_or30 = f_s_cla32_or29 | f_s_cla32_and61;
|
|
assign f_s_cla32_or31 = f_s_cla32_pg_logic14_and0 | f_s_cla32_or30;
|
|
assign f_s_cla32_pg_logic15_or0 = a[15] | b[15];
|
|
assign f_s_cla32_pg_logic15_and0 = a[15] & b[15];
|
|
assign f_s_cla32_pg_logic15_xor0 = a[15] ^ b[15];
|
|
assign f_s_cla32_xor15 = f_s_cla32_pg_logic15_xor0 ^ f_s_cla32_or31;
|
|
assign f_s_cla32_and62 = f_s_cla32_or25 & f_s_cla32_pg_logic14_or0;
|
|
assign f_s_cla32_and63 = f_s_cla32_pg_logic15_or0 & f_s_cla32_pg_logic13_or0;
|
|
assign f_s_cla32_and64 = f_s_cla32_and62 & f_s_cla32_and63;
|
|
assign f_s_cla32_and65 = f_s_cla32_and64 & f_s_cla32_pg_logic12_or0;
|
|
assign f_s_cla32_and66 = f_s_cla32_pg_logic12_and0 & f_s_cla32_pg_logic14_or0;
|
|
assign f_s_cla32_and67 = f_s_cla32_pg_logic15_or0 & f_s_cla32_pg_logic13_or0;
|
|
assign f_s_cla32_and68 = f_s_cla32_and66 & f_s_cla32_and67;
|
|
assign f_s_cla32_and69 = f_s_cla32_pg_logic13_and0 & f_s_cla32_pg_logic15_or0;
|
|
assign f_s_cla32_and70 = f_s_cla32_and69 & f_s_cla32_pg_logic14_or0;
|
|
assign f_s_cla32_and71 = f_s_cla32_pg_logic14_and0 & f_s_cla32_pg_logic15_or0;
|
|
assign f_s_cla32_or32 = f_s_cla32_and65 | f_s_cla32_and70;
|
|
assign f_s_cla32_or33 = f_s_cla32_and68 | f_s_cla32_and71;
|
|
assign f_s_cla32_or34 = f_s_cla32_or32 | f_s_cla32_or33;
|
|
assign f_s_cla32_or35 = f_s_cla32_pg_logic15_and0 | f_s_cla32_or34;
|
|
assign f_s_cla32_pg_logic16_or0 = a[16] | b[16];
|
|
assign f_s_cla32_pg_logic16_and0 = a[16] & b[16];
|
|
assign f_s_cla32_pg_logic16_xor0 = a[16] ^ b[16];
|
|
assign f_s_cla32_xor16 = f_s_cla32_pg_logic16_xor0 ^ f_s_cla32_or35;
|
|
assign f_s_cla32_and72 = f_s_cla32_or35 & f_s_cla32_pg_logic16_or0;
|
|
assign f_s_cla32_or36 = f_s_cla32_pg_logic16_and0 | f_s_cla32_and72;
|
|
assign f_s_cla32_pg_logic17_or0 = a[17] | b[17];
|
|
assign f_s_cla32_pg_logic17_and0 = a[17] & b[17];
|
|
assign f_s_cla32_pg_logic17_xor0 = a[17] ^ b[17];
|
|
assign f_s_cla32_xor17 = f_s_cla32_pg_logic17_xor0 ^ f_s_cla32_or36;
|
|
assign f_s_cla32_and73 = f_s_cla32_or35 & f_s_cla32_pg_logic17_or0;
|
|
assign f_s_cla32_and74 = f_s_cla32_and73 & f_s_cla32_pg_logic16_or0;
|
|
assign f_s_cla32_and75 = f_s_cla32_pg_logic16_and0 & f_s_cla32_pg_logic17_or0;
|
|
assign f_s_cla32_or37 = f_s_cla32_and74 | f_s_cla32_and75;
|
|
assign f_s_cla32_or38 = f_s_cla32_pg_logic17_and0 | f_s_cla32_or37;
|
|
assign f_s_cla32_pg_logic18_or0 = a[18] | b[18];
|
|
assign f_s_cla32_pg_logic18_and0 = a[18] & b[18];
|
|
assign f_s_cla32_pg_logic18_xor0 = a[18] ^ b[18];
|
|
assign f_s_cla32_xor18 = f_s_cla32_pg_logic18_xor0 ^ f_s_cla32_or38;
|
|
assign f_s_cla32_and76 = f_s_cla32_or35 & f_s_cla32_pg_logic17_or0;
|
|
assign f_s_cla32_and77 = f_s_cla32_pg_logic18_or0 & f_s_cla32_pg_logic16_or0;
|
|
assign f_s_cla32_and78 = f_s_cla32_and76 & f_s_cla32_and77;
|
|
assign f_s_cla32_and79 = f_s_cla32_pg_logic16_and0 & f_s_cla32_pg_logic18_or0;
|
|
assign f_s_cla32_and80 = f_s_cla32_and79 & f_s_cla32_pg_logic17_or0;
|
|
assign f_s_cla32_and81 = f_s_cla32_pg_logic17_and0 & f_s_cla32_pg_logic18_or0;
|
|
assign f_s_cla32_or39 = f_s_cla32_and78 | f_s_cla32_and80;
|
|
assign f_s_cla32_or40 = f_s_cla32_or39 | f_s_cla32_and81;
|
|
assign f_s_cla32_or41 = f_s_cla32_pg_logic18_and0 | f_s_cla32_or40;
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assign f_s_cla32_pg_logic19_or0 = a[19] | b[19];
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assign f_s_cla32_pg_logic19_and0 = a[19] & b[19];
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assign f_s_cla32_pg_logic19_xor0 = a[19] ^ b[19];
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assign f_s_cla32_xor19 = f_s_cla32_pg_logic19_xor0 ^ f_s_cla32_or41;
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assign f_s_cla32_and82 = f_s_cla32_or35 & f_s_cla32_pg_logic18_or0;
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assign f_s_cla32_and83 = f_s_cla32_pg_logic19_or0 & f_s_cla32_pg_logic17_or0;
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assign f_s_cla32_and84 = f_s_cla32_and82 & f_s_cla32_and83;
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assign f_s_cla32_and85 = f_s_cla32_and84 & f_s_cla32_pg_logic16_or0;
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assign f_s_cla32_and86 = f_s_cla32_pg_logic16_and0 & f_s_cla32_pg_logic18_or0;
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assign f_s_cla32_and87 = f_s_cla32_pg_logic19_or0 & f_s_cla32_pg_logic17_or0;
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assign f_s_cla32_and88 = f_s_cla32_and86 & f_s_cla32_and87;
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assign f_s_cla32_and89 = f_s_cla32_pg_logic17_and0 & f_s_cla32_pg_logic19_or0;
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assign f_s_cla32_and90 = f_s_cla32_and89 & f_s_cla32_pg_logic18_or0;
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assign f_s_cla32_and91 = f_s_cla32_pg_logic18_and0 & f_s_cla32_pg_logic19_or0;
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assign f_s_cla32_or42 = f_s_cla32_and85 | f_s_cla32_and90;
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assign f_s_cla32_or43 = f_s_cla32_and88 | f_s_cla32_and91;
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assign f_s_cla32_or44 = f_s_cla32_or42 | f_s_cla32_or43;
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assign f_s_cla32_or45 = f_s_cla32_pg_logic19_and0 | f_s_cla32_or44;
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assign f_s_cla32_pg_logic20_or0 = a[20] | b[20];
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assign f_s_cla32_pg_logic20_and0 = a[20] & b[20];
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assign f_s_cla32_pg_logic20_xor0 = a[20] ^ b[20];
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assign f_s_cla32_xor20 = f_s_cla32_pg_logic20_xor0 ^ f_s_cla32_or45;
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assign f_s_cla32_and92 = f_s_cla32_or45 & f_s_cla32_pg_logic20_or0;
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assign f_s_cla32_or46 = f_s_cla32_pg_logic20_and0 | f_s_cla32_and92;
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assign f_s_cla32_pg_logic21_or0 = a[21] | b[21];
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assign f_s_cla32_pg_logic21_and0 = a[21] & b[21];
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assign f_s_cla32_pg_logic21_xor0 = a[21] ^ b[21];
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assign f_s_cla32_xor21 = f_s_cla32_pg_logic21_xor0 ^ f_s_cla32_or46;
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assign f_s_cla32_and93 = f_s_cla32_or45 & f_s_cla32_pg_logic21_or0;
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assign f_s_cla32_and94 = f_s_cla32_and93 & f_s_cla32_pg_logic20_or0;
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assign f_s_cla32_and95 = f_s_cla32_pg_logic20_and0 & f_s_cla32_pg_logic21_or0;
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assign f_s_cla32_or47 = f_s_cla32_and94 | f_s_cla32_and95;
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assign f_s_cla32_or48 = f_s_cla32_pg_logic21_and0 | f_s_cla32_or47;
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assign f_s_cla32_pg_logic22_or0 = a[22] | b[22];
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assign f_s_cla32_pg_logic22_and0 = a[22] & b[22];
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assign f_s_cla32_pg_logic22_xor0 = a[22] ^ b[22];
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assign f_s_cla32_xor22 = f_s_cla32_pg_logic22_xor0 ^ f_s_cla32_or48;
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assign f_s_cla32_and96 = f_s_cla32_or45 & f_s_cla32_pg_logic21_or0;
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assign f_s_cla32_and97 = f_s_cla32_pg_logic22_or0 & f_s_cla32_pg_logic20_or0;
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assign f_s_cla32_and98 = f_s_cla32_and96 & f_s_cla32_and97;
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assign f_s_cla32_and99 = f_s_cla32_pg_logic20_and0 & f_s_cla32_pg_logic22_or0;
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assign f_s_cla32_and100 = f_s_cla32_and99 & f_s_cla32_pg_logic21_or0;
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assign f_s_cla32_and101 = f_s_cla32_pg_logic21_and0 & f_s_cla32_pg_logic22_or0;
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assign f_s_cla32_or49 = f_s_cla32_and98 | f_s_cla32_and100;
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assign f_s_cla32_or50 = f_s_cla32_or49 | f_s_cla32_and101;
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assign f_s_cla32_or51 = f_s_cla32_pg_logic22_and0 | f_s_cla32_or50;
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assign f_s_cla32_pg_logic23_or0 = a[23] | b[23];
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assign f_s_cla32_pg_logic23_and0 = a[23] & b[23];
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assign f_s_cla32_pg_logic23_xor0 = a[23] ^ b[23];
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assign f_s_cla32_xor23 = f_s_cla32_pg_logic23_xor0 ^ f_s_cla32_or51;
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assign f_s_cla32_and102 = f_s_cla32_or45 & f_s_cla32_pg_logic22_or0;
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assign f_s_cla32_and103 = f_s_cla32_pg_logic23_or0 & f_s_cla32_pg_logic21_or0;
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assign f_s_cla32_and104 = f_s_cla32_and102 & f_s_cla32_and103;
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assign f_s_cla32_and105 = f_s_cla32_and104 & f_s_cla32_pg_logic20_or0;
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assign f_s_cla32_and106 = f_s_cla32_pg_logic20_and0 & f_s_cla32_pg_logic22_or0;
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assign f_s_cla32_and107 = f_s_cla32_pg_logic23_or0 & f_s_cla32_pg_logic21_or0;
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assign f_s_cla32_and108 = f_s_cla32_and106 & f_s_cla32_and107;
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assign f_s_cla32_and109 = f_s_cla32_pg_logic21_and0 & f_s_cla32_pg_logic23_or0;
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assign f_s_cla32_and110 = f_s_cla32_and109 & f_s_cla32_pg_logic22_or0;
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assign f_s_cla32_and111 = f_s_cla32_pg_logic22_and0 & f_s_cla32_pg_logic23_or0;
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assign f_s_cla32_or52 = f_s_cla32_and105 | f_s_cla32_and110;
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assign f_s_cla32_or53 = f_s_cla32_and108 | f_s_cla32_and111;
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assign f_s_cla32_or54 = f_s_cla32_or52 | f_s_cla32_or53;
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assign f_s_cla32_or55 = f_s_cla32_pg_logic23_and0 | f_s_cla32_or54;
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assign f_s_cla32_pg_logic24_or0 = a[24] | b[24];
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assign f_s_cla32_pg_logic24_and0 = a[24] & b[24];
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assign f_s_cla32_pg_logic24_xor0 = a[24] ^ b[24];
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assign f_s_cla32_xor24 = f_s_cla32_pg_logic24_xor0 ^ f_s_cla32_or55;
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assign f_s_cla32_and112 = f_s_cla32_or55 & f_s_cla32_pg_logic24_or0;
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assign f_s_cla32_or56 = f_s_cla32_pg_logic24_and0 | f_s_cla32_and112;
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assign f_s_cla32_pg_logic25_or0 = a[25] | b[25];
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assign f_s_cla32_pg_logic25_and0 = a[25] & b[25];
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assign f_s_cla32_pg_logic25_xor0 = a[25] ^ b[25];
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assign f_s_cla32_xor25 = f_s_cla32_pg_logic25_xor0 ^ f_s_cla32_or56;
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assign f_s_cla32_and113 = f_s_cla32_or55 & f_s_cla32_pg_logic25_or0;
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assign f_s_cla32_and114 = f_s_cla32_and113 & f_s_cla32_pg_logic24_or0;
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assign f_s_cla32_and115 = f_s_cla32_pg_logic24_and0 & f_s_cla32_pg_logic25_or0;
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assign f_s_cla32_or57 = f_s_cla32_and114 | f_s_cla32_and115;
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assign f_s_cla32_or58 = f_s_cla32_pg_logic25_and0 | f_s_cla32_or57;
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assign f_s_cla32_pg_logic26_or0 = a[26] | b[26];
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assign f_s_cla32_pg_logic26_and0 = a[26] & b[26];
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assign f_s_cla32_pg_logic26_xor0 = a[26] ^ b[26];
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assign f_s_cla32_xor26 = f_s_cla32_pg_logic26_xor0 ^ f_s_cla32_or58;
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assign f_s_cla32_and116 = f_s_cla32_or55 & f_s_cla32_pg_logic25_or0;
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assign f_s_cla32_and117 = f_s_cla32_pg_logic26_or0 & f_s_cla32_pg_logic24_or0;
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assign f_s_cla32_and118 = f_s_cla32_and116 & f_s_cla32_and117;
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assign f_s_cla32_and119 = f_s_cla32_pg_logic24_and0 & f_s_cla32_pg_logic26_or0;
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assign f_s_cla32_and120 = f_s_cla32_and119 & f_s_cla32_pg_logic25_or0;
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assign f_s_cla32_and121 = f_s_cla32_pg_logic25_and0 & f_s_cla32_pg_logic26_or0;
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assign f_s_cla32_or59 = f_s_cla32_and118 | f_s_cla32_and120;
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assign f_s_cla32_or60 = f_s_cla32_or59 | f_s_cla32_and121;
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assign f_s_cla32_or61 = f_s_cla32_pg_logic26_and0 | f_s_cla32_or60;
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|
assign f_s_cla32_pg_logic27_or0 = a[27] | b[27];
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assign f_s_cla32_pg_logic27_and0 = a[27] & b[27];
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assign f_s_cla32_pg_logic27_xor0 = a[27] ^ b[27];
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assign f_s_cla32_xor27 = f_s_cla32_pg_logic27_xor0 ^ f_s_cla32_or61;
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assign f_s_cla32_and122 = f_s_cla32_or55 & f_s_cla32_pg_logic26_or0;
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assign f_s_cla32_and123 = f_s_cla32_pg_logic27_or0 & f_s_cla32_pg_logic25_or0;
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assign f_s_cla32_and124 = f_s_cla32_and122 & f_s_cla32_and123;
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assign f_s_cla32_and125 = f_s_cla32_and124 & f_s_cla32_pg_logic24_or0;
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assign f_s_cla32_and126 = f_s_cla32_pg_logic24_and0 & f_s_cla32_pg_logic26_or0;
|
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assign f_s_cla32_and127 = f_s_cla32_pg_logic27_or0 & f_s_cla32_pg_logic25_or0;
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assign f_s_cla32_and128 = f_s_cla32_and126 & f_s_cla32_and127;
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assign f_s_cla32_and129 = f_s_cla32_pg_logic25_and0 & f_s_cla32_pg_logic27_or0;
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assign f_s_cla32_and130 = f_s_cla32_and129 & f_s_cla32_pg_logic26_or0;
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|
assign f_s_cla32_and131 = f_s_cla32_pg_logic26_and0 & f_s_cla32_pg_logic27_or0;
|
|
assign f_s_cla32_or62 = f_s_cla32_and125 | f_s_cla32_and130;
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|
assign f_s_cla32_or63 = f_s_cla32_and128 | f_s_cla32_and131;
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|
assign f_s_cla32_or64 = f_s_cla32_or62 | f_s_cla32_or63;
|
|
assign f_s_cla32_or65 = f_s_cla32_pg_logic27_and0 | f_s_cla32_or64;
|
|
assign f_s_cla32_pg_logic28_or0 = a[28] | b[28];
|
|
assign f_s_cla32_pg_logic28_and0 = a[28] & b[28];
|
|
assign f_s_cla32_pg_logic28_xor0 = a[28] ^ b[28];
|
|
assign f_s_cla32_xor28 = f_s_cla32_pg_logic28_xor0 ^ f_s_cla32_or65;
|
|
assign f_s_cla32_and132 = f_s_cla32_or65 & f_s_cla32_pg_logic28_or0;
|
|
assign f_s_cla32_or66 = f_s_cla32_pg_logic28_and0 | f_s_cla32_and132;
|
|
assign f_s_cla32_pg_logic29_or0 = a[29] | b[29];
|
|
assign f_s_cla32_pg_logic29_and0 = a[29] & b[29];
|
|
assign f_s_cla32_pg_logic29_xor0 = a[29] ^ b[29];
|
|
assign f_s_cla32_xor29 = f_s_cla32_pg_logic29_xor0 ^ f_s_cla32_or66;
|
|
assign f_s_cla32_and133 = f_s_cla32_or65 & f_s_cla32_pg_logic29_or0;
|
|
assign f_s_cla32_and134 = f_s_cla32_and133 & f_s_cla32_pg_logic28_or0;
|
|
assign f_s_cla32_and135 = f_s_cla32_pg_logic28_and0 & f_s_cla32_pg_logic29_or0;
|
|
assign f_s_cla32_or67 = f_s_cla32_and134 | f_s_cla32_and135;
|
|
assign f_s_cla32_or68 = f_s_cla32_pg_logic29_and0 | f_s_cla32_or67;
|
|
assign f_s_cla32_pg_logic30_or0 = a[30] | b[30];
|
|
assign f_s_cla32_pg_logic30_and0 = a[30] & b[30];
|
|
assign f_s_cla32_pg_logic30_xor0 = a[30] ^ b[30];
|
|
assign f_s_cla32_xor30 = f_s_cla32_pg_logic30_xor0 ^ f_s_cla32_or68;
|
|
assign f_s_cla32_and136 = f_s_cla32_or65 & f_s_cla32_pg_logic29_or0;
|
|
assign f_s_cla32_and137 = f_s_cla32_pg_logic30_or0 & f_s_cla32_pg_logic28_or0;
|
|
assign f_s_cla32_and138 = f_s_cla32_and136 & f_s_cla32_and137;
|
|
assign f_s_cla32_and139 = f_s_cla32_pg_logic28_and0 & f_s_cla32_pg_logic30_or0;
|
|
assign f_s_cla32_and140 = f_s_cla32_and139 & f_s_cla32_pg_logic29_or0;
|
|
assign f_s_cla32_and141 = f_s_cla32_pg_logic29_and0 & f_s_cla32_pg_logic30_or0;
|
|
assign f_s_cla32_or69 = f_s_cla32_and138 | f_s_cla32_and140;
|
|
assign f_s_cla32_or70 = f_s_cla32_or69 | f_s_cla32_and141;
|
|
assign f_s_cla32_or71 = f_s_cla32_pg_logic30_and0 | f_s_cla32_or70;
|
|
assign f_s_cla32_pg_logic31_or0 = a[31] | b[31];
|
|
assign f_s_cla32_pg_logic31_and0 = a[31] & b[31];
|
|
assign f_s_cla32_pg_logic31_xor0 = a[31] ^ b[31];
|
|
assign f_s_cla32_xor31 = f_s_cla32_pg_logic31_xor0 ^ f_s_cla32_or71;
|
|
assign f_s_cla32_and142 = f_s_cla32_or65 & f_s_cla32_pg_logic30_or0;
|
|
assign f_s_cla32_and143 = f_s_cla32_pg_logic31_or0 & f_s_cla32_pg_logic29_or0;
|
|
assign f_s_cla32_and144 = f_s_cla32_and142 & f_s_cla32_and143;
|
|
assign f_s_cla32_and145 = f_s_cla32_and144 & f_s_cla32_pg_logic28_or0;
|
|
assign f_s_cla32_and146 = f_s_cla32_pg_logic28_and0 & f_s_cla32_pg_logic30_or0;
|
|
assign f_s_cla32_and147 = f_s_cla32_pg_logic31_or0 & f_s_cla32_pg_logic29_or0;
|
|
assign f_s_cla32_and148 = f_s_cla32_and146 & f_s_cla32_and147;
|
|
assign f_s_cla32_and149 = f_s_cla32_pg_logic29_and0 & f_s_cla32_pg_logic31_or0;
|
|
assign f_s_cla32_and150 = f_s_cla32_and149 & f_s_cla32_pg_logic30_or0;
|
|
assign f_s_cla32_and151 = f_s_cla32_pg_logic30_and0 & f_s_cla32_pg_logic31_or0;
|
|
assign f_s_cla32_or72 = f_s_cla32_and145 | f_s_cla32_and150;
|
|
assign f_s_cla32_or73 = f_s_cla32_and148 | f_s_cla32_and151;
|
|
assign f_s_cla32_or74 = f_s_cla32_or72 | f_s_cla32_or73;
|
|
assign f_s_cla32_or75 = f_s_cla32_pg_logic31_and0 | f_s_cla32_or74;
|
|
assign f_s_cla32_xor32 = a[31] ^ b[31];
|
|
assign f_s_cla32_xor33 = f_s_cla32_xor32 ^ f_s_cla32_or75;
|
|
|
|
assign f_s_cla32_out[0] = f_s_cla32_pg_logic0_xor0;
|
|
assign f_s_cla32_out[1] = f_s_cla32_xor1;
|
|
assign f_s_cla32_out[2] = f_s_cla32_xor2;
|
|
assign f_s_cla32_out[3] = f_s_cla32_xor3;
|
|
assign f_s_cla32_out[4] = f_s_cla32_xor4;
|
|
assign f_s_cla32_out[5] = f_s_cla32_xor5;
|
|
assign f_s_cla32_out[6] = f_s_cla32_xor6;
|
|
assign f_s_cla32_out[7] = f_s_cla32_xor7;
|
|
assign f_s_cla32_out[8] = f_s_cla32_xor8;
|
|
assign f_s_cla32_out[9] = f_s_cla32_xor9;
|
|
assign f_s_cla32_out[10] = f_s_cla32_xor10;
|
|
assign f_s_cla32_out[11] = f_s_cla32_xor11;
|
|
assign f_s_cla32_out[12] = f_s_cla32_xor12;
|
|
assign f_s_cla32_out[13] = f_s_cla32_xor13;
|
|
assign f_s_cla32_out[14] = f_s_cla32_xor14;
|
|
assign f_s_cla32_out[15] = f_s_cla32_xor15;
|
|
assign f_s_cla32_out[16] = f_s_cla32_xor16;
|
|
assign f_s_cla32_out[17] = f_s_cla32_xor17;
|
|
assign f_s_cla32_out[18] = f_s_cla32_xor18;
|
|
assign f_s_cla32_out[19] = f_s_cla32_xor19;
|
|
assign f_s_cla32_out[20] = f_s_cla32_xor20;
|
|
assign f_s_cla32_out[21] = f_s_cla32_xor21;
|
|
assign f_s_cla32_out[22] = f_s_cla32_xor22;
|
|
assign f_s_cla32_out[23] = f_s_cla32_xor23;
|
|
assign f_s_cla32_out[24] = f_s_cla32_xor24;
|
|
assign f_s_cla32_out[25] = f_s_cla32_xor25;
|
|
assign f_s_cla32_out[26] = f_s_cla32_xor26;
|
|
assign f_s_cla32_out[27] = f_s_cla32_xor27;
|
|
assign f_s_cla32_out[28] = f_s_cla32_xor28;
|
|
assign f_s_cla32_out[29] = f_s_cla32_xor29;
|
|
assign f_s_cla32_out[30] = f_s_cla32_xor30;
|
|
assign f_s_cla32_out[31] = f_s_cla32_xor31;
|
|
assign f_s_cla32_out[32] = f_s_cla32_xor33;
|
|
endmodule |