470 lines
21 KiB
Python
470 lines
21 KiB
Python
from wire_components import wire, bus
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from logic_gates_generator import not_gate, and_gate, xor_gate, or_gate, nand_gate, xnor_gate, nor_gate
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import sys
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import itertools
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""" ARITHMETIC CIRCUITS """
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class arithmetic_circuit():
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def __init__(self):
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self.components = []
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self.circuit_wires = []
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self.c_data_type = "uint64_t"
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# TODO delete?
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self.carry_out_gate = None
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self.sum_out_gates = []
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def add_component(self, component):
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self.components.append(component)
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def get_previous_component(self):
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return self.components[-1]
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def get_component_types(self):
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return list({type(c): c for c in self.components}.values())
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def get_unique_types(self):
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hier_components = self.all_gates + self.component_types
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return list({type(c): c for c in hier_components}.values())
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def get_gate_types(self):
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return list({type(g): g for g in self.all_gates}.values())
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def get_sum_wire(self):
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return self.out.get_wire(0)
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def get_carry_wire(self):
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return self.out.get_wire(1)
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# FLAT C GENERATION #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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return f"uint64_t {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"
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def get_declaration_c_flat(self):
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return f"".join([c.get_declaration_c_flat() for c in self.components])
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def get_init_c_flat(self):
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return "".join([c.get_init_c_flat() for c in self.components])
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def get_function_sum_c_flat(self):
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return "".join([c.get_function_sum_c_flat(offset=self.components.index(c)) for c in self.components])
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def get_function_carry_c_flat(self):
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return f"{self.get_previous_component().get_function_carry_c_flat(offset=self.out.N-1)}"
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# Generating flat C code representation of circuit
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def get_c_code_flat(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(self.out.get_declaration_c())
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file_object.write(self.get_declaration_c_flat()+"\n")
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file_object.write(self.get_init_c_flat()+"\n")
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file_object.write(self.get_function_sum_c_flat())
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file_object.write(self.get_function_carry_c_flat())
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C GENERATION #
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def get_function_blocks_c(self):
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# Add unique 1-bit adder components (ha, fa)
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self.component_types = self.get_component_types()
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# Add unique logic gates composing subcomponents
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self.all_gates = list(itertools.chain.from_iterable([c.get_component_types() for c in self.component_types]))
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self.component_types = self.get_unique_types()
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return "".join([c.get_function_block_c() for c in self.component_types])
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def get_declaration_c_hier(self):
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self.cout = bus(N=self.N-1, prefix="cout")
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return "".join(self.a.get_wire_declaration_c()) + \
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"".join(self.b.get_wire_declaration_c()) + \
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"".join(self.cout.get_wire_declaration_c())
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def get_init_sum_c_hier(self):
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self.in_wires = self.a.bus + self.b.bus
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return ";\n".join([f" {w.name} = " + w.get_wire_value_c(offset=int(w.name[2:])) for w in self.in_wires])
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def get_init_cout_c_hier(self):
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return "\n".join([c.get_invocation_c(wire_n=self.cout.get_wire(self.components.index(c)).name, offset=self.components.index(c)) for c in self.components[:-1]])
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def get_function_sum_c_hier(self):
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return ";\n".join([c.get_adder_sum(offset=self.components.index(c)) for c in self.components])+";\n"
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def get_function_carry_c_hier(self):
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return f"{self.get_previous_component().get_adder_cout(offset=self.out.N-1)};\n"
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def get_circuit_c(self):
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}" + \
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f"{self.get_declaration_c_hier()}\n" + \
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f"{self.get_init_sum_c_hier()};\n" + \
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f"{self.get_init_cout_c_hier()}\n\n" + \
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f"{self.get_function_sum_c_hier()}" + \
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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# Generating hierarchical C code representation of circuit
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def get_c_code_hier(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_function_blocks_c())
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file_object.write(self.get_circuit_c())
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file_object.close()
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class half_adder(arithmetic_circuit):
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def __init__(self, a: wire, b: wire, prefix: str = "ha"):
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super().__init__()
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self.c_data_type = "uint8_t"
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self.prefix = prefix
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self.a = a
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self.b = b
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", 2)
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# Sum
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# XOR gate for calculation of 1-bit sum
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obj_xor_gate = xor_gate(a, b, prefix, outid=0)
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self.add_component(obj_xor_gate)
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self.out.connect(0, obj_xor_gate.output)
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# Cout
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# AND gate for calculation of 1-bit cout
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obj_and_gate = and_gate(a, b, prefix, outid=1)
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self.add_component(obj_and_gate)
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self.out.connect(1, obj_and_gate.output)
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# FLAT C GENERATION #
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# Half adder function prototype with two inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.name}, {self.c_data_type} {self.b.name})" + "{" + "\n"
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c_flat(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name))
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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# Half adder wires values initialization
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def get_init_c_flat(self):
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self.a.prefix = self.a.name if self.a.prefix == "" else self.a.prefix
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self.b.prefix = self.b.name if self.b.prefix == "" else self.b.prefix
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return f" {self.components[0].a.name} = {self.a.get_wire_value_c(offset=self.a.index)};\n" + \
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f" {self.components[0].b.name} = {self.b.get_wire_value_c(offset=self.b.index)};\n" + \
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f" {self.components[0].output.name} = {self.components[0].get_init_c_flat()};\n" + \
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f" {self.components[1].output.name} = {self.components[1].get_init_c_flat()};\n"
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def get_function_sum_c_flat(self, offset: int = 0):
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return f" {self.out.prefix} |= {self.components[0].output.return_wire_value_c(offset=offset)};\n"
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def get_function_carry_c_flat(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.components[1].output.return_wire_value_c(offset=offset)};\n"
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# HIERARCHICAL C GENERATION #
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def get_function_block_c(self):
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self.component_types = self.get_component_types()
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self.prefix = "ha"
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return f"{self.get_circuit_c()}\n\n"
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def get_function_blocks_c(self):
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self.component_types = self.get_component_types()
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return "".join([c.get_function_block_c() for c in self.component_types])
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def get_invocation_c(self, wire_n: str, offset: int = 0):
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self.prefix = "ha" if (offset == 0) else "fa"
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return f" {wire_n} = ({self.prefix}({self.a.name}, {self.b.name}) >> 1) & 0x01;"
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def get_adder_sum(self, offset: int = 0):
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return f" {self.out.prefix} |= (({self.prefix}({self.a.name}, {self.b.name}) >> 0) & 0x01) << {offset}"
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def get_adder_cout(self, offset: int = 1):
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return f" {self.out.prefix} |= (({self.prefix}({self.a.name}, {self.b.name}) >> 1) & 0x01) << {offset}"
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def get_function_sum_c_hier(self, offset: int = 0):
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return f" {self.out.prefix} |= {self.component_types[0].get_gate_output_c(a=self.a ,b=self.b, offset=offset)};\n"
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def get_function_carry_c_hier(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.component_types[1].get_gate_output_c(a=self.a ,b=self.b, offset=offset)};\n"
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def get_circuit_c(self):
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}\n" + \
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f"{self.get_function_sum_c_hier()}" + \
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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class full_adder(arithmetic_circuit):
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def __init__(self, a: wire, b: wire, c: wire, prefix: str = "fa"):
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super().__init__()
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self.c_data_type = "uint8_t"
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self.prefix = prefix
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self.a = a
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self.b = b
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self.c = c
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", 2)
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# PG logic
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propagate_xor_gate1 = xor_gate(a, b, prefix, outid=0)
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self.add_component(propagate_xor_gate1)
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generate_and_gate1 = and_gate(a, b, prefix, outid=1)
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self.add_component(generate_and_gate1)
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# Sum
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# XOR gate for calculation of 1-bit sum
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obj_xor_gate2 = xor_gate(propagate_xor_gate1.output, c, prefix, outid=2)
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self.add_component(obj_xor_gate2)
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self.out.connect(0, obj_xor_gate2.output)
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# Cout
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# AND gate for calculation of 1-bit cout
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obj_and_gate2 = and_gate(propagate_xor_gate1.output, c, prefix, outid=3)
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self.add_component(obj_and_gate2)
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obj_or_gate = or_gate(generate_and_gate1.output, obj_and_gate2.output, prefix, outid=4)
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self.add_component(obj_or_gate)
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self.out.connect(1, obj_or_gate.output)
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# TODO delete or leave?
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self.propagate = propagate_xor_gate1.output
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self.generate = generate_and_gate1.output
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# FLAT C GENERATION #
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# Full adder function prototype with three inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.name}, {self.c_data_type} {self.b.name}, {self.c_data_type} {self.c.name})" + "{" + "\n"
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c_flat(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name))
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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# Full adder wires values initialization
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def get_init_c_flat(self):
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self.a.prefix = self.a.name if self.a.prefix == "" else self.a.prefix
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self.b.prefix = self.b.name if self.b.prefix == "" else self.b.prefix
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self.c.prefix = self.c.name
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return f" {self.components[0].a.name} = {self.a.get_wire_value_c(offset=self.a.index)};\n" + \
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f" {self.components[0].b.name} = {self.b.get_wire_value_c(offset=self.b.index)};\n" + \
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f" {self.components[2].b.name} = {self.c.get_wire_value_c()};\n" + \
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f" {self.components[0].output.name} = {self.components[0].get_init_c_flat()};\n" + \
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f" {self.components[1].output.name} = {self.components[1].get_init_c_flat()};\n" + \
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f" {self.components[2].output.name} = {self.components[2].get_init_c_flat()};\n" + \
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f" {self.components[3].output.name} = {self.components[3].get_init_c_flat()};\n" + \
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f" {self.components[4].output.name} = {self.components[4].get_init_c_flat()};\n"
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def get_function_sum_c_flat(self, offset: int = 0):
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return f" {self.out.prefix} |= {self.components[2].output.return_wire_value_c(offset=offset)};\n"
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def get_function_carry_c_flat(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.components[4].output.return_wire_value_c(offset=offset)};\n"
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# HIERARCHICAL C GENERATION #
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def get_function_block_c(self):
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self.component_types = self.get_component_types()
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self.prefix = "fa"
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self.c.name = "cin"
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return f"{self.get_circuit_c()}\n\n"
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def get_function_blocks_c(self):
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self.component_types = self.get_component_types()
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return "".join([c.get_function_block_c() for c in self.component_types])
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def get_declaration_c_hier(self):
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self.component_types[0].a.name = "xor_1"
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self.component_types[2].a.name = "and_1"
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self.component_types[2].b.name = "and_2"
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return f"{self.component_types[0].a.get_declaration_c()}" + \
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f"{self.component_types[2].a.get_declaration_c()}" + \
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f"{self.component_types[2].b.get_declaration_c()}"
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def get_init_c_hier(self):
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return f" {self.component_types[0].a.name} = {self.component_types[0].get_invocation_c(self.a, self.b)}\n" + \
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f" {self.component_types[2].a.name} = {self.component_types[1].get_invocation_c(self.a, self.b)}\n" + \
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f" {self.component_types[2].b.name} = {self.component_types[1].get_invocation_c(self.component_types[0].a, self.c)}\n"
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def get_invocation_c(self, wire_n: str, offset: int = 0):
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self.prefix = "ha" if (offset == 0) else "fa"
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self.c.name = "cout_"+str(offset-1)
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return f" {wire_n} = ({self.prefix}({self.a.name}, {self.b.name}, {self.c.name}) >> 1) & 0x01;"
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def get_adder_sum(self, offset: int = 0):
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self.c.name = "cout_"+str(offset-1)
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return f" {self.out.prefix} |= (({self.prefix}({self.a.name}, {self.b.name}, {self.c.name}) >> 0) & 0x01) << {offset}"
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def get_adder_cout(self, offset: int = 1):
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self.c.name = "cout_"+str(offset-2)
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return f" {self.out.prefix} |= (({self.prefix}({self.a.name}, {self.b.name}, {self.c.name}) >> 1) & 0x01) << {offset}"
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def get_function_sum_c_hier(self, offset: int = 0):
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return f" {self.out.prefix} |= {self.component_types[0].get_gate_output_c(a=self.component_types[0].a, b=self.c, offset=offset)};\n"
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def get_function_carry_c_hier(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.component_types[-1].get_gate_output_c(a=self.component_types[2].a, b=self.component_types[2].b, offset=offset)};\n"
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def get_circuit_c(self):
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self.component_types = self.component_types
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}" + \
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f"{self.get_declaration_c_hier()}\n" + \
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f"{self.get_init_c_hier()}\n" + \
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f"{self.get_function_sum_c_hier()}" + \
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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class signed_ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "s_rca"):
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super().__init__()
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self.N = max(a.N, b.N)
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self.c_data_type = "int64_t"
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# Bus sign extension in case buses have different lengths
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a.bus_extend(N=self.N, prefix=a.prefix)
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b.bus_extend(N=self.N, prefix=b.prefix)
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self.a = a
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self.b = b
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if prefix == "s_rca":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for N sum bits and additional cout bit
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self.out = bus("out", self.N+1)
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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# First one is a half adder
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if input_index == 0:
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obj_ha = half_adder(a.get_wire(input_index), b.get_wire(input_index), prefix=self.prefix+"_ha")
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self.add_component(obj_ha)
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self.out.connect(input_index, obj_ha)
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# Rest are full adders
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else:
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obj_fa = full_adder(a.get_wire(input_index), b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_fa)
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self.out.connect(input_index, obj_fa.get_sum_wire())
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if input_index == (self.N-1):
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self.out.connect(self.N, obj_fa.get_carry_wire())
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# Additional XOR gates to ensure correct sign extension in case of sign addition
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sign_xor_1 = xor_gate(self.get_previous_component().a, self.get_previous_component().b, prefix=self.prefix+"_xor_1")
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sign_xor_2 = xor_gate(sign_xor_1.output, self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_xor_2")
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self.add_component(sign_xor_1)
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self.add_component(sign_xor_2)
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|
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# FLAT C GENERATION #
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# Initialization of 1-bit adders and sign extension XOR gates
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def get_init_c_flat(self):
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self.components[-2].output.prefix = self.components[-2].output.name
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self.components[-3].get_carry_wire().prefix = self.components[-3].get_carry_wire().name
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return f"".join([c.get_init_c_flat() for c in self.components[:-2]]) + \
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f" {self.components[-2].a.name} = {self.a.get_wire_value_c(offset=self.N-1)};\n" + \
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f" {self.components[-2].b.name} = {self.b.get_wire_value_c(offset=self.N-1)};\n" + \
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f" {self.components[-2].output.name} = {self.components[-2].get_init_c_flat()};\n" + \
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f" {self.components[-1].a.name} = {self.components[-2].output.get_wire_value_c()};\n" + \
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f" {self.components[-1].b.name} = {self.components[-3].get_carry_wire().get_wire_value_c()};\n" + \
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f" {self.components[-1].output.name} = {self.components[-1].get_init_c_flat()};\n"
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|
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def get_function_sum_c_flat(self):
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return "".join([c.get_function_sum_c_flat(offset=self.components.index(c)) for c in self.components[:-2]])
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|
|
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def get_function_carry_c_flat(self):
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return f" {self.out.prefix} |= {self.get_previous_component().output.return_wire_value_c(offset = self.N)};\n"
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|
|
|
# HIERARCHICAL C GENERATION #
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|
def get_declaration_c_hier(self):
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self.cout = bus(N=self.N, prefix="cout")
|
|
return "".join(self.a.get_wire_declaration_c()) + \
|
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"".join(self.b.get_wire_declaration_c()) + \
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"".join(self.cout.get_wire_declaration_c()) + \
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f"{self.components[-2].output.get_declaration_c()}"
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|
|
|
def get_init_cout_c_hier(self):
|
|
return "\n".join([c.get_invocation_c(wire_n=self.cout.get_wire(self.components.index(c)).name, offset=self.components.index(c)) for c in self.components[:-2]]) + \
|
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f"\n {self.components[-2].output.name} = {self.components[-2].get_invocation_c(a=self.a.bus[-1], b=self.b.bus[-1])}"
|
|
|
|
def get_function_sum_c_hier(self):
|
|
return ";\n".join([c.get_adder_sum(offset=self.components.index(c)) for c in self.components[:-2]])+";\n"
|
|
|
|
def get_function_carry_c_hier(self):
|
|
return f" {self.out.prefix} |= {self.get_previous_component().get_gate_output_c(a=self.components[-2].output, b=self.cout.bus[-1], offset=self.out.N-1)};\n"
|
|
|
|
|
|
class unsigned_ripple_carry_adder(arithmetic_circuit):
|
|
def __init__(self, a: bus, b: bus, prefix: str = "u_rca"):
|
|
super().__init__()
|
|
self.N = max(a.N, b.N)
|
|
# Bus sign extension in ase buses have different lengths
|
|
a.bus_extend(N=self.N, prefix=a.prefix)
|
|
b.bus_extend(N=self.N, prefix=b.prefix)
|
|
self.a = a
|
|
self.b = b
|
|
if prefix == "u_rca":
|
|
self.prefix = prefix+str(self.N)
|
|
else:
|
|
self.prefix = prefix
|
|
|
|
# Output wires for N sum bits and additional cout bit
|
|
self.out = bus("out", self.N+1)
|
|
|
|
# Gradual addition of 1-bit adder components
|
|
for input_index in range(self.N):
|
|
# First one is a half adder
|
|
if input_index == 0:
|
|
obj_ha = half_adder(a.get_wire(input_index), b.get_wire(input_index), prefix=self.prefix+"_ha")
|
|
self.add_component(obj_ha)
|
|
self.out.connect(input_index, obj_ha)
|
|
# Rest are full adders
|
|
else:
|
|
obj_fa = full_adder(a.get_wire(input_index), b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
|
|
self.add_component(obj_fa)
|
|
self.out.connect(input_index, obj_fa.get_sum_wire())
|
|
|
|
if input_index == (self.N-1):
|
|
self.out.connect(self.N, obj_fa.get_carry_wire())
|
|
|
|
|
|
if __name__ == "__main__":
|
|
a = bus(N=8, prefix="a")
|
|
b = bus(N=8, prefix="b")
|
|
rca = unsigned_ripple_carry_adder(a, b)
|
|
|
|
# rca.get_c_code_hier(open("h_u_rca8.c", "w"))
|
|
|
|
w1 = wire(name="a")
|
|
w2 = wire(name="b")
|
|
w3 = wire(name="cout")
|
|
fa = full_adder(w1, w2, w3, prefix="h_fa")
|
|
ha = half_adder(w1, w2, prefix="h_ha")
|
|
|
|
# ha.get_c_code_hier(open("h_ha.c","w"))
|