235 lines
14 KiB
Python
235 lines
14 KiB
Python
from ariths_gen.multi_bit_circuits.adders.carry_lookahead_adder import UnsignedCarryLookaheadAdder
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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ArithmeticCircuit,
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MultiplierCircuit
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder,
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FullAdderPG
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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class UnsignedWallaceMultiplier(MultiplierCircuit):
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"""Class representing unsigned wallace multiplier.
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Unsigned wallace multiplier represents fast N-bit multiplier which utilizes
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the functionality of wallace tree reduction algorithm proposed by Chris Wallace.
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First partial products are calculated for each bit pair that form the partial product multiplication columns.
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At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits.
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Wallace tree algorithm is described more in detail here:
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https://en.wikipedia.org/wiki/Wallace_tree
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It presents smaller circuit in area opposed to array multiplier but is slightly bigger then dadda because of less reduction stages.
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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prefix (str, optional): Prefix name of unsigned wallace multiplier. Defaults to "".
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name (str, optional): Name of unsigned wallace multiplier. Defaults to "u_wallace_cla".
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unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
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"""
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def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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# Initialize all columns partial products forming AND gates matrix
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self.columns = self.init_column_heights()
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# Perform reduction until all columns have 2 or less bits in them
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while not all(height <= 2 for (height, *_) in self.columns):
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col = 0
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while col < len(self.columns):
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# If column has exactly 3 bits in height and all previous columns has maximum of 2 bits in height, combine them in a half adder
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if self.get_column_height(col) == 3 and all(height <= 2 for (height, *_) in self.columns[0:col-1]):
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# Add half adder and also AND gates if neccesarry (via add_column_wire invocation) into list of circuit components
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obj_adder = HalfAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
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self.add_component(obj_adder)
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# Update the number of current and next column wires
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self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
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# Update current and next column wires arrangement
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# add ha's generated sum to the bottom of current column
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# add ha's generated cout to the top of next column
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self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
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# If column has more than 3 bits in height, combine them in a full adder
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elif self.get_column_height(col) > 3:
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# Add full adder and also AND gates if neccesarry (via add_column_wire invocation) into list of circuit components
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obj_adder = FullAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), self.add_column_wire(column=col, bit=2), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
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self.add_component(obj_adder)
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# Update the number of current and next column wires
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self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
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# Update current and next column wires arrangement
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# add fa's generated sum to the bottom of current column
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# add fa's generated cout to the top of next column
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self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
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col += 1
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# Output generation
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# First output bit from single first pp AND gate
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self.out.connect(0, self.add_column_wire(column=0, bit=0))
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# Final addition of remaining bits
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# 1 bit multiplier case
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if self.N == 1:
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self.out.connect(1, ConstantWireValue0())
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# 2 bit multiplier case
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elif self.N == 2:
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obj_ha = HalfAdder(self.add_column_wire(column=1, bit=0), self.add_column_wire(column=1, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
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self.add_component(obj_ha)
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self.out.connect(1, obj_ha.get_sum_wire())
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obj_ha = HalfAdder(self.get_previous_component().get_carry_wire(), self.add_column_wire(column=2, bit=0), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
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self.add_component(obj_ha)
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self.out.connect(2, obj_ha.get_sum_wire())
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self.out.connect(3, obj_ha.get_carry_wire())
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# Final addition of remaining bits using chosen unsigned multi bit adder
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else:
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# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
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adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1)
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adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))])
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adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
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final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
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self.add_component(final_adder)
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[self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
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class SignedWallaceMultiplier(MultiplierCircuit):
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"""Class representing signed wallace multiplier.
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Signed wallace multiplier represents fast N-bit multiplier which utilizes
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the functionality of wallace tree reduction algorithm proposed by Chris Wallace and uses Baugh-Wooley algorithm
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to perform signed multiplication.
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First partial products are calculated for each bit pair that form the partial product multiplication columns.
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At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits,
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additional XOR gate serve the necessary sign extension.
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Wallace tree algorithm is described more in detail here:
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https://en.wikipedia.org/wiki/Wallace_tree
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It presents smaller circuit in area opposed to array multiplier but is slightly bigger then dadda because of less reduction stages.
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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prefix (str, optional): Prefix name of signed wallace multiplier. Defaults to "".
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name (str, optional): Name of signed wallace multiplier. Defaults to "s_wallace_cla".
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unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
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"""
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def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
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self.c_data_type = "int64_t"
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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# Initialize all columns partial products forming AND/NAND gates matrix based on Baugh-Wooley multiplication
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self.columns = self.init_column_heights(signed=True)
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# Not used for 1 bit multiplier
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if self.N != 1:
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# Adding constant wire with value 1 to achieve signedness based on Baugh-Wooley multiplication algorithm
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# (adding constant value bit to last column (with one bit) to combine them in XOR gate to get the correct final multplication output bit at the end)
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self.columns[self.N].insert(1, ConstantWireValue1())
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self.update_column_heights(curr_column=self.N, curr_height_change=1)
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# Perform reduction until all columns have 2 or less bits in them
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while not all(height <= 2 for (height, *_) in self.columns):
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col = 0
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while col < len(self.columns):
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# If column has exactly 3 bits in height and all previous columns has maximum of 2 bits in height, combine them in a half adder
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if self.get_column_height(col) == 3 and all(height <= 2 for (height, *_) in self.columns[0:col-1]):
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# Add half adder and also AND/NAND gates if neccesarry (via add_column_wire invocation) into list of circuit components
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obj_adder = HalfAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
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self.add_component(obj_adder)
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# Update the number of current and next column wires
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self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
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# Update current and next column wires arrangement
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# add ha's generated sum to the bottom of current column
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# add ha's generated cout to the top of next column
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self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
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# If column has more than 3 bits in height, combine them in a full adder
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elif self.get_column_height(col) > 3:
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# Add full adder and also AND/NAND gates if neccesarry (via add_column_wire invocation) into list of circuit components
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obj_adder = FullAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), self.add_column_wire(column=col, bit=2), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
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self.add_component(obj_adder)
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# Update the number of current and next column wires
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self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
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# Update current and next column wires arrangement
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# add fa's generated sum to the bottom of current column
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# add fa's generated cout to the top of next column
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self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
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col += 1
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# Output generation
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# First output bit from single first pp AND gate
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self.out.connect(0, self.add_column_wire(column=0, bit=0))
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# Final addition of remaining bits
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# 1 bit multiplier case
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if self.N == 1:
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self.out.connect(1, ConstantWireValue0())
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return
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# 2 bit multiplier case
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elif self.N == 2:
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obj_ha = HalfAdder(self.add_column_wire(column=1, bit=0), self.add_column_wire(column=1, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
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self.add_component(obj_ha)
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self.out.connect(1, obj_ha.get_sum_wire())
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obj_fa = FullAdder(self.get_previous_component().get_carry_wire(), self.add_column_wire(column=2, bit=0), self.add_column_wire(column=2, bit=1), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
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self.add_component(obj_fa)
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self.out.connect(2, obj_fa.get_sum_wire())
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self.out.connect(3, obj_fa.get_carry_wire())
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# Final addition of remaining bits using chosen unsigned multi bit adder
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else:
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# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
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adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1)
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adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))])
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adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
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final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
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self.add_component(final_adder)
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[self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
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# Final XOR to ensure proper sign extension
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obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
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self.add_component(obj_xor)
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self.out.connect(self.out.N-1, obj_xor.out)
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