33 lines
733 B
Verilog
33 lines
733 B
Verilog
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`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
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module add_signed_tb;
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reg signed [7:0] a;
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reg signed [7:0] b;
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wire signed [8:0] o;
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integer k, j;
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localparam period = 20;
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`dut dut(a, b, o); //.input_a(a), .input_b(b), .cgp_circuit_out(o));
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always
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begin
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for(k = -127; k < 128; k = k+1) begin
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for(j = -127; j < 128; j = j+1) begin
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assign a = k;
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assign b = j;
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#period;
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//$assert(b == 0);
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if ( k + j != o) begin
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$display("Invalid output: %d + %d = %d", a, b, o);
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end
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end;
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end;
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$finish;
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end
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endmodule |