56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
61 lines
2.3 KiB
Verilog
61 lines
2.3 KiB
Verilog
module u_cska4(input [3:0] a, input [3:0] b, output [4:0] u_cska4_out);
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wire u_cska4_xor0;
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wire u_cska4_ha0_xor0;
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wire u_cska4_ha0_and0;
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wire u_cska4_xor1;
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wire u_cska4_fa0_xor0;
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wire u_cska4_fa0_and0;
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wire u_cska4_fa0_xor1;
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wire u_cska4_fa0_and1;
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wire u_cska4_fa0_or0;
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wire u_cska4_xor2;
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wire u_cska4_fa1_xor0;
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wire u_cska4_fa1_and0;
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wire u_cska4_fa1_xor1;
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wire u_cska4_fa1_and1;
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wire u_cska4_fa1_or0;
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wire u_cska4_xor3;
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wire u_cska4_fa2_xor0;
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wire u_cska4_fa2_and0;
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wire u_cska4_fa2_xor1;
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wire u_cska4_fa2_and1;
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wire u_cska4_fa2_or0;
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wire u_cska4_and_propagate00;
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wire u_cska4_and_propagate01;
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wire u_cska4_and_propagate02;
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wire u_cska4_mux2to10_not0;
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wire u_cska4_mux2to10_and1;
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assign u_cska4_xor0 = a[0] ^ b[0];
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assign u_cska4_ha0_xor0 = a[0] ^ b[0];
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assign u_cska4_ha0_and0 = a[0] & b[0];
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assign u_cska4_xor1 = a[1] ^ b[1];
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assign u_cska4_fa0_xor0 = a[1] ^ b[1];
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assign u_cska4_fa0_and0 = a[1] & b[1];
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assign u_cska4_fa0_xor1 = u_cska4_fa0_xor0 ^ u_cska4_ha0_and0;
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assign u_cska4_fa0_and1 = u_cska4_fa0_xor0 & u_cska4_ha0_and0;
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assign u_cska4_fa0_or0 = u_cska4_fa0_and0 | u_cska4_fa0_and1;
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assign u_cska4_xor2 = a[2] ^ b[2];
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assign u_cska4_fa1_xor0 = a[2] ^ b[2];
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assign u_cska4_fa1_and0 = a[2] & b[2];
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assign u_cska4_fa1_xor1 = u_cska4_fa1_xor0 ^ u_cska4_fa0_or0;
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assign u_cska4_fa1_and1 = u_cska4_fa1_xor0 & u_cska4_fa0_or0;
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assign u_cska4_fa1_or0 = u_cska4_fa1_and0 | u_cska4_fa1_and1;
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assign u_cska4_xor3 = a[3] ^ b[3];
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assign u_cska4_fa2_xor0 = a[3] ^ b[3];
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assign u_cska4_fa2_and0 = a[3] & b[3];
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assign u_cska4_fa2_xor1 = u_cska4_fa2_xor0 ^ u_cska4_fa1_or0;
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assign u_cska4_fa2_and1 = u_cska4_fa2_xor0 & u_cska4_fa1_or0;
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assign u_cska4_fa2_or0 = u_cska4_fa2_and0 | u_cska4_fa2_and1;
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assign u_cska4_and_propagate00 = u_cska4_xor0 & u_cska4_xor2;
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assign u_cska4_and_propagate01 = u_cska4_xor1 & u_cska4_xor3;
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assign u_cska4_and_propagate02 = u_cska4_and_propagate00 & u_cska4_and_propagate01;
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assign u_cska4_mux2to10_not0 = ~u_cska4_and_propagate02;
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assign u_cska4_mux2to10_and1 = u_cska4_fa2_or0 & u_cska4_mux2to10_not0;
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assign u_cska4_out[0] = u_cska4_ha0_xor0;
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assign u_cska4_out[1] = u_cska4_fa0_xor1;
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assign u_cska4_out[2] = u_cska4_fa1_xor1;
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assign u_cska4_out[3] = u_cska4_fa2_xor1;
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assign u_cska4_out[4] = u_cska4_mux2to10_and1;
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endmodule |