56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
203 lines
8.0 KiB
Plaintext
203 lines
8.0 KiB
Plaintext
.model u_dadda_cla4
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.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
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.outputs u_dadda_cla4_out[0] u_dadda_cla4_out[1] u_dadda_cla4_out[2] u_dadda_cla4_out[3] u_dadda_cla4_out[4] u_dadda_cla4_out[5] u_dadda_cla4_out[6] u_dadda_cla4_out[7]
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=a[3] b=b[0] out=u_dadda_cla4_and_3_0
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.subckt and_gate a=a[2] b=b[1] out=u_dadda_cla4_and_2_1
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.subckt ha a=u_dadda_cla4_and_3_0 b=u_dadda_cla4_and_2_1 ha_xor0=u_dadda_cla4_ha0_xor0 ha_and0=u_dadda_cla4_ha0_and0
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.subckt and_gate a=a[3] b=b[1] out=u_dadda_cla4_and_3_1
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.subckt ha a=u_dadda_cla4_ha0_and0 b=u_dadda_cla4_and_3_1 ha_xor0=u_dadda_cla4_ha1_xor0 ha_and0=u_dadda_cla4_ha1_and0
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.subckt and_gate a=a[2] b=b[0] out=u_dadda_cla4_and_2_0
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.subckt and_gate a=a[1] b=b[1] out=u_dadda_cla4_and_1_1
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.subckt ha a=u_dadda_cla4_and_2_0 b=u_dadda_cla4_and_1_1 ha_xor0=u_dadda_cla4_ha2_xor0 ha_and0=u_dadda_cla4_ha2_and0
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.subckt and_gate a=a[1] b=b[2] out=u_dadda_cla4_and_1_2
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.subckt and_gate a=a[0] b=b[3] out=u_dadda_cla4_and_0_3
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.subckt fa a=u_dadda_cla4_ha2_and0 b=u_dadda_cla4_and_1_2 cin=u_dadda_cla4_and_0_3 fa_xor1=u_dadda_cla4_fa0_xor1 fa_or0=u_dadda_cla4_fa0_or0
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.subckt and_gate a=a[2] b=b[2] out=u_dadda_cla4_and_2_2
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.subckt and_gate a=a[1] b=b[3] out=u_dadda_cla4_and_1_3
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.subckt fa a=u_dadda_cla4_fa0_or0 b=u_dadda_cla4_and_2_2 cin=u_dadda_cla4_and_1_3 fa_xor1=u_dadda_cla4_fa1_xor1 fa_or0=u_dadda_cla4_fa1_or0
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.subckt and_gate a=a[3] b=b[2] out=u_dadda_cla4_and_3_2
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.subckt fa a=u_dadda_cla4_fa1_or0 b=u_dadda_cla4_ha1_and0 cin=u_dadda_cla4_and_3_2 fa_xor1=u_dadda_cla4_fa2_xor1 fa_or0=u_dadda_cla4_fa2_or0
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.subckt and_gate a=a[0] b=b[0] out=u_dadda_cla4_and_0_0
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.subckt and_gate a=a[1] b=b[0] out=u_dadda_cla4_and_1_0
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.subckt and_gate a=a[0] b=b[2] out=u_dadda_cla4_and_0_2
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.subckt and_gate a=a[2] b=b[3] out=u_dadda_cla4_and_2_3
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.subckt and_gate a=a[0] b=b[1] out=u_dadda_cla4_and_0_1
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.subckt and_gate a=a[3] b=b[3] out=u_dadda_cla4_and_3_3
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.names u_dadda_cla4_and_1_0 u_dadda_cla4_u_cla6_a[0]
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1 1
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.names u_dadda_cla4_and_0_2 u_dadda_cla4_u_cla6_a[1]
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1 1
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.names u_dadda_cla4_ha0_xor0 u_dadda_cla4_u_cla6_a[2]
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1 1
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.names u_dadda_cla4_ha1_xor0 u_dadda_cla4_u_cla6_a[3]
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1 1
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.names u_dadda_cla4_and_2_3 u_dadda_cla4_u_cla6_a[4]
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1 1
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.names u_dadda_cla4_fa2_or0 u_dadda_cla4_u_cla6_a[5]
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1 1
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.names u_dadda_cla4_and_0_1 u_dadda_cla4_u_cla6_b[0]
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1 1
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.names u_dadda_cla4_ha2_xor0 u_dadda_cla4_u_cla6_b[1]
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1 1
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.names u_dadda_cla4_fa0_xor1 u_dadda_cla4_u_cla6_b[2]
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1 1
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.names u_dadda_cla4_fa1_xor1 u_dadda_cla4_u_cla6_b[3]
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1 1
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.names u_dadda_cla4_fa2_xor1 u_dadda_cla4_u_cla6_b[4]
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1 1
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.names u_dadda_cla4_and_3_3 u_dadda_cla4_u_cla6_b[5]
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1 1
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.subckt u_cla6 a[0]=u_dadda_cla4_u_cla6_a[0] a[1]=u_dadda_cla4_u_cla6_a[1] a[2]=u_dadda_cla4_u_cla6_a[2] a[3]=u_dadda_cla4_u_cla6_a[3] a[4]=u_dadda_cla4_u_cla6_a[4] a[5]=u_dadda_cla4_u_cla6_a[5] b[0]=u_dadda_cla4_u_cla6_b[0] b[1]=u_dadda_cla4_u_cla6_b[1] b[2]=u_dadda_cla4_u_cla6_b[2] b[3]=u_dadda_cla4_u_cla6_b[3] b[4]=u_dadda_cla4_u_cla6_b[4] b[5]=u_dadda_cla4_u_cla6_b[5] u_cla6_out[0]=u_dadda_cla4_u_cla6_pg_logic0_xor0 u_cla6_out[1]=u_dadda_cla4_u_cla6_xor1 u_cla6_out[2]=u_dadda_cla4_u_cla6_xor2 u_cla6_out[3]=u_dadda_cla4_u_cla6_xor3 u_cla6_out[4]=u_dadda_cla4_u_cla6_xor4 u_cla6_out[5]=u_dadda_cla4_u_cla6_xor5 u_cla6_out[6]=u_dadda_cla4_u_cla6_or8
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.names u_dadda_cla4_and_0_0 u_dadda_cla4_out[0]
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1 1
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.names u_dadda_cla4_u_cla6_pg_logic0_xor0 u_dadda_cla4_out[1]
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1 1
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.names u_dadda_cla4_u_cla6_xor1 u_dadda_cla4_out[2]
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1 1
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.names u_dadda_cla4_u_cla6_xor2 u_dadda_cla4_out[3]
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1 1
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.names u_dadda_cla4_u_cla6_xor3 u_dadda_cla4_out[4]
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1 1
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.names u_dadda_cla4_u_cla6_xor4 u_dadda_cla4_out[5]
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1 1
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.names u_dadda_cla4_u_cla6_xor5 u_dadda_cla4_out[6]
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1 1
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.names u_dadda_cla4_u_cla6_or8 u_dadda_cla4_out[7]
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1 1
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.end
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.model u_cla6
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] b[0] b[1] b[2] b[3] b[4] b[5]
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.outputs u_cla6_out[0] u_cla6_out[1] u_cla6_out[2] u_cla6_out[3] u_cla6_out[4] u_cla6_out[5] u_cla6_out[6]
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.names vdd
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1
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.names gnd
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0
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.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=u_cla6_pg_logic0_or0 pg_logic_and0=u_cla6_pg_logic0_and0 pg_logic_xor0=u_cla6_pg_logic0_xor0
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.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=u_cla6_pg_logic1_or0 pg_logic_and0=u_cla6_pg_logic1_and0 pg_logic_xor0=u_cla6_pg_logic1_xor0
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.subckt xor_gate a=u_cla6_pg_logic1_xor0 b=u_cla6_pg_logic0_and0 out=u_cla6_xor1
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.subckt and_gate a=u_cla6_pg_logic0_and0 b=u_cla6_pg_logic1_or0 out=u_cla6_and0
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.subckt or_gate a=u_cla6_pg_logic1_and0 b=u_cla6_and0 out=u_cla6_or0
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.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=u_cla6_pg_logic2_or0 pg_logic_and0=u_cla6_pg_logic2_and0 pg_logic_xor0=u_cla6_pg_logic2_xor0
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.subckt xor_gate a=u_cla6_pg_logic2_xor0 b=u_cla6_or0 out=u_cla6_xor2
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.subckt and_gate a=u_cla6_pg_logic2_or0 b=u_cla6_pg_logic0_or0 out=u_cla6_and1
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.subckt and_gate a=u_cla6_pg_logic0_and0 b=u_cla6_pg_logic2_or0 out=u_cla6_and2
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.subckt and_gate a=u_cla6_and2 b=u_cla6_pg_logic1_or0 out=u_cla6_and3
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.subckt and_gate a=u_cla6_pg_logic1_and0 b=u_cla6_pg_logic2_or0 out=u_cla6_and4
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.subckt or_gate a=u_cla6_and3 b=u_cla6_and4 out=u_cla6_or1
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.subckt or_gate a=u_cla6_pg_logic2_and0 b=u_cla6_or1 out=u_cla6_or2
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.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=u_cla6_pg_logic3_or0 pg_logic_and0=u_cla6_pg_logic3_and0 pg_logic_xor0=u_cla6_pg_logic3_xor0
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.subckt xor_gate a=u_cla6_pg_logic3_xor0 b=u_cla6_or2 out=u_cla6_xor3
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.subckt and_gate a=u_cla6_pg_logic3_or0 b=u_cla6_pg_logic1_or0 out=u_cla6_and5
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.subckt and_gate a=u_cla6_pg_logic0_and0 b=u_cla6_pg_logic2_or0 out=u_cla6_and6
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.subckt and_gate a=u_cla6_pg_logic3_or0 b=u_cla6_pg_logic1_or0 out=u_cla6_and7
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.subckt and_gate a=u_cla6_and6 b=u_cla6_and7 out=u_cla6_and8
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.subckt and_gate a=u_cla6_pg_logic1_and0 b=u_cla6_pg_logic3_or0 out=u_cla6_and9
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.subckt and_gate a=u_cla6_and9 b=u_cla6_pg_logic2_or0 out=u_cla6_and10
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.subckt and_gate a=u_cla6_pg_logic2_and0 b=u_cla6_pg_logic3_or0 out=u_cla6_and11
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.subckt or_gate a=u_cla6_and8 b=u_cla6_and11 out=u_cla6_or3
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.subckt or_gate a=u_cla6_and10 b=u_cla6_or3 out=u_cla6_or4
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.subckt or_gate a=u_cla6_pg_logic3_and0 b=u_cla6_or4 out=u_cla6_or5
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.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=u_cla6_pg_logic4_or0 pg_logic_and0=u_cla6_pg_logic4_and0 pg_logic_xor0=u_cla6_pg_logic4_xor0
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.subckt xor_gate a=u_cla6_pg_logic4_xor0 b=u_cla6_or5 out=u_cla6_xor4
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.subckt and_gate a=u_cla6_or5 b=u_cla6_pg_logic4_or0 out=u_cla6_and12
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.subckt or_gate a=u_cla6_pg_logic4_and0 b=u_cla6_and12 out=u_cla6_or6
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.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=u_cla6_pg_logic5_or0 pg_logic_and0=u_cla6_pg_logic5_and0 pg_logic_xor0=u_cla6_pg_logic5_xor0
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.subckt xor_gate a=u_cla6_pg_logic5_xor0 b=u_cla6_or6 out=u_cla6_xor5
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.subckt and_gate a=u_cla6_or5 b=u_cla6_pg_logic5_or0 out=u_cla6_and13
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.subckt and_gate a=u_cla6_and13 b=u_cla6_pg_logic4_or0 out=u_cla6_and14
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.subckt and_gate a=u_cla6_pg_logic4_and0 b=u_cla6_pg_logic5_or0 out=u_cla6_and15
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.subckt or_gate a=u_cla6_and14 b=u_cla6_and15 out=u_cla6_or7
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.subckt or_gate a=u_cla6_pg_logic5_and0 b=u_cla6_or7 out=u_cla6_or8
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.names u_cla6_pg_logic0_xor0 u_cla6_out[0]
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1 1
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.names u_cla6_xor1 u_cla6_out[1]
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1 1
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.names u_cla6_xor2 u_cla6_out[2]
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1 1
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.names u_cla6_xor3 u_cla6_out[3]
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1 1
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.names u_cla6_xor4 u_cla6_out[4]
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1 1
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.names u_cla6_xor5 u_cla6_out[5]
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1 1
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.names u_cla6_or8 u_cla6_out[6]
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1 1
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.end
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.model pg_logic
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.inputs a b
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.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
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.names vdd
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1
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.names gnd
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0
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.subckt or_gate a=a b=b out=pg_logic_or0
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.subckt and_gate a=a b=b out=pg_logic_and0
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.subckt xor_gate a=a b=b out=pg_logic_xor0
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.end
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.model fa
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.inputs a b cin
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.outputs fa_xor1 fa_or0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=fa_xor0
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.subckt and_gate a=a b=b out=fa_and0
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.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
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.subckt and_gate a=fa_xor0 b=cin out=fa_and1
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.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
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.end
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.model ha
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.inputs a b
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.outputs ha_xor0 ha_and0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=ha_xor0
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.subckt and_gate a=a b=b out=ha_and0
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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