56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
115 lines
2.4 KiB
Plaintext
115 lines
2.4 KiB
Plaintext
.model u_cska4
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.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
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.outputs u_cska4_out[0] u_cska4_out[1] u_cska4_out[2] u_cska4_out[3] u_cska4_out[4]
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a[0] b=b[0] out=u_cska4_xor0
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.subckt ha a=a[0] b=b[0] ha_xor0=u_cska4_ha0_xor0 ha_and0=u_cska4_ha0_and0
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.subckt xor_gate a=a[1] b=b[1] out=u_cska4_xor1
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.subckt fa a=a[1] b=b[1] cin=u_cska4_ha0_and0 fa_xor1=u_cska4_fa0_xor1 fa_or0=u_cska4_fa0_or0
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.subckt xor_gate a=a[2] b=b[2] out=u_cska4_xor2
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.subckt fa a=a[2] b=b[2] cin=u_cska4_fa0_or0 fa_xor1=u_cska4_fa1_xor1 fa_or0=u_cska4_fa1_or0
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.subckt xor_gate a=a[3] b=b[3] out=u_cska4_xor3
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.subckt fa a=a[3] b=b[3] cin=u_cska4_fa1_or0 fa_xor1=u_cska4_fa2_xor1 fa_or0=u_cska4_fa2_or0
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.subckt and_gate a=u_cska4_xor0 b=u_cska4_xor2 out=u_cska4_and_propagate00
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.subckt and_gate a=u_cska4_xor1 b=u_cska4_xor3 out=u_cska4_and_propagate01
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.subckt and_gate a=u_cska4_and_propagate00 b=u_cska4_and_propagate01 out=u_cska4_and_propagate02
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.subckt mux2to1 d0=u_cska4_fa2_or0 d1=gnd sel=u_cska4_and_propagate02 mux2to1_xor0=u_cska4_mux2to10_and1
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.names u_cska4_ha0_xor0 u_cska4_out[0]
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1 1
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.names u_cska4_fa0_xor1 u_cska4_out[1]
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1 1
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.names u_cska4_fa1_xor1 u_cska4_out[2]
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1 1
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.names u_cska4_fa2_xor1 u_cska4_out[3]
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1 1
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.names u_cska4_mux2to10_and1 u_cska4_out[4]
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1 1
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.end
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.model mux2to1
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.inputs d0 d1 sel
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.outputs mux2to1_xor0
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=d1 b=sel out=mux2to1_and0
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.subckt not_gate a=sel out=mux2to1_not0
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.subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1
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.subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0
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.end
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.model fa
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.inputs a b cin
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.outputs fa_xor1 fa_or0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=fa_xor0
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.subckt and_gate a=a b=b out=fa_and0
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.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
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.subckt and_gate a=fa_xor0 b=cin out=fa_and1
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.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
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.end
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.model ha
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.inputs a b
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.outputs ha_xor0 ha_and0
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=ha_xor0
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.subckt and_gate a=a b=b out=ha_and0
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.end
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.model not_gate
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.inputs a
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a out
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0 1
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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