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ariths-gen-mig/generated_circuits/blif_circuits/hier/u_csamul_rca32.blif
Jan Klhůfek 56c86c13ca
New multipliers (#13) 
* #10 CGP Circuits as inputs (#11)

* CGP Circuits as inputs

* #10 support of signed output in general circuit

* input as output works

* output connected to input (c)

* automated verilog testing

* output rename

* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.

* Typos fix and code cleanup.

* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

* Updated automated testing scripts.

* Small bugfix in python code generation (I initially thought this line is useless).

* Updated generated circuits folder.

Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00

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.model u_csamul_rca32
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31]
.outputs u_csamul_rca32_out[0] u_csamul_rca32_out[1] u_csamul_rca32_out[2] u_csamul_rca32_out[3] u_csamul_rca32_out[4] u_csamul_rca32_out[5] u_csamul_rca32_out[6] u_csamul_rca32_out[7] u_csamul_rca32_out[8] u_csamul_rca32_out[9] u_csamul_rca32_out[10] u_csamul_rca32_out[11] u_csamul_rca32_out[12] u_csamul_rca32_out[13] u_csamul_rca32_out[14] u_csamul_rca32_out[15] u_csamul_rca32_out[16] u_csamul_rca32_out[17] u_csamul_rca32_out[18] u_csamul_rca32_out[19] u_csamul_rca32_out[20] u_csamul_rca32_out[21] u_csamul_rca32_out[22] u_csamul_rca32_out[23] u_csamul_rca32_out[24] u_csamul_rca32_out[25] u_csamul_rca32_out[26] u_csamul_rca32_out[27] u_csamul_rca32_out[28] u_csamul_rca32_out[29] u_csamul_rca32_out[30] u_csamul_rca32_out[31] u_csamul_rca32_out[32] u_csamul_rca32_out[33] u_csamul_rca32_out[34] u_csamul_rca32_out[35] u_csamul_rca32_out[36] u_csamul_rca32_out[37] u_csamul_rca32_out[38] u_csamul_rca32_out[39] u_csamul_rca32_out[40] u_csamul_rca32_out[41] u_csamul_rca32_out[42] u_csamul_rca32_out[43] u_csamul_rca32_out[44] u_csamul_rca32_out[45] u_csamul_rca32_out[46] u_csamul_rca32_out[47] u_csamul_rca32_out[48] u_csamul_rca32_out[49] u_csamul_rca32_out[50] u_csamul_rca32_out[51] u_csamul_rca32_out[52] u_csamul_rca32_out[53] u_csamul_rca32_out[54] u_csamul_rca32_out[55] u_csamul_rca32_out[56] u_csamul_rca32_out[57] u_csamul_rca32_out[58] u_csamul_rca32_out[59] u_csamul_rca32_out[60] u_csamul_rca32_out[61] u_csamul_rca32_out[62] u_csamul_rca32_out[63]
.names vdd
1
.names gnd
0
.subckt and_gate a=a[0] b=b[0] out=u_csamul_rca32_and0_0
.subckt and_gate a=a[1] b=b[0] out=u_csamul_rca32_and1_0
.subckt and_gate a=a[2] b=b[0] out=u_csamul_rca32_and2_0
.subckt and_gate a=a[3] b=b[0] out=u_csamul_rca32_and3_0
.subckt and_gate a=a[4] b=b[0] out=u_csamul_rca32_and4_0
.subckt and_gate a=a[5] b=b[0] out=u_csamul_rca32_and5_0
.subckt and_gate a=a[6] b=b[0] out=u_csamul_rca32_and6_0
.subckt and_gate a=a[7] b=b[0] out=u_csamul_rca32_and7_0
.subckt and_gate a=a[8] b=b[0] out=u_csamul_rca32_and8_0
.subckt and_gate a=a[9] b=b[0] out=u_csamul_rca32_and9_0
.subckt and_gate a=a[10] b=b[0] out=u_csamul_rca32_and10_0
.subckt and_gate a=a[11] b=b[0] out=u_csamul_rca32_and11_0
.subckt and_gate a=a[12] b=b[0] out=u_csamul_rca32_and12_0
.subckt and_gate a=a[13] b=b[0] out=u_csamul_rca32_and13_0
.subckt and_gate a=a[14] b=b[0] out=u_csamul_rca32_and14_0
.subckt and_gate a=a[15] b=b[0] out=u_csamul_rca32_and15_0
.subckt and_gate a=a[16] b=b[0] out=u_csamul_rca32_and16_0
.subckt and_gate a=a[17] b=b[0] out=u_csamul_rca32_and17_0
.subckt and_gate a=a[18] b=b[0] out=u_csamul_rca32_and18_0
.subckt and_gate a=a[19] b=b[0] out=u_csamul_rca32_and19_0
.subckt and_gate a=a[20] b=b[0] out=u_csamul_rca32_and20_0
.subckt and_gate a=a[21] b=b[0] out=u_csamul_rca32_and21_0
.subckt and_gate a=a[22] b=b[0] out=u_csamul_rca32_and22_0
.subckt and_gate a=a[23] b=b[0] out=u_csamul_rca32_and23_0
.subckt and_gate a=a[24] b=b[0] out=u_csamul_rca32_and24_0
.subckt and_gate a=a[25] b=b[0] out=u_csamul_rca32_and25_0
.subckt and_gate a=a[26] b=b[0] out=u_csamul_rca32_and26_0
.subckt and_gate a=a[27] b=b[0] out=u_csamul_rca32_and27_0
.subckt and_gate a=a[28] b=b[0] out=u_csamul_rca32_and28_0
.subckt and_gate a=a[29] b=b[0] out=u_csamul_rca32_and29_0
.subckt and_gate a=a[30] b=b[0] out=u_csamul_rca32_and30_0
.subckt and_gate a=a[31] b=b[0] out=u_csamul_rca32_and31_0
.subckt and_gate a=a[0] b=b[1] out=u_csamul_rca32_and0_1
.subckt ha a=u_csamul_rca32_and0_1 b=u_csamul_rca32_and1_0 ha_xor0=u_csamul_rca32_ha0_1_xor0 ha_and0=u_csamul_rca32_ha0_1_and0
.subckt and_gate a=a[1] b=b[1] out=u_csamul_rca32_and1_1
.subckt ha a=u_csamul_rca32_and1_1 b=u_csamul_rca32_and2_0 ha_xor0=u_csamul_rca32_ha1_1_xor0 ha_and0=u_csamul_rca32_ha1_1_and0
.subckt and_gate a=a[2] b=b[1] out=u_csamul_rca32_and2_1
.subckt ha a=u_csamul_rca32_and2_1 b=u_csamul_rca32_and3_0 ha_xor0=u_csamul_rca32_ha2_1_xor0 ha_and0=u_csamul_rca32_ha2_1_and0
.subckt and_gate a=a[3] b=b[1] out=u_csamul_rca32_and3_1
.subckt ha a=u_csamul_rca32_and3_1 b=u_csamul_rca32_and4_0 ha_xor0=u_csamul_rca32_ha3_1_xor0 ha_and0=u_csamul_rca32_ha3_1_and0
.subckt and_gate a=a[4] b=b[1] out=u_csamul_rca32_and4_1
.subckt ha a=u_csamul_rca32_and4_1 b=u_csamul_rca32_and5_0 ha_xor0=u_csamul_rca32_ha4_1_xor0 ha_and0=u_csamul_rca32_ha4_1_and0
.subckt and_gate a=a[5] b=b[1] out=u_csamul_rca32_and5_1
.subckt ha a=u_csamul_rca32_and5_1 b=u_csamul_rca32_and6_0 ha_xor0=u_csamul_rca32_ha5_1_xor0 ha_and0=u_csamul_rca32_ha5_1_and0
.subckt and_gate a=a[6] b=b[1] out=u_csamul_rca32_and6_1
.subckt ha a=u_csamul_rca32_and6_1 b=u_csamul_rca32_and7_0 ha_xor0=u_csamul_rca32_ha6_1_xor0 ha_and0=u_csamul_rca32_ha6_1_and0
.subckt and_gate a=a[7] b=b[1] out=u_csamul_rca32_and7_1
.subckt ha a=u_csamul_rca32_and7_1 b=u_csamul_rca32_and8_0 ha_xor0=u_csamul_rca32_ha7_1_xor0 ha_and0=u_csamul_rca32_ha7_1_and0
.subckt and_gate a=a[8] b=b[1] out=u_csamul_rca32_and8_1
.subckt ha a=u_csamul_rca32_and8_1 b=u_csamul_rca32_and9_0 ha_xor0=u_csamul_rca32_ha8_1_xor0 ha_and0=u_csamul_rca32_ha8_1_and0
.subckt and_gate a=a[9] b=b[1] out=u_csamul_rca32_and9_1
.subckt ha a=u_csamul_rca32_and9_1 b=u_csamul_rca32_and10_0 ha_xor0=u_csamul_rca32_ha9_1_xor0 ha_and0=u_csamul_rca32_ha9_1_and0
.subckt and_gate a=a[10] b=b[1] out=u_csamul_rca32_and10_1
.subckt ha a=u_csamul_rca32_and10_1 b=u_csamul_rca32_and11_0 ha_xor0=u_csamul_rca32_ha10_1_xor0 ha_and0=u_csamul_rca32_ha10_1_and0
.subckt and_gate a=a[11] b=b[1] out=u_csamul_rca32_and11_1
.subckt ha a=u_csamul_rca32_and11_1 b=u_csamul_rca32_and12_0 ha_xor0=u_csamul_rca32_ha11_1_xor0 ha_and0=u_csamul_rca32_ha11_1_and0
.subckt and_gate a=a[12] b=b[1] out=u_csamul_rca32_and12_1
.subckt ha a=u_csamul_rca32_and12_1 b=u_csamul_rca32_and13_0 ha_xor0=u_csamul_rca32_ha12_1_xor0 ha_and0=u_csamul_rca32_ha12_1_and0
.subckt and_gate a=a[13] b=b[1] out=u_csamul_rca32_and13_1
.subckt ha a=u_csamul_rca32_and13_1 b=u_csamul_rca32_and14_0 ha_xor0=u_csamul_rca32_ha13_1_xor0 ha_and0=u_csamul_rca32_ha13_1_and0
.subckt and_gate a=a[14] b=b[1] out=u_csamul_rca32_and14_1
.subckt ha a=u_csamul_rca32_and14_1 b=u_csamul_rca32_and15_0 ha_xor0=u_csamul_rca32_ha14_1_xor0 ha_and0=u_csamul_rca32_ha14_1_and0
.subckt and_gate a=a[15] b=b[1] out=u_csamul_rca32_and15_1
.subckt ha a=u_csamul_rca32_and15_1 b=u_csamul_rca32_and16_0 ha_xor0=u_csamul_rca32_ha15_1_xor0 ha_and0=u_csamul_rca32_ha15_1_and0
.subckt and_gate a=a[16] b=b[1] out=u_csamul_rca32_and16_1
.subckt ha a=u_csamul_rca32_and16_1 b=u_csamul_rca32_and17_0 ha_xor0=u_csamul_rca32_ha16_1_xor0 ha_and0=u_csamul_rca32_ha16_1_and0
.subckt and_gate a=a[17] b=b[1] out=u_csamul_rca32_and17_1
.subckt ha a=u_csamul_rca32_and17_1 b=u_csamul_rca32_and18_0 ha_xor0=u_csamul_rca32_ha17_1_xor0 ha_and0=u_csamul_rca32_ha17_1_and0
.subckt and_gate a=a[18] b=b[1] out=u_csamul_rca32_and18_1
.subckt ha a=u_csamul_rca32_and18_1 b=u_csamul_rca32_and19_0 ha_xor0=u_csamul_rca32_ha18_1_xor0 ha_and0=u_csamul_rca32_ha18_1_and0
.subckt and_gate a=a[19] b=b[1] out=u_csamul_rca32_and19_1
.subckt ha a=u_csamul_rca32_and19_1 b=u_csamul_rca32_and20_0 ha_xor0=u_csamul_rca32_ha19_1_xor0 ha_and0=u_csamul_rca32_ha19_1_and0
.subckt and_gate a=a[20] b=b[1] out=u_csamul_rca32_and20_1
.subckt ha a=u_csamul_rca32_and20_1 b=u_csamul_rca32_and21_0 ha_xor0=u_csamul_rca32_ha20_1_xor0 ha_and0=u_csamul_rca32_ha20_1_and0
.subckt and_gate a=a[21] b=b[1] out=u_csamul_rca32_and21_1
.subckt ha a=u_csamul_rca32_and21_1 b=u_csamul_rca32_and22_0 ha_xor0=u_csamul_rca32_ha21_1_xor0 ha_and0=u_csamul_rca32_ha21_1_and0
.subckt and_gate a=a[22] b=b[1] out=u_csamul_rca32_and22_1
.subckt ha a=u_csamul_rca32_and22_1 b=u_csamul_rca32_and23_0 ha_xor0=u_csamul_rca32_ha22_1_xor0 ha_and0=u_csamul_rca32_ha22_1_and0
.subckt and_gate a=a[23] b=b[1] out=u_csamul_rca32_and23_1
.subckt ha a=u_csamul_rca32_and23_1 b=u_csamul_rca32_and24_0 ha_xor0=u_csamul_rca32_ha23_1_xor0 ha_and0=u_csamul_rca32_ha23_1_and0
.subckt and_gate a=a[24] b=b[1] out=u_csamul_rca32_and24_1
.subckt ha a=u_csamul_rca32_and24_1 b=u_csamul_rca32_and25_0 ha_xor0=u_csamul_rca32_ha24_1_xor0 ha_and0=u_csamul_rca32_ha24_1_and0
.subckt and_gate a=a[25] b=b[1] out=u_csamul_rca32_and25_1
.subckt ha a=u_csamul_rca32_and25_1 b=u_csamul_rca32_and26_0 ha_xor0=u_csamul_rca32_ha25_1_xor0 ha_and0=u_csamul_rca32_ha25_1_and0
.subckt and_gate a=a[26] b=b[1] out=u_csamul_rca32_and26_1
.subckt ha a=u_csamul_rca32_and26_1 b=u_csamul_rca32_and27_0 ha_xor0=u_csamul_rca32_ha26_1_xor0 ha_and0=u_csamul_rca32_ha26_1_and0
.subckt and_gate a=a[27] b=b[1] out=u_csamul_rca32_and27_1
.subckt ha a=u_csamul_rca32_and27_1 b=u_csamul_rca32_and28_0 ha_xor0=u_csamul_rca32_ha27_1_xor0 ha_and0=u_csamul_rca32_ha27_1_and0
.subckt and_gate a=a[28] b=b[1] out=u_csamul_rca32_and28_1
.subckt ha a=u_csamul_rca32_and28_1 b=u_csamul_rca32_and29_0 ha_xor0=u_csamul_rca32_ha28_1_xor0 ha_and0=u_csamul_rca32_ha28_1_and0
.subckt and_gate a=a[29] b=b[1] out=u_csamul_rca32_and29_1
.subckt ha a=u_csamul_rca32_and29_1 b=u_csamul_rca32_and30_0 ha_xor0=u_csamul_rca32_ha29_1_xor0 ha_and0=u_csamul_rca32_ha29_1_and0
.subckt and_gate a=a[30] b=b[1] out=u_csamul_rca32_and30_1
.subckt ha a=u_csamul_rca32_and30_1 b=u_csamul_rca32_and31_0 ha_xor0=u_csamul_rca32_ha30_1_xor0 ha_and0=u_csamul_rca32_ha30_1_and0
.subckt and_gate a=a[31] b=b[1] out=u_csamul_rca32_and31_1
.subckt and_gate a=a[0] b=b[2] out=u_csamul_rca32_and0_2
.subckt fa a=u_csamul_rca32_and0_2 b=u_csamul_rca32_ha1_1_xor0 cin=u_csamul_rca32_ha0_1_and0 fa_xor1=u_csamul_rca32_fa0_2_xor1 fa_or0=u_csamul_rca32_fa0_2_or0
.subckt and_gate a=a[1] b=b[2] out=u_csamul_rca32_and1_2
.subckt fa a=u_csamul_rca32_and1_2 b=u_csamul_rca32_ha2_1_xor0 cin=u_csamul_rca32_ha1_1_and0 fa_xor1=u_csamul_rca32_fa1_2_xor1 fa_or0=u_csamul_rca32_fa1_2_or0
.subckt and_gate a=a[2] b=b[2] out=u_csamul_rca32_and2_2
.subckt fa a=u_csamul_rca32_and2_2 b=u_csamul_rca32_ha3_1_xor0 cin=u_csamul_rca32_ha2_1_and0 fa_xor1=u_csamul_rca32_fa2_2_xor1 fa_or0=u_csamul_rca32_fa2_2_or0
.subckt and_gate a=a[3] b=b[2] out=u_csamul_rca32_and3_2
.subckt fa a=u_csamul_rca32_and3_2 b=u_csamul_rca32_ha4_1_xor0 cin=u_csamul_rca32_ha3_1_and0 fa_xor1=u_csamul_rca32_fa3_2_xor1 fa_or0=u_csamul_rca32_fa3_2_or0
.subckt and_gate a=a[4] b=b[2] out=u_csamul_rca32_and4_2
.subckt fa a=u_csamul_rca32_and4_2 b=u_csamul_rca32_ha5_1_xor0 cin=u_csamul_rca32_ha4_1_and0 fa_xor1=u_csamul_rca32_fa4_2_xor1 fa_or0=u_csamul_rca32_fa4_2_or0
.subckt and_gate a=a[5] b=b[2] out=u_csamul_rca32_and5_2
.subckt fa a=u_csamul_rca32_and5_2 b=u_csamul_rca32_ha6_1_xor0 cin=u_csamul_rca32_ha5_1_and0 fa_xor1=u_csamul_rca32_fa5_2_xor1 fa_or0=u_csamul_rca32_fa5_2_or0
.subckt and_gate a=a[6] b=b[2] out=u_csamul_rca32_and6_2
.subckt fa a=u_csamul_rca32_and6_2 b=u_csamul_rca32_ha7_1_xor0 cin=u_csamul_rca32_ha6_1_and0 fa_xor1=u_csamul_rca32_fa6_2_xor1 fa_or0=u_csamul_rca32_fa6_2_or0
.subckt and_gate a=a[7] b=b[2] out=u_csamul_rca32_and7_2
.subckt fa a=u_csamul_rca32_and7_2 b=u_csamul_rca32_ha8_1_xor0 cin=u_csamul_rca32_ha7_1_and0 fa_xor1=u_csamul_rca32_fa7_2_xor1 fa_or0=u_csamul_rca32_fa7_2_or0
.subckt and_gate a=a[8] b=b[2] out=u_csamul_rca32_and8_2
.subckt fa a=u_csamul_rca32_and8_2 b=u_csamul_rca32_ha9_1_xor0 cin=u_csamul_rca32_ha8_1_and0 fa_xor1=u_csamul_rca32_fa8_2_xor1 fa_or0=u_csamul_rca32_fa8_2_or0
.subckt and_gate a=a[9] b=b[2] out=u_csamul_rca32_and9_2
.subckt fa a=u_csamul_rca32_and9_2 b=u_csamul_rca32_ha10_1_xor0 cin=u_csamul_rca32_ha9_1_and0 fa_xor1=u_csamul_rca32_fa9_2_xor1 fa_or0=u_csamul_rca32_fa9_2_or0
.subckt and_gate a=a[10] b=b[2] out=u_csamul_rca32_and10_2
.subckt fa a=u_csamul_rca32_and10_2 b=u_csamul_rca32_ha11_1_xor0 cin=u_csamul_rca32_ha10_1_and0 fa_xor1=u_csamul_rca32_fa10_2_xor1 fa_or0=u_csamul_rca32_fa10_2_or0
.subckt and_gate a=a[11] b=b[2] out=u_csamul_rca32_and11_2
.subckt fa a=u_csamul_rca32_and11_2 b=u_csamul_rca32_ha12_1_xor0 cin=u_csamul_rca32_ha11_1_and0 fa_xor1=u_csamul_rca32_fa11_2_xor1 fa_or0=u_csamul_rca32_fa11_2_or0
.subckt and_gate a=a[12] b=b[2] out=u_csamul_rca32_and12_2
.subckt fa a=u_csamul_rca32_and12_2 b=u_csamul_rca32_ha13_1_xor0 cin=u_csamul_rca32_ha12_1_and0 fa_xor1=u_csamul_rca32_fa12_2_xor1 fa_or0=u_csamul_rca32_fa12_2_or0
.subckt and_gate a=a[13] b=b[2] out=u_csamul_rca32_and13_2
.subckt fa a=u_csamul_rca32_and13_2 b=u_csamul_rca32_ha14_1_xor0 cin=u_csamul_rca32_ha13_1_and0 fa_xor1=u_csamul_rca32_fa13_2_xor1 fa_or0=u_csamul_rca32_fa13_2_or0
.subckt and_gate a=a[14] b=b[2] out=u_csamul_rca32_and14_2
.subckt fa a=u_csamul_rca32_and14_2 b=u_csamul_rca32_ha15_1_xor0 cin=u_csamul_rca32_ha14_1_and0 fa_xor1=u_csamul_rca32_fa14_2_xor1 fa_or0=u_csamul_rca32_fa14_2_or0
.subckt and_gate a=a[15] b=b[2] out=u_csamul_rca32_and15_2
.subckt fa a=u_csamul_rca32_and15_2 b=u_csamul_rca32_ha16_1_xor0 cin=u_csamul_rca32_ha15_1_and0 fa_xor1=u_csamul_rca32_fa15_2_xor1 fa_or0=u_csamul_rca32_fa15_2_or0
.subckt and_gate a=a[16] b=b[2] out=u_csamul_rca32_and16_2
.subckt fa a=u_csamul_rca32_and16_2 b=u_csamul_rca32_ha17_1_xor0 cin=u_csamul_rca32_ha16_1_and0 fa_xor1=u_csamul_rca32_fa16_2_xor1 fa_or0=u_csamul_rca32_fa16_2_or0
.subckt and_gate a=a[17] b=b[2] out=u_csamul_rca32_and17_2
.subckt fa a=u_csamul_rca32_and17_2 b=u_csamul_rca32_ha18_1_xor0 cin=u_csamul_rca32_ha17_1_and0 fa_xor1=u_csamul_rca32_fa17_2_xor1 fa_or0=u_csamul_rca32_fa17_2_or0
.subckt and_gate a=a[18] b=b[2] out=u_csamul_rca32_and18_2
.subckt fa a=u_csamul_rca32_and18_2 b=u_csamul_rca32_ha19_1_xor0 cin=u_csamul_rca32_ha18_1_and0 fa_xor1=u_csamul_rca32_fa18_2_xor1 fa_or0=u_csamul_rca32_fa18_2_or0
.subckt and_gate a=a[19] b=b[2] out=u_csamul_rca32_and19_2
.subckt fa a=u_csamul_rca32_and19_2 b=u_csamul_rca32_ha20_1_xor0 cin=u_csamul_rca32_ha19_1_and0 fa_xor1=u_csamul_rca32_fa19_2_xor1 fa_or0=u_csamul_rca32_fa19_2_or0
.subckt and_gate a=a[20] b=b[2] out=u_csamul_rca32_and20_2
.subckt fa a=u_csamul_rca32_and20_2 b=u_csamul_rca32_ha21_1_xor0 cin=u_csamul_rca32_ha20_1_and0 fa_xor1=u_csamul_rca32_fa20_2_xor1 fa_or0=u_csamul_rca32_fa20_2_or0
.subckt and_gate a=a[21] b=b[2] out=u_csamul_rca32_and21_2
.subckt fa a=u_csamul_rca32_and21_2 b=u_csamul_rca32_ha22_1_xor0 cin=u_csamul_rca32_ha21_1_and0 fa_xor1=u_csamul_rca32_fa21_2_xor1 fa_or0=u_csamul_rca32_fa21_2_or0
.subckt and_gate a=a[22] b=b[2] out=u_csamul_rca32_and22_2
.subckt fa a=u_csamul_rca32_and22_2 b=u_csamul_rca32_ha23_1_xor0 cin=u_csamul_rca32_ha22_1_and0 fa_xor1=u_csamul_rca32_fa22_2_xor1 fa_or0=u_csamul_rca32_fa22_2_or0
.subckt and_gate a=a[23] b=b[2] out=u_csamul_rca32_and23_2
.subckt fa a=u_csamul_rca32_and23_2 b=u_csamul_rca32_ha24_1_xor0 cin=u_csamul_rca32_ha23_1_and0 fa_xor1=u_csamul_rca32_fa23_2_xor1 fa_or0=u_csamul_rca32_fa23_2_or0
.subckt and_gate a=a[24] b=b[2] out=u_csamul_rca32_and24_2
.subckt fa a=u_csamul_rca32_and24_2 b=u_csamul_rca32_ha25_1_xor0 cin=u_csamul_rca32_ha24_1_and0 fa_xor1=u_csamul_rca32_fa24_2_xor1 fa_or0=u_csamul_rca32_fa24_2_or0
.subckt and_gate a=a[25] b=b[2] out=u_csamul_rca32_and25_2
.subckt fa a=u_csamul_rca32_and25_2 b=u_csamul_rca32_ha26_1_xor0 cin=u_csamul_rca32_ha25_1_and0 fa_xor1=u_csamul_rca32_fa25_2_xor1 fa_or0=u_csamul_rca32_fa25_2_or0
.subckt and_gate a=a[26] b=b[2] out=u_csamul_rca32_and26_2
.subckt fa a=u_csamul_rca32_and26_2 b=u_csamul_rca32_ha27_1_xor0 cin=u_csamul_rca32_ha26_1_and0 fa_xor1=u_csamul_rca32_fa26_2_xor1 fa_or0=u_csamul_rca32_fa26_2_or0
.subckt and_gate a=a[27] b=b[2] out=u_csamul_rca32_and27_2
.subckt fa a=u_csamul_rca32_and27_2 b=u_csamul_rca32_ha28_1_xor0 cin=u_csamul_rca32_ha27_1_and0 fa_xor1=u_csamul_rca32_fa27_2_xor1 fa_or0=u_csamul_rca32_fa27_2_or0
.subckt and_gate a=a[28] b=b[2] out=u_csamul_rca32_and28_2
.subckt fa a=u_csamul_rca32_and28_2 b=u_csamul_rca32_ha29_1_xor0 cin=u_csamul_rca32_ha28_1_and0 fa_xor1=u_csamul_rca32_fa28_2_xor1 fa_or0=u_csamul_rca32_fa28_2_or0
.subckt and_gate a=a[29] b=b[2] out=u_csamul_rca32_and29_2
.subckt fa a=u_csamul_rca32_and29_2 b=u_csamul_rca32_ha30_1_xor0 cin=u_csamul_rca32_ha29_1_and0 fa_xor1=u_csamul_rca32_fa29_2_xor1 fa_or0=u_csamul_rca32_fa29_2_or0
.subckt and_gate a=a[30] b=b[2] out=u_csamul_rca32_and30_2
.subckt fa a=u_csamul_rca32_and30_2 b=u_csamul_rca32_and31_1 cin=u_csamul_rca32_ha30_1_and0 fa_xor1=u_csamul_rca32_fa30_2_xor1 fa_or0=u_csamul_rca32_fa30_2_or0
.subckt and_gate a=a[31] b=b[2] out=u_csamul_rca32_and31_2
.subckt and_gate a=a[0] b=b[3] out=u_csamul_rca32_and0_3
.subckt fa a=u_csamul_rca32_and0_3 b=u_csamul_rca32_fa1_2_xor1 cin=u_csamul_rca32_fa0_2_or0 fa_xor1=u_csamul_rca32_fa0_3_xor1 fa_or0=u_csamul_rca32_fa0_3_or0
.subckt and_gate a=a[1] b=b[3] out=u_csamul_rca32_and1_3
.subckt fa a=u_csamul_rca32_and1_3 b=u_csamul_rca32_fa2_2_xor1 cin=u_csamul_rca32_fa1_2_or0 fa_xor1=u_csamul_rca32_fa1_3_xor1 fa_or0=u_csamul_rca32_fa1_3_or0
.subckt and_gate a=a[2] b=b[3] out=u_csamul_rca32_and2_3
.subckt fa a=u_csamul_rca32_and2_3 b=u_csamul_rca32_fa3_2_xor1 cin=u_csamul_rca32_fa2_2_or0 fa_xor1=u_csamul_rca32_fa2_3_xor1 fa_or0=u_csamul_rca32_fa2_3_or0
.subckt and_gate a=a[3] b=b[3] out=u_csamul_rca32_and3_3
.subckt fa a=u_csamul_rca32_and3_3 b=u_csamul_rca32_fa4_2_xor1 cin=u_csamul_rca32_fa3_2_or0 fa_xor1=u_csamul_rca32_fa3_3_xor1 fa_or0=u_csamul_rca32_fa3_3_or0
.subckt and_gate a=a[4] b=b[3] out=u_csamul_rca32_and4_3
.subckt fa a=u_csamul_rca32_and4_3 b=u_csamul_rca32_fa5_2_xor1 cin=u_csamul_rca32_fa4_2_or0 fa_xor1=u_csamul_rca32_fa4_3_xor1 fa_or0=u_csamul_rca32_fa4_3_or0
.subckt and_gate a=a[5] b=b[3] out=u_csamul_rca32_and5_3
.subckt fa a=u_csamul_rca32_and5_3 b=u_csamul_rca32_fa6_2_xor1 cin=u_csamul_rca32_fa5_2_or0 fa_xor1=u_csamul_rca32_fa5_3_xor1 fa_or0=u_csamul_rca32_fa5_3_or0
.subckt and_gate a=a[6] b=b[3] out=u_csamul_rca32_and6_3
.subckt fa a=u_csamul_rca32_and6_3 b=u_csamul_rca32_fa7_2_xor1 cin=u_csamul_rca32_fa6_2_or0 fa_xor1=u_csamul_rca32_fa6_3_xor1 fa_or0=u_csamul_rca32_fa6_3_or0
.subckt and_gate a=a[7] b=b[3] out=u_csamul_rca32_and7_3
.subckt fa a=u_csamul_rca32_and7_3 b=u_csamul_rca32_fa8_2_xor1 cin=u_csamul_rca32_fa7_2_or0 fa_xor1=u_csamul_rca32_fa7_3_xor1 fa_or0=u_csamul_rca32_fa7_3_or0
.subckt and_gate a=a[8] b=b[3] out=u_csamul_rca32_and8_3
.subckt fa a=u_csamul_rca32_and8_3 b=u_csamul_rca32_fa9_2_xor1 cin=u_csamul_rca32_fa8_2_or0 fa_xor1=u_csamul_rca32_fa8_3_xor1 fa_or0=u_csamul_rca32_fa8_3_or0
.subckt and_gate a=a[9] b=b[3] out=u_csamul_rca32_and9_3
.subckt fa a=u_csamul_rca32_and9_3 b=u_csamul_rca32_fa10_2_xor1 cin=u_csamul_rca32_fa9_2_or0 fa_xor1=u_csamul_rca32_fa9_3_xor1 fa_or0=u_csamul_rca32_fa9_3_or0
.subckt and_gate a=a[10] b=b[3] out=u_csamul_rca32_and10_3
.subckt fa a=u_csamul_rca32_and10_3 b=u_csamul_rca32_fa11_2_xor1 cin=u_csamul_rca32_fa10_2_or0 fa_xor1=u_csamul_rca32_fa10_3_xor1 fa_or0=u_csamul_rca32_fa10_3_or0
.subckt and_gate a=a[11] b=b[3] out=u_csamul_rca32_and11_3
.subckt fa a=u_csamul_rca32_and11_3 b=u_csamul_rca32_fa12_2_xor1 cin=u_csamul_rca32_fa11_2_or0 fa_xor1=u_csamul_rca32_fa11_3_xor1 fa_or0=u_csamul_rca32_fa11_3_or0
.subckt and_gate a=a[12] b=b[3] out=u_csamul_rca32_and12_3
.subckt fa a=u_csamul_rca32_and12_3 b=u_csamul_rca32_fa13_2_xor1 cin=u_csamul_rca32_fa12_2_or0 fa_xor1=u_csamul_rca32_fa12_3_xor1 fa_or0=u_csamul_rca32_fa12_3_or0
.subckt and_gate a=a[13] b=b[3] out=u_csamul_rca32_and13_3
.subckt fa a=u_csamul_rca32_and13_3 b=u_csamul_rca32_fa14_2_xor1 cin=u_csamul_rca32_fa13_2_or0 fa_xor1=u_csamul_rca32_fa13_3_xor1 fa_or0=u_csamul_rca32_fa13_3_or0
.subckt and_gate a=a[14] b=b[3] out=u_csamul_rca32_and14_3
.subckt fa a=u_csamul_rca32_and14_3 b=u_csamul_rca32_fa15_2_xor1 cin=u_csamul_rca32_fa14_2_or0 fa_xor1=u_csamul_rca32_fa14_3_xor1 fa_or0=u_csamul_rca32_fa14_3_or0
.subckt and_gate a=a[15] b=b[3] out=u_csamul_rca32_and15_3
.subckt fa a=u_csamul_rca32_and15_3 b=u_csamul_rca32_fa16_2_xor1 cin=u_csamul_rca32_fa15_2_or0 fa_xor1=u_csamul_rca32_fa15_3_xor1 fa_or0=u_csamul_rca32_fa15_3_or0
.subckt and_gate a=a[16] b=b[3] out=u_csamul_rca32_and16_3
.subckt fa a=u_csamul_rca32_and16_3 b=u_csamul_rca32_fa17_2_xor1 cin=u_csamul_rca32_fa16_2_or0 fa_xor1=u_csamul_rca32_fa16_3_xor1 fa_or0=u_csamul_rca32_fa16_3_or0
.subckt and_gate a=a[17] b=b[3] out=u_csamul_rca32_and17_3
.subckt fa a=u_csamul_rca32_and17_3 b=u_csamul_rca32_fa18_2_xor1 cin=u_csamul_rca32_fa17_2_or0 fa_xor1=u_csamul_rca32_fa17_3_xor1 fa_or0=u_csamul_rca32_fa17_3_or0
.subckt and_gate a=a[18] b=b[3] out=u_csamul_rca32_and18_3
.subckt fa a=u_csamul_rca32_and18_3 b=u_csamul_rca32_fa19_2_xor1 cin=u_csamul_rca32_fa18_2_or0 fa_xor1=u_csamul_rca32_fa18_3_xor1 fa_or0=u_csamul_rca32_fa18_3_or0
.subckt and_gate a=a[19] b=b[3] out=u_csamul_rca32_and19_3
.subckt fa a=u_csamul_rca32_and19_3 b=u_csamul_rca32_fa20_2_xor1 cin=u_csamul_rca32_fa19_2_or0 fa_xor1=u_csamul_rca32_fa19_3_xor1 fa_or0=u_csamul_rca32_fa19_3_or0
.subckt and_gate a=a[20] b=b[3] out=u_csamul_rca32_and20_3
.subckt fa a=u_csamul_rca32_and20_3 b=u_csamul_rca32_fa21_2_xor1 cin=u_csamul_rca32_fa20_2_or0 fa_xor1=u_csamul_rca32_fa20_3_xor1 fa_or0=u_csamul_rca32_fa20_3_or0
.subckt and_gate a=a[21] b=b[3] out=u_csamul_rca32_and21_3
.subckt fa a=u_csamul_rca32_and21_3 b=u_csamul_rca32_fa22_2_xor1 cin=u_csamul_rca32_fa21_2_or0 fa_xor1=u_csamul_rca32_fa21_3_xor1 fa_or0=u_csamul_rca32_fa21_3_or0
.subckt and_gate a=a[22] b=b[3] out=u_csamul_rca32_and22_3
.subckt fa a=u_csamul_rca32_and22_3 b=u_csamul_rca32_fa23_2_xor1 cin=u_csamul_rca32_fa22_2_or0 fa_xor1=u_csamul_rca32_fa22_3_xor1 fa_or0=u_csamul_rca32_fa22_3_or0
.subckt and_gate a=a[23] b=b[3] out=u_csamul_rca32_and23_3
.subckt fa a=u_csamul_rca32_and23_3 b=u_csamul_rca32_fa24_2_xor1 cin=u_csamul_rca32_fa23_2_or0 fa_xor1=u_csamul_rca32_fa23_3_xor1 fa_or0=u_csamul_rca32_fa23_3_or0
.subckt and_gate a=a[24] b=b[3] out=u_csamul_rca32_and24_3
.subckt fa a=u_csamul_rca32_and24_3 b=u_csamul_rca32_fa25_2_xor1 cin=u_csamul_rca32_fa24_2_or0 fa_xor1=u_csamul_rca32_fa24_3_xor1 fa_or0=u_csamul_rca32_fa24_3_or0
.subckt and_gate a=a[25] b=b[3] out=u_csamul_rca32_and25_3
.subckt fa a=u_csamul_rca32_and25_3 b=u_csamul_rca32_fa26_2_xor1 cin=u_csamul_rca32_fa25_2_or0 fa_xor1=u_csamul_rca32_fa25_3_xor1 fa_or0=u_csamul_rca32_fa25_3_or0
.subckt and_gate a=a[26] b=b[3] out=u_csamul_rca32_and26_3
.subckt fa a=u_csamul_rca32_and26_3 b=u_csamul_rca32_fa27_2_xor1 cin=u_csamul_rca32_fa26_2_or0 fa_xor1=u_csamul_rca32_fa26_3_xor1 fa_or0=u_csamul_rca32_fa26_3_or0
.subckt and_gate a=a[27] b=b[3] out=u_csamul_rca32_and27_3
.subckt fa a=u_csamul_rca32_and27_3 b=u_csamul_rca32_fa28_2_xor1 cin=u_csamul_rca32_fa27_2_or0 fa_xor1=u_csamul_rca32_fa27_3_xor1 fa_or0=u_csamul_rca32_fa27_3_or0
.subckt and_gate a=a[28] b=b[3] out=u_csamul_rca32_and28_3
.subckt fa a=u_csamul_rca32_and28_3 b=u_csamul_rca32_fa29_2_xor1 cin=u_csamul_rca32_fa28_2_or0 fa_xor1=u_csamul_rca32_fa28_3_xor1 fa_or0=u_csamul_rca32_fa28_3_or0
.subckt and_gate a=a[29] b=b[3] out=u_csamul_rca32_and29_3
.subckt fa a=u_csamul_rca32_and29_3 b=u_csamul_rca32_fa30_2_xor1 cin=u_csamul_rca32_fa29_2_or0 fa_xor1=u_csamul_rca32_fa29_3_xor1 fa_or0=u_csamul_rca32_fa29_3_or0
.subckt and_gate a=a[30] b=b[3] out=u_csamul_rca32_and30_3
.subckt fa a=u_csamul_rca32_and30_3 b=u_csamul_rca32_and31_2 cin=u_csamul_rca32_fa30_2_or0 fa_xor1=u_csamul_rca32_fa30_3_xor1 fa_or0=u_csamul_rca32_fa30_3_or0
.subckt and_gate a=a[31] b=b[3] out=u_csamul_rca32_and31_3
.subckt and_gate a=a[0] b=b[4] out=u_csamul_rca32_and0_4
.subckt fa a=u_csamul_rca32_and0_4 b=u_csamul_rca32_fa1_3_xor1 cin=u_csamul_rca32_fa0_3_or0 fa_xor1=u_csamul_rca32_fa0_4_xor1 fa_or0=u_csamul_rca32_fa0_4_or0
.subckt and_gate a=a[1] b=b[4] out=u_csamul_rca32_and1_4
.subckt fa a=u_csamul_rca32_and1_4 b=u_csamul_rca32_fa2_3_xor1 cin=u_csamul_rca32_fa1_3_or0 fa_xor1=u_csamul_rca32_fa1_4_xor1 fa_or0=u_csamul_rca32_fa1_4_or0
.subckt and_gate a=a[2] b=b[4] out=u_csamul_rca32_and2_4
.subckt fa a=u_csamul_rca32_and2_4 b=u_csamul_rca32_fa3_3_xor1 cin=u_csamul_rca32_fa2_3_or0 fa_xor1=u_csamul_rca32_fa2_4_xor1 fa_or0=u_csamul_rca32_fa2_4_or0
.subckt and_gate a=a[3] b=b[4] out=u_csamul_rca32_and3_4
.subckt fa a=u_csamul_rca32_and3_4 b=u_csamul_rca32_fa4_3_xor1 cin=u_csamul_rca32_fa3_3_or0 fa_xor1=u_csamul_rca32_fa3_4_xor1 fa_or0=u_csamul_rca32_fa3_4_or0
.subckt and_gate a=a[4] b=b[4] out=u_csamul_rca32_and4_4
.subckt fa a=u_csamul_rca32_and4_4 b=u_csamul_rca32_fa5_3_xor1 cin=u_csamul_rca32_fa4_3_or0 fa_xor1=u_csamul_rca32_fa4_4_xor1 fa_or0=u_csamul_rca32_fa4_4_or0
.subckt and_gate a=a[5] b=b[4] out=u_csamul_rca32_and5_4
.subckt fa a=u_csamul_rca32_and5_4 b=u_csamul_rca32_fa6_3_xor1 cin=u_csamul_rca32_fa5_3_or0 fa_xor1=u_csamul_rca32_fa5_4_xor1 fa_or0=u_csamul_rca32_fa5_4_or0
.subckt and_gate a=a[6] b=b[4] out=u_csamul_rca32_and6_4
.subckt fa a=u_csamul_rca32_and6_4 b=u_csamul_rca32_fa7_3_xor1 cin=u_csamul_rca32_fa6_3_or0 fa_xor1=u_csamul_rca32_fa6_4_xor1 fa_or0=u_csamul_rca32_fa6_4_or0
.subckt and_gate a=a[7] b=b[4] out=u_csamul_rca32_and7_4
.subckt fa a=u_csamul_rca32_and7_4 b=u_csamul_rca32_fa8_3_xor1 cin=u_csamul_rca32_fa7_3_or0 fa_xor1=u_csamul_rca32_fa7_4_xor1 fa_or0=u_csamul_rca32_fa7_4_or0
.subckt and_gate a=a[8] b=b[4] out=u_csamul_rca32_and8_4
.subckt fa a=u_csamul_rca32_and8_4 b=u_csamul_rca32_fa9_3_xor1 cin=u_csamul_rca32_fa8_3_or0 fa_xor1=u_csamul_rca32_fa8_4_xor1 fa_or0=u_csamul_rca32_fa8_4_or0
.subckt and_gate a=a[9] b=b[4] out=u_csamul_rca32_and9_4
.subckt fa a=u_csamul_rca32_and9_4 b=u_csamul_rca32_fa10_3_xor1 cin=u_csamul_rca32_fa9_3_or0 fa_xor1=u_csamul_rca32_fa9_4_xor1 fa_or0=u_csamul_rca32_fa9_4_or0
.subckt and_gate a=a[10] b=b[4] out=u_csamul_rca32_and10_4
.subckt fa a=u_csamul_rca32_and10_4 b=u_csamul_rca32_fa11_3_xor1 cin=u_csamul_rca32_fa10_3_or0 fa_xor1=u_csamul_rca32_fa10_4_xor1 fa_or0=u_csamul_rca32_fa10_4_or0
.subckt and_gate a=a[11] b=b[4] out=u_csamul_rca32_and11_4
.subckt fa a=u_csamul_rca32_and11_4 b=u_csamul_rca32_fa12_3_xor1 cin=u_csamul_rca32_fa11_3_or0 fa_xor1=u_csamul_rca32_fa11_4_xor1 fa_or0=u_csamul_rca32_fa11_4_or0
.subckt and_gate a=a[12] b=b[4] out=u_csamul_rca32_and12_4
.subckt fa a=u_csamul_rca32_and12_4 b=u_csamul_rca32_fa13_3_xor1 cin=u_csamul_rca32_fa12_3_or0 fa_xor1=u_csamul_rca32_fa12_4_xor1 fa_or0=u_csamul_rca32_fa12_4_or0
.subckt and_gate a=a[13] b=b[4] out=u_csamul_rca32_and13_4
.subckt fa a=u_csamul_rca32_and13_4 b=u_csamul_rca32_fa14_3_xor1 cin=u_csamul_rca32_fa13_3_or0 fa_xor1=u_csamul_rca32_fa13_4_xor1 fa_or0=u_csamul_rca32_fa13_4_or0
.subckt and_gate a=a[14] b=b[4] out=u_csamul_rca32_and14_4
.subckt fa a=u_csamul_rca32_and14_4 b=u_csamul_rca32_fa15_3_xor1 cin=u_csamul_rca32_fa14_3_or0 fa_xor1=u_csamul_rca32_fa14_4_xor1 fa_or0=u_csamul_rca32_fa14_4_or0
.subckt and_gate a=a[15] b=b[4] out=u_csamul_rca32_and15_4
.subckt fa a=u_csamul_rca32_and15_4 b=u_csamul_rca32_fa16_3_xor1 cin=u_csamul_rca32_fa15_3_or0 fa_xor1=u_csamul_rca32_fa15_4_xor1 fa_or0=u_csamul_rca32_fa15_4_or0
.subckt and_gate a=a[16] b=b[4] out=u_csamul_rca32_and16_4
.subckt fa a=u_csamul_rca32_and16_4 b=u_csamul_rca32_fa17_3_xor1 cin=u_csamul_rca32_fa16_3_or0 fa_xor1=u_csamul_rca32_fa16_4_xor1 fa_or0=u_csamul_rca32_fa16_4_or0
.subckt and_gate a=a[17] b=b[4] out=u_csamul_rca32_and17_4
.subckt fa a=u_csamul_rca32_and17_4 b=u_csamul_rca32_fa18_3_xor1 cin=u_csamul_rca32_fa17_3_or0 fa_xor1=u_csamul_rca32_fa17_4_xor1 fa_or0=u_csamul_rca32_fa17_4_or0
.subckt and_gate a=a[18] b=b[4] out=u_csamul_rca32_and18_4
.subckt fa a=u_csamul_rca32_and18_4 b=u_csamul_rca32_fa19_3_xor1 cin=u_csamul_rca32_fa18_3_or0 fa_xor1=u_csamul_rca32_fa18_4_xor1 fa_or0=u_csamul_rca32_fa18_4_or0
.subckt and_gate a=a[19] b=b[4] out=u_csamul_rca32_and19_4
.subckt fa a=u_csamul_rca32_and19_4 b=u_csamul_rca32_fa20_3_xor1 cin=u_csamul_rca32_fa19_3_or0 fa_xor1=u_csamul_rca32_fa19_4_xor1 fa_or0=u_csamul_rca32_fa19_4_or0
.subckt and_gate a=a[20] b=b[4] out=u_csamul_rca32_and20_4
.subckt fa a=u_csamul_rca32_and20_4 b=u_csamul_rca32_fa21_3_xor1 cin=u_csamul_rca32_fa20_3_or0 fa_xor1=u_csamul_rca32_fa20_4_xor1 fa_or0=u_csamul_rca32_fa20_4_or0
.subckt and_gate a=a[21] b=b[4] out=u_csamul_rca32_and21_4
.subckt fa a=u_csamul_rca32_and21_4 b=u_csamul_rca32_fa22_3_xor1 cin=u_csamul_rca32_fa21_3_or0 fa_xor1=u_csamul_rca32_fa21_4_xor1 fa_or0=u_csamul_rca32_fa21_4_or0
.subckt and_gate a=a[22] b=b[4] out=u_csamul_rca32_and22_4
.subckt fa a=u_csamul_rca32_and22_4 b=u_csamul_rca32_fa23_3_xor1 cin=u_csamul_rca32_fa22_3_or0 fa_xor1=u_csamul_rca32_fa22_4_xor1 fa_or0=u_csamul_rca32_fa22_4_or0
.subckt and_gate a=a[23] b=b[4] out=u_csamul_rca32_and23_4
.subckt fa a=u_csamul_rca32_and23_4 b=u_csamul_rca32_fa24_3_xor1 cin=u_csamul_rca32_fa23_3_or0 fa_xor1=u_csamul_rca32_fa23_4_xor1 fa_or0=u_csamul_rca32_fa23_4_or0
.subckt and_gate a=a[24] b=b[4] out=u_csamul_rca32_and24_4
.subckt fa a=u_csamul_rca32_and24_4 b=u_csamul_rca32_fa25_3_xor1 cin=u_csamul_rca32_fa24_3_or0 fa_xor1=u_csamul_rca32_fa24_4_xor1 fa_or0=u_csamul_rca32_fa24_4_or0
.subckt and_gate a=a[25] b=b[4] out=u_csamul_rca32_and25_4
.subckt fa a=u_csamul_rca32_and25_4 b=u_csamul_rca32_fa26_3_xor1 cin=u_csamul_rca32_fa25_3_or0 fa_xor1=u_csamul_rca32_fa25_4_xor1 fa_or0=u_csamul_rca32_fa25_4_or0
.subckt and_gate a=a[26] b=b[4] out=u_csamul_rca32_and26_4
.subckt fa a=u_csamul_rca32_and26_4 b=u_csamul_rca32_fa27_3_xor1 cin=u_csamul_rca32_fa26_3_or0 fa_xor1=u_csamul_rca32_fa26_4_xor1 fa_or0=u_csamul_rca32_fa26_4_or0
.subckt and_gate a=a[27] b=b[4] out=u_csamul_rca32_and27_4
.subckt fa a=u_csamul_rca32_and27_4 b=u_csamul_rca32_fa28_3_xor1 cin=u_csamul_rca32_fa27_3_or0 fa_xor1=u_csamul_rca32_fa27_4_xor1 fa_or0=u_csamul_rca32_fa27_4_or0
.subckt and_gate a=a[28] b=b[4] out=u_csamul_rca32_and28_4
.subckt fa a=u_csamul_rca32_and28_4 b=u_csamul_rca32_fa29_3_xor1 cin=u_csamul_rca32_fa28_3_or0 fa_xor1=u_csamul_rca32_fa28_4_xor1 fa_or0=u_csamul_rca32_fa28_4_or0
.subckt and_gate a=a[29] b=b[4] out=u_csamul_rca32_and29_4
.subckt fa a=u_csamul_rca32_and29_4 b=u_csamul_rca32_fa30_3_xor1 cin=u_csamul_rca32_fa29_3_or0 fa_xor1=u_csamul_rca32_fa29_4_xor1 fa_or0=u_csamul_rca32_fa29_4_or0
.subckt and_gate a=a[30] b=b[4] out=u_csamul_rca32_and30_4
.subckt fa a=u_csamul_rca32_and30_4 b=u_csamul_rca32_and31_3 cin=u_csamul_rca32_fa30_3_or0 fa_xor1=u_csamul_rca32_fa30_4_xor1 fa_or0=u_csamul_rca32_fa30_4_or0
.subckt and_gate a=a[31] b=b[4] out=u_csamul_rca32_and31_4
.subckt and_gate a=a[0] b=b[5] out=u_csamul_rca32_and0_5
.subckt fa a=u_csamul_rca32_and0_5 b=u_csamul_rca32_fa1_4_xor1 cin=u_csamul_rca32_fa0_4_or0 fa_xor1=u_csamul_rca32_fa0_5_xor1 fa_or0=u_csamul_rca32_fa0_5_or0
.subckt and_gate a=a[1] b=b[5] out=u_csamul_rca32_and1_5
.subckt fa a=u_csamul_rca32_and1_5 b=u_csamul_rca32_fa2_4_xor1 cin=u_csamul_rca32_fa1_4_or0 fa_xor1=u_csamul_rca32_fa1_5_xor1 fa_or0=u_csamul_rca32_fa1_5_or0
.subckt and_gate a=a[2] b=b[5] out=u_csamul_rca32_and2_5
.subckt fa a=u_csamul_rca32_and2_5 b=u_csamul_rca32_fa3_4_xor1 cin=u_csamul_rca32_fa2_4_or0 fa_xor1=u_csamul_rca32_fa2_5_xor1 fa_or0=u_csamul_rca32_fa2_5_or0
.subckt and_gate a=a[3] b=b[5] out=u_csamul_rca32_and3_5
.subckt fa a=u_csamul_rca32_and3_5 b=u_csamul_rca32_fa4_4_xor1 cin=u_csamul_rca32_fa3_4_or0 fa_xor1=u_csamul_rca32_fa3_5_xor1 fa_or0=u_csamul_rca32_fa3_5_or0
.subckt and_gate a=a[4] b=b[5] out=u_csamul_rca32_and4_5
.subckt fa a=u_csamul_rca32_and4_5 b=u_csamul_rca32_fa5_4_xor1 cin=u_csamul_rca32_fa4_4_or0 fa_xor1=u_csamul_rca32_fa4_5_xor1 fa_or0=u_csamul_rca32_fa4_5_or0
.subckt and_gate a=a[5] b=b[5] out=u_csamul_rca32_and5_5
.subckt fa a=u_csamul_rca32_and5_5 b=u_csamul_rca32_fa6_4_xor1 cin=u_csamul_rca32_fa5_4_or0 fa_xor1=u_csamul_rca32_fa5_5_xor1 fa_or0=u_csamul_rca32_fa5_5_or0
.subckt and_gate a=a[6] b=b[5] out=u_csamul_rca32_and6_5
.subckt fa a=u_csamul_rca32_and6_5 b=u_csamul_rca32_fa7_4_xor1 cin=u_csamul_rca32_fa6_4_or0 fa_xor1=u_csamul_rca32_fa6_5_xor1 fa_or0=u_csamul_rca32_fa6_5_or0
.subckt and_gate a=a[7] b=b[5] out=u_csamul_rca32_and7_5
.subckt fa a=u_csamul_rca32_and7_5 b=u_csamul_rca32_fa8_4_xor1 cin=u_csamul_rca32_fa7_4_or0 fa_xor1=u_csamul_rca32_fa7_5_xor1 fa_or0=u_csamul_rca32_fa7_5_or0
.subckt and_gate a=a[8] b=b[5] out=u_csamul_rca32_and8_5
.subckt fa a=u_csamul_rca32_and8_5 b=u_csamul_rca32_fa9_4_xor1 cin=u_csamul_rca32_fa8_4_or0 fa_xor1=u_csamul_rca32_fa8_5_xor1 fa_or0=u_csamul_rca32_fa8_5_or0
.subckt and_gate a=a[9] b=b[5] out=u_csamul_rca32_and9_5
.subckt fa a=u_csamul_rca32_and9_5 b=u_csamul_rca32_fa10_4_xor1 cin=u_csamul_rca32_fa9_4_or0 fa_xor1=u_csamul_rca32_fa9_5_xor1 fa_or0=u_csamul_rca32_fa9_5_or0
.subckt and_gate a=a[10] b=b[5] out=u_csamul_rca32_and10_5
.subckt fa a=u_csamul_rca32_and10_5 b=u_csamul_rca32_fa11_4_xor1 cin=u_csamul_rca32_fa10_4_or0 fa_xor1=u_csamul_rca32_fa10_5_xor1 fa_or0=u_csamul_rca32_fa10_5_or0
.subckt and_gate a=a[11] b=b[5] out=u_csamul_rca32_and11_5
.subckt fa a=u_csamul_rca32_and11_5 b=u_csamul_rca32_fa12_4_xor1 cin=u_csamul_rca32_fa11_4_or0 fa_xor1=u_csamul_rca32_fa11_5_xor1 fa_or0=u_csamul_rca32_fa11_5_or0
.subckt and_gate a=a[12] b=b[5] out=u_csamul_rca32_and12_5
.subckt fa a=u_csamul_rca32_and12_5 b=u_csamul_rca32_fa13_4_xor1 cin=u_csamul_rca32_fa12_4_or0 fa_xor1=u_csamul_rca32_fa12_5_xor1 fa_or0=u_csamul_rca32_fa12_5_or0
.subckt and_gate a=a[13] b=b[5] out=u_csamul_rca32_and13_5
.subckt fa a=u_csamul_rca32_and13_5 b=u_csamul_rca32_fa14_4_xor1 cin=u_csamul_rca32_fa13_4_or0 fa_xor1=u_csamul_rca32_fa13_5_xor1 fa_or0=u_csamul_rca32_fa13_5_or0
.subckt and_gate a=a[14] b=b[5] out=u_csamul_rca32_and14_5
.subckt fa a=u_csamul_rca32_and14_5 b=u_csamul_rca32_fa15_4_xor1 cin=u_csamul_rca32_fa14_4_or0 fa_xor1=u_csamul_rca32_fa14_5_xor1 fa_or0=u_csamul_rca32_fa14_5_or0
.subckt and_gate a=a[15] b=b[5] out=u_csamul_rca32_and15_5
.subckt fa a=u_csamul_rca32_and15_5 b=u_csamul_rca32_fa16_4_xor1 cin=u_csamul_rca32_fa15_4_or0 fa_xor1=u_csamul_rca32_fa15_5_xor1 fa_or0=u_csamul_rca32_fa15_5_or0
.subckt and_gate a=a[16] b=b[5] out=u_csamul_rca32_and16_5
.subckt fa a=u_csamul_rca32_and16_5 b=u_csamul_rca32_fa17_4_xor1 cin=u_csamul_rca32_fa16_4_or0 fa_xor1=u_csamul_rca32_fa16_5_xor1 fa_or0=u_csamul_rca32_fa16_5_or0
.subckt and_gate a=a[17] b=b[5] out=u_csamul_rca32_and17_5
.subckt fa a=u_csamul_rca32_and17_5 b=u_csamul_rca32_fa18_4_xor1 cin=u_csamul_rca32_fa17_4_or0 fa_xor1=u_csamul_rca32_fa17_5_xor1 fa_or0=u_csamul_rca32_fa17_5_or0
.subckt and_gate a=a[18] b=b[5] out=u_csamul_rca32_and18_5
.subckt fa a=u_csamul_rca32_and18_5 b=u_csamul_rca32_fa19_4_xor1 cin=u_csamul_rca32_fa18_4_or0 fa_xor1=u_csamul_rca32_fa18_5_xor1 fa_or0=u_csamul_rca32_fa18_5_or0
.subckt and_gate a=a[19] b=b[5] out=u_csamul_rca32_and19_5
.subckt fa a=u_csamul_rca32_and19_5 b=u_csamul_rca32_fa20_4_xor1 cin=u_csamul_rca32_fa19_4_or0 fa_xor1=u_csamul_rca32_fa19_5_xor1 fa_or0=u_csamul_rca32_fa19_5_or0
.subckt and_gate a=a[20] b=b[5] out=u_csamul_rca32_and20_5
.subckt fa a=u_csamul_rca32_and20_5 b=u_csamul_rca32_fa21_4_xor1 cin=u_csamul_rca32_fa20_4_or0 fa_xor1=u_csamul_rca32_fa20_5_xor1 fa_or0=u_csamul_rca32_fa20_5_or0
.subckt and_gate a=a[21] b=b[5] out=u_csamul_rca32_and21_5
.subckt fa a=u_csamul_rca32_and21_5 b=u_csamul_rca32_fa22_4_xor1 cin=u_csamul_rca32_fa21_4_or0 fa_xor1=u_csamul_rca32_fa21_5_xor1 fa_or0=u_csamul_rca32_fa21_5_or0
.subckt and_gate a=a[22] b=b[5] out=u_csamul_rca32_and22_5
.subckt fa a=u_csamul_rca32_and22_5 b=u_csamul_rca32_fa23_4_xor1 cin=u_csamul_rca32_fa22_4_or0 fa_xor1=u_csamul_rca32_fa22_5_xor1 fa_or0=u_csamul_rca32_fa22_5_or0
.subckt and_gate a=a[23] b=b[5] out=u_csamul_rca32_and23_5
.subckt fa a=u_csamul_rca32_and23_5 b=u_csamul_rca32_fa24_4_xor1 cin=u_csamul_rca32_fa23_4_or0 fa_xor1=u_csamul_rca32_fa23_5_xor1 fa_or0=u_csamul_rca32_fa23_5_or0
.subckt and_gate a=a[24] b=b[5] out=u_csamul_rca32_and24_5
.subckt fa a=u_csamul_rca32_and24_5 b=u_csamul_rca32_fa25_4_xor1 cin=u_csamul_rca32_fa24_4_or0 fa_xor1=u_csamul_rca32_fa24_5_xor1 fa_or0=u_csamul_rca32_fa24_5_or0
.subckt and_gate a=a[25] b=b[5] out=u_csamul_rca32_and25_5
.subckt fa a=u_csamul_rca32_and25_5 b=u_csamul_rca32_fa26_4_xor1 cin=u_csamul_rca32_fa25_4_or0 fa_xor1=u_csamul_rca32_fa25_5_xor1 fa_or0=u_csamul_rca32_fa25_5_or0
.subckt and_gate a=a[26] b=b[5] out=u_csamul_rca32_and26_5
.subckt fa a=u_csamul_rca32_and26_5 b=u_csamul_rca32_fa27_4_xor1 cin=u_csamul_rca32_fa26_4_or0 fa_xor1=u_csamul_rca32_fa26_5_xor1 fa_or0=u_csamul_rca32_fa26_5_or0
.subckt and_gate a=a[27] b=b[5] out=u_csamul_rca32_and27_5
.subckt fa a=u_csamul_rca32_and27_5 b=u_csamul_rca32_fa28_4_xor1 cin=u_csamul_rca32_fa27_4_or0 fa_xor1=u_csamul_rca32_fa27_5_xor1 fa_or0=u_csamul_rca32_fa27_5_or0
.subckt and_gate a=a[28] b=b[5] out=u_csamul_rca32_and28_5
.subckt fa a=u_csamul_rca32_and28_5 b=u_csamul_rca32_fa29_4_xor1 cin=u_csamul_rca32_fa28_4_or0 fa_xor1=u_csamul_rca32_fa28_5_xor1 fa_or0=u_csamul_rca32_fa28_5_or0
.subckt and_gate a=a[29] b=b[5] out=u_csamul_rca32_and29_5
.subckt fa a=u_csamul_rca32_and29_5 b=u_csamul_rca32_fa30_4_xor1 cin=u_csamul_rca32_fa29_4_or0 fa_xor1=u_csamul_rca32_fa29_5_xor1 fa_or0=u_csamul_rca32_fa29_5_or0
.subckt and_gate a=a[30] b=b[5] out=u_csamul_rca32_and30_5
.subckt fa a=u_csamul_rca32_and30_5 b=u_csamul_rca32_and31_4 cin=u_csamul_rca32_fa30_4_or0 fa_xor1=u_csamul_rca32_fa30_5_xor1 fa_or0=u_csamul_rca32_fa30_5_or0
.subckt and_gate a=a[31] b=b[5] out=u_csamul_rca32_and31_5
.subckt and_gate a=a[0] b=b[6] out=u_csamul_rca32_and0_6
.subckt fa a=u_csamul_rca32_and0_6 b=u_csamul_rca32_fa1_5_xor1 cin=u_csamul_rca32_fa0_5_or0 fa_xor1=u_csamul_rca32_fa0_6_xor1 fa_or0=u_csamul_rca32_fa0_6_or0
.subckt and_gate a=a[1] b=b[6] out=u_csamul_rca32_and1_6
.subckt fa a=u_csamul_rca32_and1_6 b=u_csamul_rca32_fa2_5_xor1 cin=u_csamul_rca32_fa1_5_or0 fa_xor1=u_csamul_rca32_fa1_6_xor1 fa_or0=u_csamul_rca32_fa1_6_or0
.subckt and_gate a=a[2] b=b[6] out=u_csamul_rca32_and2_6
.subckt fa a=u_csamul_rca32_and2_6 b=u_csamul_rca32_fa3_5_xor1 cin=u_csamul_rca32_fa2_5_or0 fa_xor1=u_csamul_rca32_fa2_6_xor1 fa_or0=u_csamul_rca32_fa2_6_or0
.subckt and_gate a=a[3] b=b[6] out=u_csamul_rca32_and3_6
.subckt fa a=u_csamul_rca32_and3_6 b=u_csamul_rca32_fa4_5_xor1 cin=u_csamul_rca32_fa3_5_or0 fa_xor1=u_csamul_rca32_fa3_6_xor1 fa_or0=u_csamul_rca32_fa3_6_or0
.subckt and_gate a=a[4] b=b[6] out=u_csamul_rca32_and4_6
.subckt fa a=u_csamul_rca32_and4_6 b=u_csamul_rca32_fa5_5_xor1 cin=u_csamul_rca32_fa4_5_or0 fa_xor1=u_csamul_rca32_fa4_6_xor1 fa_or0=u_csamul_rca32_fa4_6_or0
.subckt and_gate a=a[5] b=b[6] out=u_csamul_rca32_and5_6
.subckt fa a=u_csamul_rca32_and5_6 b=u_csamul_rca32_fa6_5_xor1 cin=u_csamul_rca32_fa5_5_or0 fa_xor1=u_csamul_rca32_fa5_6_xor1 fa_or0=u_csamul_rca32_fa5_6_or0
.subckt and_gate a=a[6] b=b[6] out=u_csamul_rca32_and6_6
.subckt fa a=u_csamul_rca32_and6_6 b=u_csamul_rca32_fa7_5_xor1 cin=u_csamul_rca32_fa6_5_or0 fa_xor1=u_csamul_rca32_fa6_6_xor1 fa_or0=u_csamul_rca32_fa6_6_or0
.subckt and_gate a=a[7] b=b[6] out=u_csamul_rca32_and7_6
.subckt fa a=u_csamul_rca32_and7_6 b=u_csamul_rca32_fa8_5_xor1 cin=u_csamul_rca32_fa7_5_or0 fa_xor1=u_csamul_rca32_fa7_6_xor1 fa_or0=u_csamul_rca32_fa7_6_or0
.subckt and_gate a=a[8] b=b[6] out=u_csamul_rca32_and8_6
.subckt fa a=u_csamul_rca32_and8_6 b=u_csamul_rca32_fa9_5_xor1 cin=u_csamul_rca32_fa8_5_or0 fa_xor1=u_csamul_rca32_fa8_6_xor1 fa_or0=u_csamul_rca32_fa8_6_or0
.subckt and_gate a=a[9] b=b[6] out=u_csamul_rca32_and9_6
.subckt fa a=u_csamul_rca32_and9_6 b=u_csamul_rca32_fa10_5_xor1 cin=u_csamul_rca32_fa9_5_or0 fa_xor1=u_csamul_rca32_fa9_6_xor1 fa_or0=u_csamul_rca32_fa9_6_or0
.subckt and_gate a=a[10] b=b[6] out=u_csamul_rca32_and10_6
.subckt fa a=u_csamul_rca32_and10_6 b=u_csamul_rca32_fa11_5_xor1 cin=u_csamul_rca32_fa10_5_or0 fa_xor1=u_csamul_rca32_fa10_6_xor1 fa_or0=u_csamul_rca32_fa10_6_or0
.subckt and_gate a=a[11] b=b[6] out=u_csamul_rca32_and11_6
.subckt fa a=u_csamul_rca32_and11_6 b=u_csamul_rca32_fa12_5_xor1 cin=u_csamul_rca32_fa11_5_or0 fa_xor1=u_csamul_rca32_fa11_6_xor1 fa_or0=u_csamul_rca32_fa11_6_or0
.subckt and_gate a=a[12] b=b[6] out=u_csamul_rca32_and12_6
.subckt fa a=u_csamul_rca32_and12_6 b=u_csamul_rca32_fa13_5_xor1 cin=u_csamul_rca32_fa12_5_or0 fa_xor1=u_csamul_rca32_fa12_6_xor1 fa_or0=u_csamul_rca32_fa12_6_or0
.subckt and_gate a=a[13] b=b[6] out=u_csamul_rca32_and13_6
.subckt fa a=u_csamul_rca32_and13_6 b=u_csamul_rca32_fa14_5_xor1 cin=u_csamul_rca32_fa13_5_or0 fa_xor1=u_csamul_rca32_fa13_6_xor1 fa_or0=u_csamul_rca32_fa13_6_or0
.subckt and_gate a=a[14] b=b[6] out=u_csamul_rca32_and14_6
.subckt fa a=u_csamul_rca32_and14_6 b=u_csamul_rca32_fa15_5_xor1 cin=u_csamul_rca32_fa14_5_or0 fa_xor1=u_csamul_rca32_fa14_6_xor1 fa_or0=u_csamul_rca32_fa14_6_or0
.subckt and_gate a=a[15] b=b[6] out=u_csamul_rca32_and15_6
.subckt fa a=u_csamul_rca32_and15_6 b=u_csamul_rca32_fa16_5_xor1 cin=u_csamul_rca32_fa15_5_or0 fa_xor1=u_csamul_rca32_fa15_6_xor1 fa_or0=u_csamul_rca32_fa15_6_or0
.subckt and_gate a=a[16] b=b[6] out=u_csamul_rca32_and16_6
.subckt fa a=u_csamul_rca32_and16_6 b=u_csamul_rca32_fa17_5_xor1 cin=u_csamul_rca32_fa16_5_or0 fa_xor1=u_csamul_rca32_fa16_6_xor1 fa_or0=u_csamul_rca32_fa16_6_or0
.subckt and_gate a=a[17] b=b[6] out=u_csamul_rca32_and17_6
.subckt fa a=u_csamul_rca32_and17_6 b=u_csamul_rca32_fa18_5_xor1 cin=u_csamul_rca32_fa17_5_or0 fa_xor1=u_csamul_rca32_fa17_6_xor1 fa_or0=u_csamul_rca32_fa17_6_or0
.subckt and_gate a=a[18] b=b[6] out=u_csamul_rca32_and18_6
.subckt fa a=u_csamul_rca32_and18_6 b=u_csamul_rca32_fa19_5_xor1 cin=u_csamul_rca32_fa18_5_or0 fa_xor1=u_csamul_rca32_fa18_6_xor1 fa_or0=u_csamul_rca32_fa18_6_or0
.subckt and_gate a=a[19] b=b[6] out=u_csamul_rca32_and19_6
.subckt fa a=u_csamul_rca32_and19_6 b=u_csamul_rca32_fa20_5_xor1 cin=u_csamul_rca32_fa19_5_or0 fa_xor1=u_csamul_rca32_fa19_6_xor1 fa_or0=u_csamul_rca32_fa19_6_or0
.subckt and_gate a=a[20] b=b[6] out=u_csamul_rca32_and20_6
.subckt fa a=u_csamul_rca32_and20_6 b=u_csamul_rca32_fa21_5_xor1 cin=u_csamul_rca32_fa20_5_or0 fa_xor1=u_csamul_rca32_fa20_6_xor1 fa_or0=u_csamul_rca32_fa20_6_or0
.subckt and_gate a=a[21] b=b[6] out=u_csamul_rca32_and21_6
.subckt fa a=u_csamul_rca32_and21_6 b=u_csamul_rca32_fa22_5_xor1 cin=u_csamul_rca32_fa21_5_or0 fa_xor1=u_csamul_rca32_fa21_6_xor1 fa_or0=u_csamul_rca32_fa21_6_or0
.subckt and_gate a=a[22] b=b[6] out=u_csamul_rca32_and22_6
.subckt fa a=u_csamul_rca32_and22_6 b=u_csamul_rca32_fa23_5_xor1 cin=u_csamul_rca32_fa22_5_or0 fa_xor1=u_csamul_rca32_fa22_6_xor1 fa_or0=u_csamul_rca32_fa22_6_or0
.subckt and_gate a=a[23] b=b[6] out=u_csamul_rca32_and23_6
.subckt fa a=u_csamul_rca32_and23_6 b=u_csamul_rca32_fa24_5_xor1 cin=u_csamul_rca32_fa23_5_or0 fa_xor1=u_csamul_rca32_fa23_6_xor1 fa_or0=u_csamul_rca32_fa23_6_or0
.subckt and_gate a=a[24] b=b[6] out=u_csamul_rca32_and24_6
.subckt fa a=u_csamul_rca32_and24_6 b=u_csamul_rca32_fa25_5_xor1 cin=u_csamul_rca32_fa24_5_or0 fa_xor1=u_csamul_rca32_fa24_6_xor1 fa_or0=u_csamul_rca32_fa24_6_or0
.subckt and_gate a=a[25] b=b[6] out=u_csamul_rca32_and25_6
.subckt fa a=u_csamul_rca32_and25_6 b=u_csamul_rca32_fa26_5_xor1 cin=u_csamul_rca32_fa25_5_or0 fa_xor1=u_csamul_rca32_fa25_6_xor1 fa_or0=u_csamul_rca32_fa25_6_or0
.subckt and_gate a=a[26] b=b[6] out=u_csamul_rca32_and26_6
.subckt fa a=u_csamul_rca32_and26_6 b=u_csamul_rca32_fa27_5_xor1 cin=u_csamul_rca32_fa26_5_or0 fa_xor1=u_csamul_rca32_fa26_6_xor1 fa_or0=u_csamul_rca32_fa26_6_or0
.subckt and_gate a=a[27] b=b[6] out=u_csamul_rca32_and27_6
.subckt fa a=u_csamul_rca32_and27_6 b=u_csamul_rca32_fa28_5_xor1 cin=u_csamul_rca32_fa27_5_or0 fa_xor1=u_csamul_rca32_fa27_6_xor1 fa_or0=u_csamul_rca32_fa27_6_or0
.subckt and_gate a=a[28] b=b[6] out=u_csamul_rca32_and28_6
.subckt fa a=u_csamul_rca32_and28_6 b=u_csamul_rca32_fa29_5_xor1 cin=u_csamul_rca32_fa28_5_or0 fa_xor1=u_csamul_rca32_fa28_6_xor1 fa_or0=u_csamul_rca32_fa28_6_or0
.subckt and_gate a=a[29] b=b[6] out=u_csamul_rca32_and29_6
.subckt fa a=u_csamul_rca32_and29_6 b=u_csamul_rca32_fa30_5_xor1 cin=u_csamul_rca32_fa29_5_or0 fa_xor1=u_csamul_rca32_fa29_6_xor1 fa_or0=u_csamul_rca32_fa29_6_or0
.subckt and_gate a=a[30] b=b[6] out=u_csamul_rca32_and30_6
.subckt fa a=u_csamul_rca32_and30_6 b=u_csamul_rca32_and31_5 cin=u_csamul_rca32_fa30_5_or0 fa_xor1=u_csamul_rca32_fa30_6_xor1 fa_or0=u_csamul_rca32_fa30_6_or0
.subckt and_gate a=a[31] b=b[6] out=u_csamul_rca32_and31_6
.subckt and_gate a=a[0] b=b[7] out=u_csamul_rca32_and0_7
.subckt fa a=u_csamul_rca32_and0_7 b=u_csamul_rca32_fa1_6_xor1 cin=u_csamul_rca32_fa0_6_or0 fa_xor1=u_csamul_rca32_fa0_7_xor1 fa_or0=u_csamul_rca32_fa0_7_or0
.subckt and_gate a=a[1] b=b[7] out=u_csamul_rca32_and1_7
.subckt fa a=u_csamul_rca32_and1_7 b=u_csamul_rca32_fa2_6_xor1 cin=u_csamul_rca32_fa1_6_or0 fa_xor1=u_csamul_rca32_fa1_7_xor1 fa_or0=u_csamul_rca32_fa1_7_or0
.subckt and_gate a=a[2] b=b[7] out=u_csamul_rca32_and2_7
.subckt fa a=u_csamul_rca32_and2_7 b=u_csamul_rca32_fa3_6_xor1 cin=u_csamul_rca32_fa2_6_or0 fa_xor1=u_csamul_rca32_fa2_7_xor1 fa_or0=u_csamul_rca32_fa2_7_or0
.subckt and_gate a=a[3] b=b[7] out=u_csamul_rca32_and3_7
.subckt fa a=u_csamul_rca32_and3_7 b=u_csamul_rca32_fa4_6_xor1 cin=u_csamul_rca32_fa3_6_or0 fa_xor1=u_csamul_rca32_fa3_7_xor1 fa_or0=u_csamul_rca32_fa3_7_or0
.subckt and_gate a=a[4] b=b[7] out=u_csamul_rca32_and4_7
.subckt fa a=u_csamul_rca32_and4_7 b=u_csamul_rca32_fa5_6_xor1 cin=u_csamul_rca32_fa4_6_or0 fa_xor1=u_csamul_rca32_fa4_7_xor1 fa_or0=u_csamul_rca32_fa4_7_or0
.subckt and_gate a=a[5] b=b[7] out=u_csamul_rca32_and5_7
.subckt fa a=u_csamul_rca32_and5_7 b=u_csamul_rca32_fa6_6_xor1 cin=u_csamul_rca32_fa5_6_or0 fa_xor1=u_csamul_rca32_fa5_7_xor1 fa_or0=u_csamul_rca32_fa5_7_or0
.subckt and_gate a=a[6] b=b[7] out=u_csamul_rca32_and6_7
.subckt fa a=u_csamul_rca32_and6_7 b=u_csamul_rca32_fa7_6_xor1 cin=u_csamul_rca32_fa6_6_or0 fa_xor1=u_csamul_rca32_fa6_7_xor1 fa_or0=u_csamul_rca32_fa6_7_or0
.subckt and_gate a=a[7] b=b[7] out=u_csamul_rca32_and7_7
.subckt fa a=u_csamul_rca32_and7_7 b=u_csamul_rca32_fa8_6_xor1 cin=u_csamul_rca32_fa7_6_or0 fa_xor1=u_csamul_rca32_fa7_7_xor1 fa_or0=u_csamul_rca32_fa7_7_or0
.subckt and_gate a=a[8] b=b[7] out=u_csamul_rca32_and8_7
.subckt fa a=u_csamul_rca32_and8_7 b=u_csamul_rca32_fa9_6_xor1 cin=u_csamul_rca32_fa8_6_or0 fa_xor1=u_csamul_rca32_fa8_7_xor1 fa_or0=u_csamul_rca32_fa8_7_or0
.subckt and_gate a=a[9] b=b[7] out=u_csamul_rca32_and9_7
.subckt fa a=u_csamul_rca32_and9_7 b=u_csamul_rca32_fa10_6_xor1 cin=u_csamul_rca32_fa9_6_or0 fa_xor1=u_csamul_rca32_fa9_7_xor1 fa_or0=u_csamul_rca32_fa9_7_or0
.subckt and_gate a=a[10] b=b[7] out=u_csamul_rca32_and10_7
.subckt fa a=u_csamul_rca32_and10_7 b=u_csamul_rca32_fa11_6_xor1 cin=u_csamul_rca32_fa10_6_or0 fa_xor1=u_csamul_rca32_fa10_7_xor1 fa_or0=u_csamul_rca32_fa10_7_or0
.subckt and_gate a=a[11] b=b[7] out=u_csamul_rca32_and11_7
.subckt fa a=u_csamul_rca32_and11_7 b=u_csamul_rca32_fa12_6_xor1 cin=u_csamul_rca32_fa11_6_or0 fa_xor1=u_csamul_rca32_fa11_7_xor1 fa_or0=u_csamul_rca32_fa11_7_or0
.subckt and_gate a=a[12] b=b[7] out=u_csamul_rca32_and12_7
.subckt fa a=u_csamul_rca32_and12_7 b=u_csamul_rca32_fa13_6_xor1 cin=u_csamul_rca32_fa12_6_or0 fa_xor1=u_csamul_rca32_fa12_7_xor1 fa_or0=u_csamul_rca32_fa12_7_or0
.subckt and_gate a=a[13] b=b[7] out=u_csamul_rca32_and13_7
.subckt fa a=u_csamul_rca32_and13_7 b=u_csamul_rca32_fa14_6_xor1 cin=u_csamul_rca32_fa13_6_or0 fa_xor1=u_csamul_rca32_fa13_7_xor1 fa_or0=u_csamul_rca32_fa13_7_or0
.subckt and_gate a=a[14] b=b[7] out=u_csamul_rca32_and14_7
.subckt fa a=u_csamul_rca32_and14_7 b=u_csamul_rca32_fa15_6_xor1 cin=u_csamul_rca32_fa14_6_or0 fa_xor1=u_csamul_rca32_fa14_7_xor1 fa_or0=u_csamul_rca32_fa14_7_or0
.subckt and_gate a=a[15] b=b[7] out=u_csamul_rca32_and15_7
.subckt fa a=u_csamul_rca32_and15_7 b=u_csamul_rca32_fa16_6_xor1 cin=u_csamul_rca32_fa15_6_or0 fa_xor1=u_csamul_rca32_fa15_7_xor1 fa_or0=u_csamul_rca32_fa15_7_or0
.subckt and_gate a=a[16] b=b[7] out=u_csamul_rca32_and16_7
.subckt fa a=u_csamul_rca32_and16_7 b=u_csamul_rca32_fa17_6_xor1 cin=u_csamul_rca32_fa16_6_or0 fa_xor1=u_csamul_rca32_fa16_7_xor1 fa_or0=u_csamul_rca32_fa16_7_or0
.subckt and_gate a=a[17] b=b[7] out=u_csamul_rca32_and17_7
.subckt fa a=u_csamul_rca32_and17_7 b=u_csamul_rca32_fa18_6_xor1 cin=u_csamul_rca32_fa17_6_or0 fa_xor1=u_csamul_rca32_fa17_7_xor1 fa_or0=u_csamul_rca32_fa17_7_or0
.subckt and_gate a=a[18] b=b[7] out=u_csamul_rca32_and18_7
.subckt fa a=u_csamul_rca32_and18_7 b=u_csamul_rca32_fa19_6_xor1 cin=u_csamul_rca32_fa18_6_or0 fa_xor1=u_csamul_rca32_fa18_7_xor1 fa_or0=u_csamul_rca32_fa18_7_or0
.subckt and_gate a=a[19] b=b[7] out=u_csamul_rca32_and19_7
.subckt fa a=u_csamul_rca32_and19_7 b=u_csamul_rca32_fa20_6_xor1 cin=u_csamul_rca32_fa19_6_or0 fa_xor1=u_csamul_rca32_fa19_7_xor1 fa_or0=u_csamul_rca32_fa19_7_or0
.subckt and_gate a=a[20] b=b[7] out=u_csamul_rca32_and20_7
.subckt fa a=u_csamul_rca32_and20_7 b=u_csamul_rca32_fa21_6_xor1 cin=u_csamul_rca32_fa20_6_or0 fa_xor1=u_csamul_rca32_fa20_7_xor1 fa_or0=u_csamul_rca32_fa20_7_or0
.subckt and_gate a=a[21] b=b[7] out=u_csamul_rca32_and21_7
.subckt fa a=u_csamul_rca32_and21_7 b=u_csamul_rca32_fa22_6_xor1 cin=u_csamul_rca32_fa21_6_or0 fa_xor1=u_csamul_rca32_fa21_7_xor1 fa_or0=u_csamul_rca32_fa21_7_or0
.subckt and_gate a=a[22] b=b[7] out=u_csamul_rca32_and22_7
.subckt fa a=u_csamul_rca32_and22_7 b=u_csamul_rca32_fa23_6_xor1 cin=u_csamul_rca32_fa22_6_or0 fa_xor1=u_csamul_rca32_fa22_7_xor1 fa_or0=u_csamul_rca32_fa22_7_or0
.subckt and_gate a=a[23] b=b[7] out=u_csamul_rca32_and23_7
.subckt fa a=u_csamul_rca32_and23_7 b=u_csamul_rca32_fa24_6_xor1 cin=u_csamul_rca32_fa23_6_or0 fa_xor1=u_csamul_rca32_fa23_7_xor1 fa_or0=u_csamul_rca32_fa23_7_or0
.subckt and_gate a=a[24] b=b[7] out=u_csamul_rca32_and24_7
.subckt fa a=u_csamul_rca32_and24_7 b=u_csamul_rca32_fa25_6_xor1 cin=u_csamul_rca32_fa24_6_or0 fa_xor1=u_csamul_rca32_fa24_7_xor1 fa_or0=u_csamul_rca32_fa24_7_or0
.subckt and_gate a=a[25] b=b[7] out=u_csamul_rca32_and25_7
.subckt fa a=u_csamul_rca32_and25_7 b=u_csamul_rca32_fa26_6_xor1 cin=u_csamul_rca32_fa25_6_or0 fa_xor1=u_csamul_rca32_fa25_7_xor1 fa_or0=u_csamul_rca32_fa25_7_or0
.subckt and_gate a=a[26] b=b[7] out=u_csamul_rca32_and26_7
.subckt fa a=u_csamul_rca32_and26_7 b=u_csamul_rca32_fa27_6_xor1 cin=u_csamul_rca32_fa26_6_or0 fa_xor1=u_csamul_rca32_fa26_7_xor1 fa_or0=u_csamul_rca32_fa26_7_or0
.subckt and_gate a=a[27] b=b[7] out=u_csamul_rca32_and27_7
.subckt fa a=u_csamul_rca32_and27_7 b=u_csamul_rca32_fa28_6_xor1 cin=u_csamul_rca32_fa27_6_or0 fa_xor1=u_csamul_rca32_fa27_7_xor1 fa_or0=u_csamul_rca32_fa27_7_or0
.subckt and_gate a=a[28] b=b[7] out=u_csamul_rca32_and28_7
.subckt fa a=u_csamul_rca32_and28_7 b=u_csamul_rca32_fa29_6_xor1 cin=u_csamul_rca32_fa28_6_or0 fa_xor1=u_csamul_rca32_fa28_7_xor1 fa_or0=u_csamul_rca32_fa28_7_or0
.subckt and_gate a=a[29] b=b[7] out=u_csamul_rca32_and29_7
.subckt fa a=u_csamul_rca32_and29_7 b=u_csamul_rca32_fa30_6_xor1 cin=u_csamul_rca32_fa29_6_or0 fa_xor1=u_csamul_rca32_fa29_7_xor1 fa_or0=u_csamul_rca32_fa29_7_or0
.subckt and_gate a=a[30] b=b[7] out=u_csamul_rca32_and30_7
.subckt fa a=u_csamul_rca32_and30_7 b=u_csamul_rca32_and31_6 cin=u_csamul_rca32_fa30_6_or0 fa_xor1=u_csamul_rca32_fa30_7_xor1 fa_or0=u_csamul_rca32_fa30_7_or0
.subckt and_gate a=a[31] b=b[7] out=u_csamul_rca32_and31_7
.subckt and_gate a=a[0] b=b[8] out=u_csamul_rca32_and0_8
.subckt fa a=u_csamul_rca32_and0_8 b=u_csamul_rca32_fa1_7_xor1 cin=u_csamul_rca32_fa0_7_or0 fa_xor1=u_csamul_rca32_fa0_8_xor1 fa_or0=u_csamul_rca32_fa0_8_or0
.subckt and_gate a=a[1] b=b[8] out=u_csamul_rca32_and1_8
.subckt fa a=u_csamul_rca32_and1_8 b=u_csamul_rca32_fa2_7_xor1 cin=u_csamul_rca32_fa1_7_or0 fa_xor1=u_csamul_rca32_fa1_8_xor1 fa_or0=u_csamul_rca32_fa1_8_or0
.subckt and_gate a=a[2] b=b[8] out=u_csamul_rca32_and2_8
.subckt fa a=u_csamul_rca32_and2_8 b=u_csamul_rca32_fa3_7_xor1 cin=u_csamul_rca32_fa2_7_or0 fa_xor1=u_csamul_rca32_fa2_8_xor1 fa_or0=u_csamul_rca32_fa2_8_or0
.subckt and_gate a=a[3] b=b[8] out=u_csamul_rca32_and3_8
.subckt fa a=u_csamul_rca32_and3_8 b=u_csamul_rca32_fa4_7_xor1 cin=u_csamul_rca32_fa3_7_or0 fa_xor1=u_csamul_rca32_fa3_8_xor1 fa_or0=u_csamul_rca32_fa3_8_or0
.subckt and_gate a=a[4] b=b[8] out=u_csamul_rca32_and4_8
.subckt fa a=u_csamul_rca32_and4_8 b=u_csamul_rca32_fa5_7_xor1 cin=u_csamul_rca32_fa4_7_or0 fa_xor1=u_csamul_rca32_fa4_8_xor1 fa_or0=u_csamul_rca32_fa4_8_or0
.subckt and_gate a=a[5] b=b[8] out=u_csamul_rca32_and5_8
.subckt fa a=u_csamul_rca32_and5_8 b=u_csamul_rca32_fa6_7_xor1 cin=u_csamul_rca32_fa5_7_or0 fa_xor1=u_csamul_rca32_fa5_8_xor1 fa_or0=u_csamul_rca32_fa5_8_or0
.subckt and_gate a=a[6] b=b[8] out=u_csamul_rca32_and6_8
.subckt fa a=u_csamul_rca32_and6_8 b=u_csamul_rca32_fa7_7_xor1 cin=u_csamul_rca32_fa6_7_or0 fa_xor1=u_csamul_rca32_fa6_8_xor1 fa_or0=u_csamul_rca32_fa6_8_or0
.subckt and_gate a=a[7] b=b[8] out=u_csamul_rca32_and7_8
.subckt fa a=u_csamul_rca32_and7_8 b=u_csamul_rca32_fa8_7_xor1 cin=u_csamul_rca32_fa7_7_or0 fa_xor1=u_csamul_rca32_fa7_8_xor1 fa_or0=u_csamul_rca32_fa7_8_or0
.subckt and_gate a=a[8] b=b[8] out=u_csamul_rca32_and8_8
.subckt fa a=u_csamul_rca32_and8_8 b=u_csamul_rca32_fa9_7_xor1 cin=u_csamul_rca32_fa8_7_or0 fa_xor1=u_csamul_rca32_fa8_8_xor1 fa_or0=u_csamul_rca32_fa8_8_or0
.subckt and_gate a=a[9] b=b[8] out=u_csamul_rca32_and9_8
.subckt fa a=u_csamul_rca32_and9_8 b=u_csamul_rca32_fa10_7_xor1 cin=u_csamul_rca32_fa9_7_or0 fa_xor1=u_csamul_rca32_fa9_8_xor1 fa_or0=u_csamul_rca32_fa9_8_or0
.subckt and_gate a=a[10] b=b[8] out=u_csamul_rca32_and10_8
.subckt fa a=u_csamul_rca32_and10_8 b=u_csamul_rca32_fa11_7_xor1 cin=u_csamul_rca32_fa10_7_or0 fa_xor1=u_csamul_rca32_fa10_8_xor1 fa_or0=u_csamul_rca32_fa10_8_or0
.subckt and_gate a=a[11] b=b[8] out=u_csamul_rca32_and11_8
.subckt fa a=u_csamul_rca32_and11_8 b=u_csamul_rca32_fa12_7_xor1 cin=u_csamul_rca32_fa11_7_or0 fa_xor1=u_csamul_rca32_fa11_8_xor1 fa_or0=u_csamul_rca32_fa11_8_or0
.subckt and_gate a=a[12] b=b[8] out=u_csamul_rca32_and12_8
.subckt fa a=u_csamul_rca32_and12_8 b=u_csamul_rca32_fa13_7_xor1 cin=u_csamul_rca32_fa12_7_or0 fa_xor1=u_csamul_rca32_fa12_8_xor1 fa_or0=u_csamul_rca32_fa12_8_or0
.subckt and_gate a=a[13] b=b[8] out=u_csamul_rca32_and13_8
.subckt fa a=u_csamul_rca32_and13_8 b=u_csamul_rca32_fa14_7_xor1 cin=u_csamul_rca32_fa13_7_or0 fa_xor1=u_csamul_rca32_fa13_8_xor1 fa_or0=u_csamul_rca32_fa13_8_or0
.subckt and_gate a=a[14] b=b[8] out=u_csamul_rca32_and14_8
.subckt fa a=u_csamul_rca32_and14_8 b=u_csamul_rca32_fa15_7_xor1 cin=u_csamul_rca32_fa14_7_or0 fa_xor1=u_csamul_rca32_fa14_8_xor1 fa_or0=u_csamul_rca32_fa14_8_or0
.subckt and_gate a=a[15] b=b[8] out=u_csamul_rca32_and15_8
.subckt fa a=u_csamul_rca32_and15_8 b=u_csamul_rca32_fa16_7_xor1 cin=u_csamul_rca32_fa15_7_or0 fa_xor1=u_csamul_rca32_fa15_8_xor1 fa_or0=u_csamul_rca32_fa15_8_or0
.subckt and_gate a=a[16] b=b[8] out=u_csamul_rca32_and16_8
.subckt fa a=u_csamul_rca32_and16_8 b=u_csamul_rca32_fa17_7_xor1 cin=u_csamul_rca32_fa16_7_or0 fa_xor1=u_csamul_rca32_fa16_8_xor1 fa_or0=u_csamul_rca32_fa16_8_or0
.subckt and_gate a=a[17] b=b[8] out=u_csamul_rca32_and17_8
.subckt fa a=u_csamul_rca32_and17_8 b=u_csamul_rca32_fa18_7_xor1 cin=u_csamul_rca32_fa17_7_or0 fa_xor1=u_csamul_rca32_fa17_8_xor1 fa_or0=u_csamul_rca32_fa17_8_or0
.subckt and_gate a=a[18] b=b[8] out=u_csamul_rca32_and18_8
.subckt fa a=u_csamul_rca32_and18_8 b=u_csamul_rca32_fa19_7_xor1 cin=u_csamul_rca32_fa18_7_or0 fa_xor1=u_csamul_rca32_fa18_8_xor1 fa_or0=u_csamul_rca32_fa18_8_or0
.subckt and_gate a=a[19] b=b[8] out=u_csamul_rca32_and19_8
.subckt fa a=u_csamul_rca32_and19_8 b=u_csamul_rca32_fa20_7_xor1 cin=u_csamul_rca32_fa19_7_or0 fa_xor1=u_csamul_rca32_fa19_8_xor1 fa_or0=u_csamul_rca32_fa19_8_or0
.subckt and_gate a=a[20] b=b[8] out=u_csamul_rca32_and20_8
.subckt fa a=u_csamul_rca32_and20_8 b=u_csamul_rca32_fa21_7_xor1 cin=u_csamul_rca32_fa20_7_or0 fa_xor1=u_csamul_rca32_fa20_8_xor1 fa_or0=u_csamul_rca32_fa20_8_or0
.subckt and_gate a=a[21] b=b[8] out=u_csamul_rca32_and21_8
.subckt fa a=u_csamul_rca32_and21_8 b=u_csamul_rca32_fa22_7_xor1 cin=u_csamul_rca32_fa21_7_or0 fa_xor1=u_csamul_rca32_fa21_8_xor1 fa_or0=u_csamul_rca32_fa21_8_or0
.subckt and_gate a=a[22] b=b[8] out=u_csamul_rca32_and22_8
.subckt fa a=u_csamul_rca32_and22_8 b=u_csamul_rca32_fa23_7_xor1 cin=u_csamul_rca32_fa22_7_or0 fa_xor1=u_csamul_rca32_fa22_8_xor1 fa_or0=u_csamul_rca32_fa22_8_or0
.subckt and_gate a=a[23] b=b[8] out=u_csamul_rca32_and23_8
.subckt fa a=u_csamul_rca32_and23_8 b=u_csamul_rca32_fa24_7_xor1 cin=u_csamul_rca32_fa23_7_or0 fa_xor1=u_csamul_rca32_fa23_8_xor1 fa_or0=u_csamul_rca32_fa23_8_or0
.subckt and_gate a=a[24] b=b[8] out=u_csamul_rca32_and24_8
.subckt fa a=u_csamul_rca32_and24_8 b=u_csamul_rca32_fa25_7_xor1 cin=u_csamul_rca32_fa24_7_or0 fa_xor1=u_csamul_rca32_fa24_8_xor1 fa_or0=u_csamul_rca32_fa24_8_or0
.subckt and_gate a=a[25] b=b[8] out=u_csamul_rca32_and25_8
.subckt fa a=u_csamul_rca32_and25_8 b=u_csamul_rca32_fa26_7_xor1 cin=u_csamul_rca32_fa25_7_or0 fa_xor1=u_csamul_rca32_fa25_8_xor1 fa_or0=u_csamul_rca32_fa25_8_or0
.subckt and_gate a=a[26] b=b[8] out=u_csamul_rca32_and26_8
.subckt fa a=u_csamul_rca32_and26_8 b=u_csamul_rca32_fa27_7_xor1 cin=u_csamul_rca32_fa26_7_or0 fa_xor1=u_csamul_rca32_fa26_8_xor1 fa_or0=u_csamul_rca32_fa26_8_or0
.subckt and_gate a=a[27] b=b[8] out=u_csamul_rca32_and27_8
.subckt fa a=u_csamul_rca32_and27_8 b=u_csamul_rca32_fa28_7_xor1 cin=u_csamul_rca32_fa27_7_or0 fa_xor1=u_csamul_rca32_fa27_8_xor1 fa_or0=u_csamul_rca32_fa27_8_or0
.subckt and_gate a=a[28] b=b[8] out=u_csamul_rca32_and28_8
.subckt fa a=u_csamul_rca32_and28_8 b=u_csamul_rca32_fa29_7_xor1 cin=u_csamul_rca32_fa28_7_or0 fa_xor1=u_csamul_rca32_fa28_8_xor1 fa_or0=u_csamul_rca32_fa28_8_or0
.subckt and_gate a=a[29] b=b[8] out=u_csamul_rca32_and29_8
.subckt fa a=u_csamul_rca32_and29_8 b=u_csamul_rca32_fa30_7_xor1 cin=u_csamul_rca32_fa29_7_or0 fa_xor1=u_csamul_rca32_fa29_8_xor1 fa_or0=u_csamul_rca32_fa29_8_or0
.subckt and_gate a=a[30] b=b[8] out=u_csamul_rca32_and30_8
.subckt fa a=u_csamul_rca32_and30_8 b=u_csamul_rca32_and31_7 cin=u_csamul_rca32_fa30_7_or0 fa_xor1=u_csamul_rca32_fa30_8_xor1 fa_or0=u_csamul_rca32_fa30_8_or0
.subckt and_gate a=a[31] b=b[8] out=u_csamul_rca32_and31_8
.subckt and_gate a=a[0] b=b[9] out=u_csamul_rca32_and0_9
.subckt fa a=u_csamul_rca32_and0_9 b=u_csamul_rca32_fa1_8_xor1 cin=u_csamul_rca32_fa0_8_or0 fa_xor1=u_csamul_rca32_fa0_9_xor1 fa_or0=u_csamul_rca32_fa0_9_or0
.subckt and_gate a=a[1] b=b[9] out=u_csamul_rca32_and1_9
.subckt fa a=u_csamul_rca32_and1_9 b=u_csamul_rca32_fa2_8_xor1 cin=u_csamul_rca32_fa1_8_or0 fa_xor1=u_csamul_rca32_fa1_9_xor1 fa_or0=u_csamul_rca32_fa1_9_or0
.subckt and_gate a=a[2] b=b[9] out=u_csamul_rca32_and2_9
.subckt fa a=u_csamul_rca32_and2_9 b=u_csamul_rca32_fa3_8_xor1 cin=u_csamul_rca32_fa2_8_or0 fa_xor1=u_csamul_rca32_fa2_9_xor1 fa_or0=u_csamul_rca32_fa2_9_or0
.subckt and_gate a=a[3] b=b[9] out=u_csamul_rca32_and3_9
.subckt fa a=u_csamul_rca32_and3_9 b=u_csamul_rca32_fa4_8_xor1 cin=u_csamul_rca32_fa3_8_or0 fa_xor1=u_csamul_rca32_fa3_9_xor1 fa_or0=u_csamul_rca32_fa3_9_or0
.subckt and_gate a=a[4] b=b[9] out=u_csamul_rca32_and4_9
.subckt fa a=u_csamul_rca32_and4_9 b=u_csamul_rca32_fa5_8_xor1 cin=u_csamul_rca32_fa4_8_or0 fa_xor1=u_csamul_rca32_fa4_9_xor1 fa_or0=u_csamul_rca32_fa4_9_or0
.subckt and_gate a=a[5] b=b[9] out=u_csamul_rca32_and5_9
.subckt fa a=u_csamul_rca32_and5_9 b=u_csamul_rca32_fa6_8_xor1 cin=u_csamul_rca32_fa5_8_or0 fa_xor1=u_csamul_rca32_fa5_9_xor1 fa_or0=u_csamul_rca32_fa5_9_or0
.subckt and_gate a=a[6] b=b[9] out=u_csamul_rca32_and6_9
.subckt fa a=u_csamul_rca32_and6_9 b=u_csamul_rca32_fa7_8_xor1 cin=u_csamul_rca32_fa6_8_or0 fa_xor1=u_csamul_rca32_fa6_9_xor1 fa_or0=u_csamul_rca32_fa6_9_or0
.subckt and_gate a=a[7] b=b[9] out=u_csamul_rca32_and7_9
.subckt fa a=u_csamul_rca32_and7_9 b=u_csamul_rca32_fa8_8_xor1 cin=u_csamul_rca32_fa7_8_or0 fa_xor1=u_csamul_rca32_fa7_9_xor1 fa_or0=u_csamul_rca32_fa7_9_or0
.subckt and_gate a=a[8] b=b[9] out=u_csamul_rca32_and8_9
.subckt fa a=u_csamul_rca32_and8_9 b=u_csamul_rca32_fa9_8_xor1 cin=u_csamul_rca32_fa8_8_or0 fa_xor1=u_csamul_rca32_fa8_9_xor1 fa_or0=u_csamul_rca32_fa8_9_or0
.subckt and_gate a=a[9] b=b[9] out=u_csamul_rca32_and9_9
.subckt fa a=u_csamul_rca32_and9_9 b=u_csamul_rca32_fa10_8_xor1 cin=u_csamul_rca32_fa9_8_or0 fa_xor1=u_csamul_rca32_fa9_9_xor1 fa_or0=u_csamul_rca32_fa9_9_or0
.subckt and_gate a=a[10] b=b[9] out=u_csamul_rca32_and10_9
.subckt fa a=u_csamul_rca32_and10_9 b=u_csamul_rca32_fa11_8_xor1 cin=u_csamul_rca32_fa10_8_or0 fa_xor1=u_csamul_rca32_fa10_9_xor1 fa_or0=u_csamul_rca32_fa10_9_or0
.subckt and_gate a=a[11] b=b[9] out=u_csamul_rca32_and11_9
.subckt fa a=u_csamul_rca32_and11_9 b=u_csamul_rca32_fa12_8_xor1 cin=u_csamul_rca32_fa11_8_or0 fa_xor1=u_csamul_rca32_fa11_9_xor1 fa_or0=u_csamul_rca32_fa11_9_or0
.subckt and_gate a=a[12] b=b[9] out=u_csamul_rca32_and12_9
.subckt fa a=u_csamul_rca32_and12_9 b=u_csamul_rca32_fa13_8_xor1 cin=u_csamul_rca32_fa12_8_or0 fa_xor1=u_csamul_rca32_fa12_9_xor1 fa_or0=u_csamul_rca32_fa12_9_or0
.subckt and_gate a=a[13] b=b[9] out=u_csamul_rca32_and13_9
.subckt fa a=u_csamul_rca32_and13_9 b=u_csamul_rca32_fa14_8_xor1 cin=u_csamul_rca32_fa13_8_or0 fa_xor1=u_csamul_rca32_fa13_9_xor1 fa_or0=u_csamul_rca32_fa13_9_or0
.subckt and_gate a=a[14] b=b[9] out=u_csamul_rca32_and14_9
.subckt fa a=u_csamul_rca32_and14_9 b=u_csamul_rca32_fa15_8_xor1 cin=u_csamul_rca32_fa14_8_or0 fa_xor1=u_csamul_rca32_fa14_9_xor1 fa_or0=u_csamul_rca32_fa14_9_or0
.subckt and_gate a=a[15] b=b[9] out=u_csamul_rca32_and15_9
.subckt fa a=u_csamul_rca32_and15_9 b=u_csamul_rca32_fa16_8_xor1 cin=u_csamul_rca32_fa15_8_or0 fa_xor1=u_csamul_rca32_fa15_9_xor1 fa_or0=u_csamul_rca32_fa15_9_or0
.subckt and_gate a=a[16] b=b[9] out=u_csamul_rca32_and16_9
.subckt fa a=u_csamul_rca32_and16_9 b=u_csamul_rca32_fa17_8_xor1 cin=u_csamul_rca32_fa16_8_or0 fa_xor1=u_csamul_rca32_fa16_9_xor1 fa_or0=u_csamul_rca32_fa16_9_or0
.subckt and_gate a=a[17] b=b[9] out=u_csamul_rca32_and17_9
.subckt fa a=u_csamul_rca32_and17_9 b=u_csamul_rca32_fa18_8_xor1 cin=u_csamul_rca32_fa17_8_or0 fa_xor1=u_csamul_rca32_fa17_9_xor1 fa_or0=u_csamul_rca32_fa17_9_or0
.subckt and_gate a=a[18] b=b[9] out=u_csamul_rca32_and18_9
.subckt fa a=u_csamul_rca32_and18_9 b=u_csamul_rca32_fa19_8_xor1 cin=u_csamul_rca32_fa18_8_or0 fa_xor1=u_csamul_rca32_fa18_9_xor1 fa_or0=u_csamul_rca32_fa18_9_or0
.subckt and_gate a=a[19] b=b[9] out=u_csamul_rca32_and19_9
.subckt fa a=u_csamul_rca32_and19_9 b=u_csamul_rca32_fa20_8_xor1 cin=u_csamul_rca32_fa19_8_or0 fa_xor1=u_csamul_rca32_fa19_9_xor1 fa_or0=u_csamul_rca32_fa19_9_or0
.subckt and_gate a=a[20] b=b[9] out=u_csamul_rca32_and20_9
.subckt fa a=u_csamul_rca32_and20_9 b=u_csamul_rca32_fa21_8_xor1 cin=u_csamul_rca32_fa20_8_or0 fa_xor1=u_csamul_rca32_fa20_9_xor1 fa_or0=u_csamul_rca32_fa20_9_or0
.subckt and_gate a=a[21] b=b[9] out=u_csamul_rca32_and21_9
.subckt fa a=u_csamul_rca32_and21_9 b=u_csamul_rca32_fa22_8_xor1 cin=u_csamul_rca32_fa21_8_or0 fa_xor1=u_csamul_rca32_fa21_9_xor1 fa_or0=u_csamul_rca32_fa21_9_or0
.subckt and_gate a=a[22] b=b[9] out=u_csamul_rca32_and22_9
.subckt fa a=u_csamul_rca32_and22_9 b=u_csamul_rca32_fa23_8_xor1 cin=u_csamul_rca32_fa22_8_or0 fa_xor1=u_csamul_rca32_fa22_9_xor1 fa_or0=u_csamul_rca32_fa22_9_or0
.subckt and_gate a=a[23] b=b[9] out=u_csamul_rca32_and23_9
.subckt fa a=u_csamul_rca32_and23_9 b=u_csamul_rca32_fa24_8_xor1 cin=u_csamul_rca32_fa23_8_or0 fa_xor1=u_csamul_rca32_fa23_9_xor1 fa_or0=u_csamul_rca32_fa23_9_or0
.subckt and_gate a=a[24] b=b[9] out=u_csamul_rca32_and24_9
.subckt fa a=u_csamul_rca32_and24_9 b=u_csamul_rca32_fa25_8_xor1 cin=u_csamul_rca32_fa24_8_or0 fa_xor1=u_csamul_rca32_fa24_9_xor1 fa_or0=u_csamul_rca32_fa24_9_or0
.subckt and_gate a=a[25] b=b[9] out=u_csamul_rca32_and25_9
.subckt fa a=u_csamul_rca32_and25_9 b=u_csamul_rca32_fa26_8_xor1 cin=u_csamul_rca32_fa25_8_or0 fa_xor1=u_csamul_rca32_fa25_9_xor1 fa_or0=u_csamul_rca32_fa25_9_or0
.subckt and_gate a=a[26] b=b[9] out=u_csamul_rca32_and26_9
.subckt fa a=u_csamul_rca32_and26_9 b=u_csamul_rca32_fa27_8_xor1 cin=u_csamul_rca32_fa26_8_or0 fa_xor1=u_csamul_rca32_fa26_9_xor1 fa_or0=u_csamul_rca32_fa26_9_or0
.subckt and_gate a=a[27] b=b[9] out=u_csamul_rca32_and27_9
.subckt fa a=u_csamul_rca32_and27_9 b=u_csamul_rca32_fa28_8_xor1 cin=u_csamul_rca32_fa27_8_or0 fa_xor1=u_csamul_rca32_fa27_9_xor1 fa_or0=u_csamul_rca32_fa27_9_or0
.subckt and_gate a=a[28] b=b[9] out=u_csamul_rca32_and28_9
.subckt fa a=u_csamul_rca32_and28_9 b=u_csamul_rca32_fa29_8_xor1 cin=u_csamul_rca32_fa28_8_or0 fa_xor1=u_csamul_rca32_fa28_9_xor1 fa_or0=u_csamul_rca32_fa28_9_or0
.subckt and_gate a=a[29] b=b[9] out=u_csamul_rca32_and29_9
.subckt fa a=u_csamul_rca32_and29_9 b=u_csamul_rca32_fa30_8_xor1 cin=u_csamul_rca32_fa29_8_or0 fa_xor1=u_csamul_rca32_fa29_9_xor1 fa_or0=u_csamul_rca32_fa29_9_or0
.subckt and_gate a=a[30] b=b[9] out=u_csamul_rca32_and30_9
.subckt fa a=u_csamul_rca32_and30_9 b=u_csamul_rca32_and31_8 cin=u_csamul_rca32_fa30_8_or0 fa_xor1=u_csamul_rca32_fa30_9_xor1 fa_or0=u_csamul_rca32_fa30_9_or0
.subckt and_gate a=a[31] b=b[9] out=u_csamul_rca32_and31_9
.subckt and_gate a=a[0] b=b[10] out=u_csamul_rca32_and0_10
.subckt fa a=u_csamul_rca32_and0_10 b=u_csamul_rca32_fa1_9_xor1 cin=u_csamul_rca32_fa0_9_or0 fa_xor1=u_csamul_rca32_fa0_10_xor1 fa_or0=u_csamul_rca32_fa0_10_or0
.subckt and_gate a=a[1] b=b[10] out=u_csamul_rca32_and1_10
.subckt fa a=u_csamul_rca32_and1_10 b=u_csamul_rca32_fa2_9_xor1 cin=u_csamul_rca32_fa1_9_or0 fa_xor1=u_csamul_rca32_fa1_10_xor1 fa_or0=u_csamul_rca32_fa1_10_or0
.subckt and_gate a=a[2] b=b[10] out=u_csamul_rca32_and2_10
.subckt fa a=u_csamul_rca32_and2_10 b=u_csamul_rca32_fa3_9_xor1 cin=u_csamul_rca32_fa2_9_or0 fa_xor1=u_csamul_rca32_fa2_10_xor1 fa_or0=u_csamul_rca32_fa2_10_or0
.subckt and_gate a=a[3] b=b[10] out=u_csamul_rca32_and3_10
.subckt fa a=u_csamul_rca32_and3_10 b=u_csamul_rca32_fa4_9_xor1 cin=u_csamul_rca32_fa3_9_or0 fa_xor1=u_csamul_rca32_fa3_10_xor1 fa_or0=u_csamul_rca32_fa3_10_or0
.subckt and_gate a=a[4] b=b[10] out=u_csamul_rca32_and4_10
.subckt fa a=u_csamul_rca32_and4_10 b=u_csamul_rca32_fa5_9_xor1 cin=u_csamul_rca32_fa4_9_or0 fa_xor1=u_csamul_rca32_fa4_10_xor1 fa_or0=u_csamul_rca32_fa4_10_or0
.subckt and_gate a=a[5] b=b[10] out=u_csamul_rca32_and5_10
.subckt fa a=u_csamul_rca32_and5_10 b=u_csamul_rca32_fa6_9_xor1 cin=u_csamul_rca32_fa5_9_or0 fa_xor1=u_csamul_rca32_fa5_10_xor1 fa_or0=u_csamul_rca32_fa5_10_or0
.subckt and_gate a=a[6] b=b[10] out=u_csamul_rca32_and6_10
.subckt fa a=u_csamul_rca32_and6_10 b=u_csamul_rca32_fa7_9_xor1 cin=u_csamul_rca32_fa6_9_or0 fa_xor1=u_csamul_rca32_fa6_10_xor1 fa_or0=u_csamul_rca32_fa6_10_or0
.subckt and_gate a=a[7] b=b[10] out=u_csamul_rca32_and7_10
.subckt fa a=u_csamul_rca32_and7_10 b=u_csamul_rca32_fa8_9_xor1 cin=u_csamul_rca32_fa7_9_or0 fa_xor1=u_csamul_rca32_fa7_10_xor1 fa_or0=u_csamul_rca32_fa7_10_or0
.subckt and_gate a=a[8] b=b[10] out=u_csamul_rca32_and8_10
.subckt fa a=u_csamul_rca32_and8_10 b=u_csamul_rca32_fa9_9_xor1 cin=u_csamul_rca32_fa8_9_or0 fa_xor1=u_csamul_rca32_fa8_10_xor1 fa_or0=u_csamul_rca32_fa8_10_or0
.subckt and_gate a=a[9] b=b[10] out=u_csamul_rca32_and9_10
.subckt fa a=u_csamul_rca32_and9_10 b=u_csamul_rca32_fa10_9_xor1 cin=u_csamul_rca32_fa9_9_or0 fa_xor1=u_csamul_rca32_fa9_10_xor1 fa_or0=u_csamul_rca32_fa9_10_or0
.subckt and_gate a=a[10] b=b[10] out=u_csamul_rca32_and10_10
.subckt fa a=u_csamul_rca32_and10_10 b=u_csamul_rca32_fa11_9_xor1 cin=u_csamul_rca32_fa10_9_or0 fa_xor1=u_csamul_rca32_fa10_10_xor1 fa_or0=u_csamul_rca32_fa10_10_or0
.subckt and_gate a=a[11] b=b[10] out=u_csamul_rca32_and11_10
.subckt fa a=u_csamul_rca32_and11_10 b=u_csamul_rca32_fa12_9_xor1 cin=u_csamul_rca32_fa11_9_or0 fa_xor1=u_csamul_rca32_fa11_10_xor1 fa_or0=u_csamul_rca32_fa11_10_or0
.subckt and_gate a=a[12] b=b[10] out=u_csamul_rca32_and12_10
.subckt fa a=u_csamul_rca32_and12_10 b=u_csamul_rca32_fa13_9_xor1 cin=u_csamul_rca32_fa12_9_or0 fa_xor1=u_csamul_rca32_fa12_10_xor1 fa_or0=u_csamul_rca32_fa12_10_or0
.subckt and_gate a=a[13] b=b[10] out=u_csamul_rca32_and13_10
.subckt fa a=u_csamul_rca32_and13_10 b=u_csamul_rca32_fa14_9_xor1 cin=u_csamul_rca32_fa13_9_or0 fa_xor1=u_csamul_rca32_fa13_10_xor1 fa_or0=u_csamul_rca32_fa13_10_or0
.subckt and_gate a=a[14] b=b[10] out=u_csamul_rca32_and14_10
.subckt fa a=u_csamul_rca32_and14_10 b=u_csamul_rca32_fa15_9_xor1 cin=u_csamul_rca32_fa14_9_or0 fa_xor1=u_csamul_rca32_fa14_10_xor1 fa_or0=u_csamul_rca32_fa14_10_or0
.subckt and_gate a=a[15] b=b[10] out=u_csamul_rca32_and15_10
.subckt fa a=u_csamul_rca32_and15_10 b=u_csamul_rca32_fa16_9_xor1 cin=u_csamul_rca32_fa15_9_or0 fa_xor1=u_csamul_rca32_fa15_10_xor1 fa_or0=u_csamul_rca32_fa15_10_or0
.subckt and_gate a=a[16] b=b[10] out=u_csamul_rca32_and16_10
.subckt fa a=u_csamul_rca32_and16_10 b=u_csamul_rca32_fa17_9_xor1 cin=u_csamul_rca32_fa16_9_or0 fa_xor1=u_csamul_rca32_fa16_10_xor1 fa_or0=u_csamul_rca32_fa16_10_or0
.subckt and_gate a=a[17] b=b[10] out=u_csamul_rca32_and17_10
.subckt fa a=u_csamul_rca32_and17_10 b=u_csamul_rca32_fa18_9_xor1 cin=u_csamul_rca32_fa17_9_or0 fa_xor1=u_csamul_rca32_fa17_10_xor1 fa_or0=u_csamul_rca32_fa17_10_or0
.subckt and_gate a=a[18] b=b[10] out=u_csamul_rca32_and18_10
.subckt fa a=u_csamul_rca32_and18_10 b=u_csamul_rca32_fa19_9_xor1 cin=u_csamul_rca32_fa18_9_or0 fa_xor1=u_csamul_rca32_fa18_10_xor1 fa_or0=u_csamul_rca32_fa18_10_or0
.subckt and_gate a=a[19] b=b[10] out=u_csamul_rca32_and19_10
.subckt fa a=u_csamul_rca32_and19_10 b=u_csamul_rca32_fa20_9_xor1 cin=u_csamul_rca32_fa19_9_or0 fa_xor1=u_csamul_rca32_fa19_10_xor1 fa_or0=u_csamul_rca32_fa19_10_or0
.subckt and_gate a=a[20] b=b[10] out=u_csamul_rca32_and20_10
.subckt fa a=u_csamul_rca32_and20_10 b=u_csamul_rca32_fa21_9_xor1 cin=u_csamul_rca32_fa20_9_or0 fa_xor1=u_csamul_rca32_fa20_10_xor1 fa_or0=u_csamul_rca32_fa20_10_or0
.subckt and_gate a=a[21] b=b[10] out=u_csamul_rca32_and21_10
.subckt fa a=u_csamul_rca32_and21_10 b=u_csamul_rca32_fa22_9_xor1 cin=u_csamul_rca32_fa21_9_or0 fa_xor1=u_csamul_rca32_fa21_10_xor1 fa_or0=u_csamul_rca32_fa21_10_or0
.subckt and_gate a=a[22] b=b[10] out=u_csamul_rca32_and22_10
.subckt fa a=u_csamul_rca32_and22_10 b=u_csamul_rca32_fa23_9_xor1 cin=u_csamul_rca32_fa22_9_or0 fa_xor1=u_csamul_rca32_fa22_10_xor1 fa_or0=u_csamul_rca32_fa22_10_or0
.subckt and_gate a=a[23] b=b[10] out=u_csamul_rca32_and23_10
.subckt fa a=u_csamul_rca32_and23_10 b=u_csamul_rca32_fa24_9_xor1 cin=u_csamul_rca32_fa23_9_or0 fa_xor1=u_csamul_rca32_fa23_10_xor1 fa_or0=u_csamul_rca32_fa23_10_or0
.subckt and_gate a=a[24] b=b[10] out=u_csamul_rca32_and24_10
.subckt fa a=u_csamul_rca32_and24_10 b=u_csamul_rca32_fa25_9_xor1 cin=u_csamul_rca32_fa24_9_or0 fa_xor1=u_csamul_rca32_fa24_10_xor1 fa_or0=u_csamul_rca32_fa24_10_or0
.subckt and_gate a=a[25] b=b[10] out=u_csamul_rca32_and25_10
.subckt fa a=u_csamul_rca32_and25_10 b=u_csamul_rca32_fa26_9_xor1 cin=u_csamul_rca32_fa25_9_or0 fa_xor1=u_csamul_rca32_fa25_10_xor1 fa_or0=u_csamul_rca32_fa25_10_or0
.subckt and_gate a=a[26] b=b[10] out=u_csamul_rca32_and26_10
.subckt fa a=u_csamul_rca32_and26_10 b=u_csamul_rca32_fa27_9_xor1 cin=u_csamul_rca32_fa26_9_or0 fa_xor1=u_csamul_rca32_fa26_10_xor1 fa_or0=u_csamul_rca32_fa26_10_or0
.subckt and_gate a=a[27] b=b[10] out=u_csamul_rca32_and27_10
.subckt fa a=u_csamul_rca32_and27_10 b=u_csamul_rca32_fa28_9_xor1 cin=u_csamul_rca32_fa27_9_or0 fa_xor1=u_csamul_rca32_fa27_10_xor1 fa_or0=u_csamul_rca32_fa27_10_or0
.subckt and_gate a=a[28] b=b[10] out=u_csamul_rca32_and28_10
.subckt fa a=u_csamul_rca32_and28_10 b=u_csamul_rca32_fa29_9_xor1 cin=u_csamul_rca32_fa28_9_or0 fa_xor1=u_csamul_rca32_fa28_10_xor1 fa_or0=u_csamul_rca32_fa28_10_or0
.subckt and_gate a=a[29] b=b[10] out=u_csamul_rca32_and29_10
.subckt fa a=u_csamul_rca32_and29_10 b=u_csamul_rca32_fa30_9_xor1 cin=u_csamul_rca32_fa29_9_or0 fa_xor1=u_csamul_rca32_fa29_10_xor1 fa_or0=u_csamul_rca32_fa29_10_or0
.subckt and_gate a=a[30] b=b[10] out=u_csamul_rca32_and30_10
.subckt fa a=u_csamul_rca32_and30_10 b=u_csamul_rca32_and31_9 cin=u_csamul_rca32_fa30_9_or0 fa_xor1=u_csamul_rca32_fa30_10_xor1 fa_or0=u_csamul_rca32_fa30_10_or0
.subckt and_gate a=a[31] b=b[10] out=u_csamul_rca32_and31_10
.subckt and_gate a=a[0] b=b[11] out=u_csamul_rca32_and0_11
.subckt fa a=u_csamul_rca32_and0_11 b=u_csamul_rca32_fa1_10_xor1 cin=u_csamul_rca32_fa0_10_or0 fa_xor1=u_csamul_rca32_fa0_11_xor1 fa_or0=u_csamul_rca32_fa0_11_or0
.subckt and_gate a=a[1] b=b[11] out=u_csamul_rca32_and1_11
.subckt fa a=u_csamul_rca32_and1_11 b=u_csamul_rca32_fa2_10_xor1 cin=u_csamul_rca32_fa1_10_or0 fa_xor1=u_csamul_rca32_fa1_11_xor1 fa_or0=u_csamul_rca32_fa1_11_or0
.subckt and_gate a=a[2] b=b[11] out=u_csamul_rca32_and2_11
.subckt fa a=u_csamul_rca32_and2_11 b=u_csamul_rca32_fa3_10_xor1 cin=u_csamul_rca32_fa2_10_or0 fa_xor1=u_csamul_rca32_fa2_11_xor1 fa_or0=u_csamul_rca32_fa2_11_or0
.subckt and_gate a=a[3] b=b[11] out=u_csamul_rca32_and3_11
.subckt fa a=u_csamul_rca32_and3_11 b=u_csamul_rca32_fa4_10_xor1 cin=u_csamul_rca32_fa3_10_or0 fa_xor1=u_csamul_rca32_fa3_11_xor1 fa_or0=u_csamul_rca32_fa3_11_or0
.subckt and_gate a=a[4] b=b[11] out=u_csamul_rca32_and4_11
.subckt fa a=u_csamul_rca32_and4_11 b=u_csamul_rca32_fa5_10_xor1 cin=u_csamul_rca32_fa4_10_or0 fa_xor1=u_csamul_rca32_fa4_11_xor1 fa_or0=u_csamul_rca32_fa4_11_or0
.subckt and_gate a=a[5] b=b[11] out=u_csamul_rca32_and5_11
.subckt fa a=u_csamul_rca32_and5_11 b=u_csamul_rca32_fa6_10_xor1 cin=u_csamul_rca32_fa5_10_or0 fa_xor1=u_csamul_rca32_fa5_11_xor1 fa_or0=u_csamul_rca32_fa5_11_or0
.subckt and_gate a=a[6] b=b[11] out=u_csamul_rca32_and6_11
.subckt fa a=u_csamul_rca32_and6_11 b=u_csamul_rca32_fa7_10_xor1 cin=u_csamul_rca32_fa6_10_or0 fa_xor1=u_csamul_rca32_fa6_11_xor1 fa_or0=u_csamul_rca32_fa6_11_or0
.subckt and_gate a=a[7] b=b[11] out=u_csamul_rca32_and7_11
.subckt fa a=u_csamul_rca32_and7_11 b=u_csamul_rca32_fa8_10_xor1 cin=u_csamul_rca32_fa7_10_or0 fa_xor1=u_csamul_rca32_fa7_11_xor1 fa_or0=u_csamul_rca32_fa7_11_or0
.subckt and_gate a=a[8] b=b[11] out=u_csamul_rca32_and8_11
.subckt fa a=u_csamul_rca32_and8_11 b=u_csamul_rca32_fa9_10_xor1 cin=u_csamul_rca32_fa8_10_or0 fa_xor1=u_csamul_rca32_fa8_11_xor1 fa_or0=u_csamul_rca32_fa8_11_or0
.subckt and_gate a=a[9] b=b[11] out=u_csamul_rca32_and9_11
.subckt fa a=u_csamul_rca32_and9_11 b=u_csamul_rca32_fa10_10_xor1 cin=u_csamul_rca32_fa9_10_or0 fa_xor1=u_csamul_rca32_fa9_11_xor1 fa_or0=u_csamul_rca32_fa9_11_or0
.subckt and_gate a=a[10] b=b[11] out=u_csamul_rca32_and10_11
.subckt fa a=u_csamul_rca32_and10_11 b=u_csamul_rca32_fa11_10_xor1 cin=u_csamul_rca32_fa10_10_or0 fa_xor1=u_csamul_rca32_fa10_11_xor1 fa_or0=u_csamul_rca32_fa10_11_or0
.subckt and_gate a=a[11] b=b[11] out=u_csamul_rca32_and11_11
.subckt fa a=u_csamul_rca32_and11_11 b=u_csamul_rca32_fa12_10_xor1 cin=u_csamul_rca32_fa11_10_or0 fa_xor1=u_csamul_rca32_fa11_11_xor1 fa_or0=u_csamul_rca32_fa11_11_or0
.subckt and_gate a=a[12] b=b[11] out=u_csamul_rca32_and12_11
.subckt fa a=u_csamul_rca32_and12_11 b=u_csamul_rca32_fa13_10_xor1 cin=u_csamul_rca32_fa12_10_or0 fa_xor1=u_csamul_rca32_fa12_11_xor1 fa_or0=u_csamul_rca32_fa12_11_or0
.subckt and_gate a=a[13] b=b[11] out=u_csamul_rca32_and13_11
.subckt fa a=u_csamul_rca32_and13_11 b=u_csamul_rca32_fa14_10_xor1 cin=u_csamul_rca32_fa13_10_or0 fa_xor1=u_csamul_rca32_fa13_11_xor1 fa_or0=u_csamul_rca32_fa13_11_or0
.subckt and_gate a=a[14] b=b[11] out=u_csamul_rca32_and14_11
.subckt fa a=u_csamul_rca32_and14_11 b=u_csamul_rca32_fa15_10_xor1 cin=u_csamul_rca32_fa14_10_or0 fa_xor1=u_csamul_rca32_fa14_11_xor1 fa_or0=u_csamul_rca32_fa14_11_or0
.subckt and_gate a=a[15] b=b[11] out=u_csamul_rca32_and15_11
.subckt fa a=u_csamul_rca32_and15_11 b=u_csamul_rca32_fa16_10_xor1 cin=u_csamul_rca32_fa15_10_or0 fa_xor1=u_csamul_rca32_fa15_11_xor1 fa_or0=u_csamul_rca32_fa15_11_or0
.subckt and_gate a=a[16] b=b[11] out=u_csamul_rca32_and16_11
.subckt fa a=u_csamul_rca32_and16_11 b=u_csamul_rca32_fa17_10_xor1 cin=u_csamul_rca32_fa16_10_or0 fa_xor1=u_csamul_rca32_fa16_11_xor1 fa_or0=u_csamul_rca32_fa16_11_or0
.subckt and_gate a=a[17] b=b[11] out=u_csamul_rca32_and17_11
.subckt fa a=u_csamul_rca32_and17_11 b=u_csamul_rca32_fa18_10_xor1 cin=u_csamul_rca32_fa17_10_or0 fa_xor1=u_csamul_rca32_fa17_11_xor1 fa_or0=u_csamul_rca32_fa17_11_or0
.subckt and_gate a=a[18] b=b[11] out=u_csamul_rca32_and18_11
.subckt fa a=u_csamul_rca32_and18_11 b=u_csamul_rca32_fa19_10_xor1 cin=u_csamul_rca32_fa18_10_or0 fa_xor1=u_csamul_rca32_fa18_11_xor1 fa_or0=u_csamul_rca32_fa18_11_or0
.subckt and_gate a=a[19] b=b[11] out=u_csamul_rca32_and19_11
.subckt fa a=u_csamul_rca32_and19_11 b=u_csamul_rca32_fa20_10_xor1 cin=u_csamul_rca32_fa19_10_or0 fa_xor1=u_csamul_rca32_fa19_11_xor1 fa_or0=u_csamul_rca32_fa19_11_or0
.subckt and_gate a=a[20] b=b[11] out=u_csamul_rca32_and20_11
.subckt fa a=u_csamul_rca32_and20_11 b=u_csamul_rca32_fa21_10_xor1 cin=u_csamul_rca32_fa20_10_or0 fa_xor1=u_csamul_rca32_fa20_11_xor1 fa_or0=u_csamul_rca32_fa20_11_or0
.subckt and_gate a=a[21] b=b[11] out=u_csamul_rca32_and21_11
.subckt fa a=u_csamul_rca32_and21_11 b=u_csamul_rca32_fa22_10_xor1 cin=u_csamul_rca32_fa21_10_or0 fa_xor1=u_csamul_rca32_fa21_11_xor1 fa_or0=u_csamul_rca32_fa21_11_or0
.subckt and_gate a=a[22] b=b[11] out=u_csamul_rca32_and22_11
.subckt fa a=u_csamul_rca32_and22_11 b=u_csamul_rca32_fa23_10_xor1 cin=u_csamul_rca32_fa22_10_or0 fa_xor1=u_csamul_rca32_fa22_11_xor1 fa_or0=u_csamul_rca32_fa22_11_or0
.subckt and_gate a=a[23] b=b[11] out=u_csamul_rca32_and23_11
.subckt fa a=u_csamul_rca32_and23_11 b=u_csamul_rca32_fa24_10_xor1 cin=u_csamul_rca32_fa23_10_or0 fa_xor1=u_csamul_rca32_fa23_11_xor1 fa_or0=u_csamul_rca32_fa23_11_or0
.subckt and_gate a=a[24] b=b[11] out=u_csamul_rca32_and24_11
.subckt fa a=u_csamul_rca32_and24_11 b=u_csamul_rca32_fa25_10_xor1 cin=u_csamul_rca32_fa24_10_or0 fa_xor1=u_csamul_rca32_fa24_11_xor1 fa_or0=u_csamul_rca32_fa24_11_or0
.subckt and_gate a=a[25] b=b[11] out=u_csamul_rca32_and25_11
.subckt fa a=u_csamul_rca32_and25_11 b=u_csamul_rca32_fa26_10_xor1 cin=u_csamul_rca32_fa25_10_or0 fa_xor1=u_csamul_rca32_fa25_11_xor1 fa_or0=u_csamul_rca32_fa25_11_or0
.subckt and_gate a=a[26] b=b[11] out=u_csamul_rca32_and26_11
.subckt fa a=u_csamul_rca32_and26_11 b=u_csamul_rca32_fa27_10_xor1 cin=u_csamul_rca32_fa26_10_or0 fa_xor1=u_csamul_rca32_fa26_11_xor1 fa_or0=u_csamul_rca32_fa26_11_or0
.subckt and_gate a=a[27] b=b[11] out=u_csamul_rca32_and27_11
.subckt fa a=u_csamul_rca32_and27_11 b=u_csamul_rca32_fa28_10_xor1 cin=u_csamul_rca32_fa27_10_or0 fa_xor1=u_csamul_rca32_fa27_11_xor1 fa_or0=u_csamul_rca32_fa27_11_or0
.subckt and_gate a=a[28] b=b[11] out=u_csamul_rca32_and28_11
.subckt fa a=u_csamul_rca32_and28_11 b=u_csamul_rca32_fa29_10_xor1 cin=u_csamul_rca32_fa28_10_or0 fa_xor1=u_csamul_rca32_fa28_11_xor1 fa_or0=u_csamul_rca32_fa28_11_or0
.subckt and_gate a=a[29] b=b[11] out=u_csamul_rca32_and29_11
.subckt fa a=u_csamul_rca32_and29_11 b=u_csamul_rca32_fa30_10_xor1 cin=u_csamul_rca32_fa29_10_or0 fa_xor1=u_csamul_rca32_fa29_11_xor1 fa_or0=u_csamul_rca32_fa29_11_or0
.subckt and_gate a=a[30] b=b[11] out=u_csamul_rca32_and30_11
.subckt fa a=u_csamul_rca32_and30_11 b=u_csamul_rca32_and31_10 cin=u_csamul_rca32_fa30_10_or0 fa_xor1=u_csamul_rca32_fa30_11_xor1 fa_or0=u_csamul_rca32_fa30_11_or0
.subckt and_gate a=a[31] b=b[11] out=u_csamul_rca32_and31_11
.subckt and_gate a=a[0] b=b[12] out=u_csamul_rca32_and0_12
.subckt fa a=u_csamul_rca32_and0_12 b=u_csamul_rca32_fa1_11_xor1 cin=u_csamul_rca32_fa0_11_or0 fa_xor1=u_csamul_rca32_fa0_12_xor1 fa_or0=u_csamul_rca32_fa0_12_or0
.subckt and_gate a=a[1] b=b[12] out=u_csamul_rca32_and1_12
.subckt fa a=u_csamul_rca32_and1_12 b=u_csamul_rca32_fa2_11_xor1 cin=u_csamul_rca32_fa1_11_or0 fa_xor1=u_csamul_rca32_fa1_12_xor1 fa_or0=u_csamul_rca32_fa1_12_or0
.subckt and_gate a=a[2] b=b[12] out=u_csamul_rca32_and2_12
.subckt fa a=u_csamul_rca32_and2_12 b=u_csamul_rca32_fa3_11_xor1 cin=u_csamul_rca32_fa2_11_or0 fa_xor1=u_csamul_rca32_fa2_12_xor1 fa_or0=u_csamul_rca32_fa2_12_or0
.subckt and_gate a=a[3] b=b[12] out=u_csamul_rca32_and3_12
.subckt fa a=u_csamul_rca32_and3_12 b=u_csamul_rca32_fa4_11_xor1 cin=u_csamul_rca32_fa3_11_or0 fa_xor1=u_csamul_rca32_fa3_12_xor1 fa_or0=u_csamul_rca32_fa3_12_or0
.subckt and_gate a=a[4] b=b[12] out=u_csamul_rca32_and4_12
.subckt fa a=u_csamul_rca32_and4_12 b=u_csamul_rca32_fa5_11_xor1 cin=u_csamul_rca32_fa4_11_or0 fa_xor1=u_csamul_rca32_fa4_12_xor1 fa_or0=u_csamul_rca32_fa4_12_or0
.subckt and_gate a=a[5] b=b[12] out=u_csamul_rca32_and5_12
.subckt fa a=u_csamul_rca32_and5_12 b=u_csamul_rca32_fa6_11_xor1 cin=u_csamul_rca32_fa5_11_or0 fa_xor1=u_csamul_rca32_fa5_12_xor1 fa_or0=u_csamul_rca32_fa5_12_or0
.subckt and_gate a=a[6] b=b[12] out=u_csamul_rca32_and6_12
.subckt fa a=u_csamul_rca32_and6_12 b=u_csamul_rca32_fa7_11_xor1 cin=u_csamul_rca32_fa6_11_or0 fa_xor1=u_csamul_rca32_fa6_12_xor1 fa_or0=u_csamul_rca32_fa6_12_or0
.subckt and_gate a=a[7] b=b[12] out=u_csamul_rca32_and7_12
.subckt fa a=u_csamul_rca32_and7_12 b=u_csamul_rca32_fa8_11_xor1 cin=u_csamul_rca32_fa7_11_or0 fa_xor1=u_csamul_rca32_fa7_12_xor1 fa_or0=u_csamul_rca32_fa7_12_or0
.subckt and_gate a=a[8] b=b[12] out=u_csamul_rca32_and8_12
.subckt fa a=u_csamul_rca32_and8_12 b=u_csamul_rca32_fa9_11_xor1 cin=u_csamul_rca32_fa8_11_or0 fa_xor1=u_csamul_rca32_fa8_12_xor1 fa_or0=u_csamul_rca32_fa8_12_or0
.subckt and_gate a=a[9] b=b[12] out=u_csamul_rca32_and9_12
.subckt fa a=u_csamul_rca32_and9_12 b=u_csamul_rca32_fa10_11_xor1 cin=u_csamul_rca32_fa9_11_or0 fa_xor1=u_csamul_rca32_fa9_12_xor1 fa_or0=u_csamul_rca32_fa9_12_or0
.subckt and_gate a=a[10] b=b[12] out=u_csamul_rca32_and10_12
.subckt fa a=u_csamul_rca32_and10_12 b=u_csamul_rca32_fa11_11_xor1 cin=u_csamul_rca32_fa10_11_or0 fa_xor1=u_csamul_rca32_fa10_12_xor1 fa_or0=u_csamul_rca32_fa10_12_or0
.subckt and_gate a=a[11] b=b[12] out=u_csamul_rca32_and11_12
.subckt fa a=u_csamul_rca32_and11_12 b=u_csamul_rca32_fa12_11_xor1 cin=u_csamul_rca32_fa11_11_or0 fa_xor1=u_csamul_rca32_fa11_12_xor1 fa_or0=u_csamul_rca32_fa11_12_or0
.subckt and_gate a=a[12] b=b[12] out=u_csamul_rca32_and12_12
.subckt fa a=u_csamul_rca32_and12_12 b=u_csamul_rca32_fa13_11_xor1 cin=u_csamul_rca32_fa12_11_or0 fa_xor1=u_csamul_rca32_fa12_12_xor1 fa_or0=u_csamul_rca32_fa12_12_or0
.subckt and_gate a=a[13] b=b[12] out=u_csamul_rca32_and13_12
.subckt fa a=u_csamul_rca32_and13_12 b=u_csamul_rca32_fa14_11_xor1 cin=u_csamul_rca32_fa13_11_or0 fa_xor1=u_csamul_rca32_fa13_12_xor1 fa_or0=u_csamul_rca32_fa13_12_or0
.subckt and_gate a=a[14] b=b[12] out=u_csamul_rca32_and14_12
.subckt fa a=u_csamul_rca32_and14_12 b=u_csamul_rca32_fa15_11_xor1 cin=u_csamul_rca32_fa14_11_or0 fa_xor1=u_csamul_rca32_fa14_12_xor1 fa_or0=u_csamul_rca32_fa14_12_or0
.subckt and_gate a=a[15] b=b[12] out=u_csamul_rca32_and15_12
.subckt fa a=u_csamul_rca32_and15_12 b=u_csamul_rca32_fa16_11_xor1 cin=u_csamul_rca32_fa15_11_or0 fa_xor1=u_csamul_rca32_fa15_12_xor1 fa_or0=u_csamul_rca32_fa15_12_or0
.subckt and_gate a=a[16] b=b[12] out=u_csamul_rca32_and16_12
.subckt fa a=u_csamul_rca32_and16_12 b=u_csamul_rca32_fa17_11_xor1 cin=u_csamul_rca32_fa16_11_or0 fa_xor1=u_csamul_rca32_fa16_12_xor1 fa_or0=u_csamul_rca32_fa16_12_or0
.subckt and_gate a=a[17] b=b[12] out=u_csamul_rca32_and17_12
.subckt fa a=u_csamul_rca32_and17_12 b=u_csamul_rca32_fa18_11_xor1 cin=u_csamul_rca32_fa17_11_or0 fa_xor1=u_csamul_rca32_fa17_12_xor1 fa_or0=u_csamul_rca32_fa17_12_or0
.subckt and_gate a=a[18] b=b[12] out=u_csamul_rca32_and18_12
.subckt fa a=u_csamul_rca32_and18_12 b=u_csamul_rca32_fa19_11_xor1 cin=u_csamul_rca32_fa18_11_or0 fa_xor1=u_csamul_rca32_fa18_12_xor1 fa_or0=u_csamul_rca32_fa18_12_or0
.subckt and_gate a=a[19] b=b[12] out=u_csamul_rca32_and19_12
.subckt fa a=u_csamul_rca32_and19_12 b=u_csamul_rca32_fa20_11_xor1 cin=u_csamul_rca32_fa19_11_or0 fa_xor1=u_csamul_rca32_fa19_12_xor1 fa_or0=u_csamul_rca32_fa19_12_or0
.subckt and_gate a=a[20] b=b[12] out=u_csamul_rca32_and20_12
.subckt fa a=u_csamul_rca32_and20_12 b=u_csamul_rca32_fa21_11_xor1 cin=u_csamul_rca32_fa20_11_or0 fa_xor1=u_csamul_rca32_fa20_12_xor1 fa_or0=u_csamul_rca32_fa20_12_or0
.subckt and_gate a=a[21] b=b[12] out=u_csamul_rca32_and21_12
.subckt fa a=u_csamul_rca32_and21_12 b=u_csamul_rca32_fa22_11_xor1 cin=u_csamul_rca32_fa21_11_or0 fa_xor1=u_csamul_rca32_fa21_12_xor1 fa_or0=u_csamul_rca32_fa21_12_or0
.subckt and_gate a=a[22] b=b[12] out=u_csamul_rca32_and22_12
.subckt fa a=u_csamul_rca32_and22_12 b=u_csamul_rca32_fa23_11_xor1 cin=u_csamul_rca32_fa22_11_or0 fa_xor1=u_csamul_rca32_fa22_12_xor1 fa_or0=u_csamul_rca32_fa22_12_or0
.subckt and_gate a=a[23] b=b[12] out=u_csamul_rca32_and23_12
.subckt fa a=u_csamul_rca32_and23_12 b=u_csamul_rca32_fa24_11_xor1 cin=u_csamul_rca32_fa23_11_or0 fa_xor1=u_csamul_rca32_fa23_12_xor1 fa_or0=u_csamul_rca32_fa23_12_or0
.subckt and_gate a=a[24] b=b[12] out=u_csamul_rca32_and24_12
.subckt fa a=u_csamul_rca32_and24_12 b=u_csamul_rca32_fa25_11_xor1 cin=u_csamul_rca32_fa24_11_or0 fa_xor1=u_csamul_rca32_fa24_12_xor1 fa_or0=u_csamul_rca32_fa24_12_or0
.subckt and_gate a=a[25] b=b[12] out=u_csamul_rca32_and25_12
.subckt fa a=u_csamul_rca32_and25_12 b=u_csamul_rca32_fa26_11_xor1 cin=u_csamul_rca32_fa25_11_or0 fa_xor1=u_csamul_rca32_fa25_12_xor1 fa_or0=u_csamul_rca32_fa25_12_or0
.subckt and_gate a=a[26] b=b[12] out=u_csamul_rca32_and26_12
.subckt fa a=u_csamul_rca32_and26_12 b=u_csamul_rca32_fa27_11_xor1 cin=u_csamul_rca32_fa26_11_or0 fa_xor1=u_csamul_rca32_fa26_12_xor1 fa_or0=u_csamul_rca32_fa26_12_or0
.subckt and_gate a=a[27] b=b[12] out=u_csamul_rca32_and27_12
.subckt fa a=u_csamul_rca32_and27_12 b=u_csamul_rca32_fa28_11_xor1 cin=u_csamul_rca32_fa27_11_or0 fa_xor1=u_csamul_rca32_fa27_12_xor1 fa_or0=u_csamul_rca32_fa27_12_or0
.subckt and_gate a=a[28] b=b[12] out=u_csamul_rca32_and28_12
.subckt fa a=u_csamul_rca32_and28_12 b=u_csamul_rca32_fa29_11_xor1 cin=u_csamul_rca32_fa28_11_or0 fa_xor1=u_csamul_rca32_fa28_12_xor1 fa_or0=u_csamul_rca32_fa28_12_or0
.subckt and_gate a=a[29] b=b[12] out=u_csamul_rca32_and29_12
.subckt fa a=u_csamul_rca32_and29_12 b=u_csamul_rca32_fa30_11_xor1 cin=u_csamul_rca32_fa29_11_or0 fa_xor1=u_csamul_rca32_fa29_12_xor1 fa_or0=u_csamul_rca32_fa29_12_or0
.subckt and_gate a=a[30] b=b[12] out=u_csamul_rca32_and30_12
.subckt fa a=u_csamul_rca32_and30_12 b=u_csamul_rca32_and31_11 cin=u_csamul_rca32_fa30_11_or0 fa_xor1=u_csamul_rca32_fa30_12_xor1 fa_or0=u_csamul_rca32_fa30_12_or0
.subckt and_gate a=a[31] b=b[12] out=u_csamul_rca32_and31_12
.subckt and_gate a=a[0] b=b[13] out=u_csamul_rca32_and0_13
.subckt fa a=u_csamul_rca32_and0_13 b=u_csamul_rca32_fa1_12_xor1 cin=u_csamul_rca32_fa0_12_or0 fa_xor1=u_csamul_rca32_fa0_13_xor1 fa_or0=u_csamul_rca32_fa0_13_or0
.subckt and_gate a=a[1] b=b[13] out=u_csamul_rca32_and1_13
.subckt fa a=u_csamul_rca32_and1_13 b=u_csamul_rca32_fa2_12_xor1 cin=u_csamul_rca32_fa1_12_or0 fa_xor1=u_csamul_rca32_fa1_13_xor1 fa_or0=u_csamul_rca32_fa1_13_or0
.subckt and_gate a=a[2] b=b[13] out=u_csamul_rca32_and2_13
.subckt fa a=u_csamul_rca32_and2_13 b=u_csamul_rca32_fa3_12_xor1 cin=u_csamul_rca32_fa2_12_or0 fa_xor1=u_csamul_rca32_fa2_13_xor1 fa_or0=u_csamul_rca32_fa2_13_or0
.subckt and_gate a=a[3] b=b[13] out=u_csamul_rca32_and3_13
.subckt fa a=u_csamul_rca32_and3_13 b=u_csamul_rca32_fa4_12_xor1 cin=u_csamul_rca32_fa3_12_or0 fa_xor1=u_csamul_rca32_fa3_13_xor1 fa_or0=u_csamul_rca32_fa3_13_or0
.subckt and_gate a=a[4] b=b[13] out=u_csamul_rca32_and4_13
.subckt fa a=u_csamul_rca32_and4_13 b=u_csamul_rca32_fa5_12_xor1 cin=u_csamul_rca32_fa4_12_or0 fa_xor1=u_csamul_rca32_fa4_13_xor1 fa_or0=u_csamul_rca32_fa4_13_or0
.subckt and_gate a=a[5] b=b[13] out=u_csamul_rca32_and5_13
.subckt fa a=u_csamul_rca32_and5_13 b=u_csamul_rca32_fa6_12_xor1 cin=u_csamul_rca32_fa5_12_or0 fa_xor1=u_csamul_rca32_fa5_13_xor1 fa_or0=u_csamul_rca32_fa5_13_or0
.subckt and_gate a=a[6] b=b[13] out=u_csamul_rca32_and6_13
.subckt fa a=u_csamul_rca32_and6_13 b=u_csamul_rca32_fa7_12_xor1 cin=u_csamul_rca32_fa6_12_or0 fa_xor1=u_csamul_rca32_fa6_13_xor1 fa_or0=u_csamul_rca32_fa6_13_or0
.subckt and_gate a=a[7] b=b[13] out=u_csamul_rca32_and7_13
.subckt fa a=u_csamul_rca32_and7_13 b=u_csamul_rca32_fa8_12_xor1 cin=u_csamul_rca32_fa7_12_or0 fa_xor1=u_csamul_rca32_fa7_13_xor1 fa_or0=u_csamul_rca32_fa7_13_or0
.subckt and_gate a=a[8] b=b[13] out=u_csamul_rca32_and8_13
.subckt fa a=u_csamul_rca32_and8_13 b=u_csamul_rca32_fa9_12_xor1 cin=u_csamul_rca32_fa8_12_or0 fa_xor1=u_csamul_rca32_fa8_13_xor1 fa_or0=u_csamul_rca32_fa8_13_or0
.subckt and_gate a=a[9] b=b[13] out=u_csamul_rca32_and9_13
.subckt fa a=u_csamul_rca32_and9_13 b=u_csamul_rca32_fa10_12_xor1 cin=u_csamul_rca32_fa9_12_or0 fa_xor1=u_csamul_rca32_fa9_13_xor1 fa_or0=u_csamul_rca32_fa9_13_or0
.subckt and_gate a=a[10] b=b[13] out=u_csamul_rca32_and10_13
.subckt fa a=u_csamul_rca32_and10_13 b=u_csamul_rca32_fa11_12_xor1 cin=u_csamul_rca32_fa10_12_or0 fa_xor1=u_csamul_rca32_fa10_13_xor1 fa_or0=u_csamul_rca32_fa10_13_or0
.subckt and_gate a=a[11] b=b[13] out=u_csamul_rca32_and11_13
.subckt fa a=u_csamul_rca32_and11_13 b=u_csamul_rca32_fa12_12_xor1 cin=u_csamul_rca32_fa11_12_or0 fa_xor1=u_csamul_rca32_fa11_13_xor1 fa_or0=u_csamul_rca32_fa11_13_or0
.subckt and_gate a=a[12] b=b[13] out=u_csamul_rca32_and12_13
.subckt fa a=u_csamul_rca32_and12_13 b=u_csamul_rca32_fa13_12_xor1 cin=u_csamul_rca32_fa12_12_or0 fa_xor1=u_csamul_rca32_fa12_13_xor1 fa_or0=u_csamul_rca32_fa12_13_or0
.subckt and_gate a=a[13] b=b[13] out=u_csamul_rca32_and13_13
.subckt fa a=u_csamul_rca32_and13_13 b=u_csamul_rca32_fa14_12_xor1 cin=u_csamul_rca32_fa13_12_or0 fa_xor1=u_csamul_rca32_fa13_13_xor1 fa_or0=u_csamul_rca32_fa13_13_or0
.subckt and_gate a=a[14] b=b[13] out=u_csamul_rca32_and14_13
.subckt fa a=u_csamul_rca32_and14_13 b=u_csamul_rca32_fa15_12_xor1 cin=u_csamul_rca32_fa14_12_or0 fa_xor1=u_csamul_rca32_fa14_13_xor1 fa_or0=u_csamul_rca32_fa14_13_or0
.subckt and_gate a=a[15] b=b[13] out=u_csamul_rca32_and15_13
.subckt fa a=u_csamul_rca32_and15_13 b=u_csamul_rca32_fa16_12_xor1 cin=u_csamul_rca32_fa15_12_or0 fa_xor1=u_csamul_rca32_fa15_13_xor1 fa_or0=u_csamul_rca32_fa15_13_or0
.subckt and_gate a=a[16] b=b[13] out=u_csamul_rca32_and16_13
.subckt fa a=u_csamul_rca32_and16_13 b=u_csamul_rca32_fa17_12_xor1 cin=u_csamul_rca32_fa16_12_or0 fa_xor1=u_csamul_rca32_fa16_13_xor1 fa_or0=u_csamul_rca32_fa16_13_or0
.subckt and_gate a=a[17] b=b[13] out=u_csamul_rca32_and17_13
.subckt fa a=u_csamul_rca32_and17_13 b=u_csamul_rca32_fa18_12_xor1 cin=u_csamul_rca32_fa17_12_or0 fa_xor1=u_csamul_rca32_fa17_13_xor1 fa_or0=u_csamul_rca32_fa17_13_or0
.subckt and_gate a=a[18] b=b[13] out=u_csamul_rca32_and18_13
.subckt fa a=u_csamul_rca32_and18_13 b=u_csamul_rca32_fa19_12_xor1 cin=u_csamul_rca32_fa18_12_or0 fa_xor1=u_csamul_rca32_fa18_13_xor1 fa_or0=u_csamul_rca32_fa18_13_or0
.subckt and_gate a=a[19] b=b[13] out=u_csamul_rca32_and19_13
.subckt fa a=u_csamul_rca32_and19_13 b=u_csamul_rca32_fa20_12_xor1 cin=u_csamul_rca32_fa19_12_or0 fa_xor1=u_csamul_rca32_fa19_13_xor1 fa_or0=u_csamul_rca32_fa19_13_or0
.subckt and_gate a=a[20] b=b[13] out=u_csamul_rca32_and20_13
.subckt fa a=u_csamul_rca32_and20_13 b=u_csamul_rca32_fa21_12_xor1 cin=u_csamul_rca32_fa20_12_or0 fa_xor1=u_csamul_rca32_fa20_13_xor1 fa_or0=u_csamul_rca32_fa20_13_or0
.subckt and_gate a=a[21] b=b[13] out=u_csamul_rca32_and21_13
.subckt fa a=u_csamul_rca32_and21_13 b=u_csamul_rca32_fa22_12_xor1 cin=u_csamul_rca32_fa21_12_or0 fa_xor1=u_csamul_rca32_fa21_13_xor1 fa_or0=u_csamul_rca32_fa21_13_or0
.subckt and_gate a=a[22] b=b[13] out=u_csamul_rca32_and22_13
.subckt fa a=u_csamul_rca32_and22_13 b=u_csamul_rca32_fa23_12_xor1 cin=u_csamul_rca32_fa22_12_or0 fa_xor1=u_csamul_rca32_fa22_13_xor1 fa_or0=u_csamul_rca32_fa22_13_or0
.subckt and_gate a=a[23] b=b[13] out=u_csamul_rca32_and23_13
.subckt fa a=u_csamul_rca32_and23_13 b=u_csamul_rca32_fa24_12_xor1 cin=u_csamul_rca32_fa23_12_or0 fa_xor1=u_csamul_rca32_fa23_13_xor1 fa_or0=u_csamul_rca32_fa23_13_or0
.subckt and_gate a=a[24] b=b[13] out=u_csamul_rca32_and24_13
.subckt fa a=u_csamul_rca32_and24_13 b=u_csamul_rca32_fa25_12_xor1 cin=u_csamul_rca32_fa24_12_or0 fa_xor1=u_csamul_rca32_fa24_13_xor1 fa_or0=u_csamul_rca32_fa24_13_or0
.subckt and_gate a=a[25] b=b[13] out=u_csamul_rca32_and25_13
.subckt fa a=u_csamul_rca32_and25_13 b=u_csamul_rca32_fa26_12_xor1 cin=u_csamul_rca32_fa25_12_or0 fa_xor1=u_csamul_rca32_fa25_13_xor1 fa_or0=u_csamul_rca32_fa25_13_or0
.subckt and_gate a=a[26] b=b[13] out=u_csamul_rca32_and26_13
.subckt fa a=u_csamul_rca32_and26_13 b=u_csamul_rca32_fa27_12_xor1 cin=u_csamul_rca32_fa26_12_or0 fa_xor1=u_csamul_rca32_fa26_13_xor1 fa_or0=u_csamul_rca32_fa26_13_or0
.subckt and_gate a=a[27] b=b[13] out=u_csamul_rca32_and27_13
.subckt fa a=u_csamul_rca32_and27_13 b=u_csamul_rca32_fa28_12_xor1 cin=u_csamul_rca32_fa27_12_or0 fa_xor1=u_csamul_rca32_fa27_13_xor1 fa_or0=u_csamul_rca32_fa27_13_or0
.subckt and_gate a=a[28] b=b[13] out=u_csamul_rca32_and28_13
.subckt fa a=u_csamul_rca32_and28_13 b=u_csamul_rca32_fa29_12_xor1 cin=u_csamul_rca32_fa28_12_or0 fa_xor1=u_csamul_rca32_fa28_13_xor1 fa_or0=u_csamul_rca32_fa28_13_or0
.subckt and_gate a=a[29] b=b[13] out=u_csamul_rca32_and29_13
.subckt fa a=u_csamul_rca32_and29_13 b=u_csamul_rca32_fa30_12_xor1 cin=u_csamul_rca32_fa29_12_or0 fa_xor1=u_csamul_rca32_fa29_13_xor1 fa_or0=u_csamul_rca32_fa29_13_or0
.subckt and_gate a=a[30] b=b[13] out=u_csamul_rca32_and30_13
.subckt fa a=u_csamul_rca32_and30_13 b=u_csamul_rca32_and31_12 cin=u_csamul_rca32_fa30_12_or0 fa_xor1=u_csamul_rca32_fa30_13_xor1 fa_or0=u_csamul_rca32_fa30_13_or0
.subckt and_gate a=a[31] b=b[13] out=u_csamul_rca32_and31_13
.subckt and_gate a=a[0] b=b[14] out=u_csamul_rca32_and0_14
.subckt fa a=u_csamul_rca32_and0_14 b=u_csamul_rca32_fa1_13_xor1 cin=u_csamul_rca32_fa0_13_or0 fa_xor1=u_csamul_rca32_fa0_14_xor1 fa_or0=u_csamul_rca32_fa0_14_or0
.subckt and_gate a=a[1] b=b[14] out=u_csamul_rca32_and1_14
.subckt fa a=u_csamul_rca32_and1_14 b=u_csamul_rca32_fa2_13_xor1 cin=u_csamul_rca32_fa1_13_or0 fa_xor1=u_csamul_rca32_fa1_14_xor1 fa_or0=u_csamul_rca32_fa1_14_or0
.subckt and_gate a=a[2] b=b[14] out=u_csamul_rca32_and2_14
.subckt fa a=u_csamul_rca32_and2_14 b=u_csamul_rca32_fa3_13_xor1 cin=u_csamul_rca32_fa2_13_or0 fa_xor1=u_csamul_rca32_fa2_14_xor1 fa_or0=u_csamul_rca32_fa2_14_or0
.subckt and_gate a=a[3] b=b[14] out=u_csamul_rca32_and3_14
.subckt fa a=u_csamul_rca32_and3_14 b=u_csamul_rca32_fa4_13_xor1 cin=u_csamul_rca32_fa3_13_or0 fa_xor1=u_csamul_rca32_fa3_14_xor1 fa_or0=u_csamul_rca32_fa3_14_or0
.subckt and_gate a=a[4] b=b[14] out=u_csamul_rca32_and4_14
.subckt fa a=u_csamul_rca32_and4_14 b=u_csamul_rca32_fa5_13_xor1 cin=u_csamul_rca32_fa4_13_or0 fa_xor1=u_csamul_rca32_fa4_14_xor1 fa_or0=u_csamul_rca32_fa4_14_or0
.subckt and_gate a=a[5] b=b[14] out=u_csamul_rca32_and5_14
.subckt fa a=u_csamul_rca32_and5_14 b=u_csamul_rca32_fa6_13_xor1 cin=u_csamul_rca32_fa5_13_or0 fa_xor1=u_csamul_rca32_fa5_14_xor1 fa_or0=u_csamul_rca32_fa5_14_or0
.subckt and_gate a=a[6] b=b[14] out=u_csamul_rca32_and6_14
.subckt fa a=u_csamul_rca32_and6_14 b=u_csamul_rca32_fa7_13_xor1 cin=u_csamul_rca32_fa6_13_or0 fa_xor1=u_csamul_rca32_fa6_14_xor1 fa_or0=u_csamul_rca32_fa6_14_or0
.subckt and_gate a=a[7] b=b[14] out=u_csamul_rca32_and7_14
.subckt fa a=u_csamul_rca32_and7_14 b=u_csamul_rca32_fa8_13_xor1 cin=u_csamul_rca32_fa7_13_or0 fa_xor1=u_csamul_rca32_fa7_14_xor1 fa_or0=u_csamul_rca32_fa7_14_or0
.subckt and_gate a=a[8] b=b[14] out=u_csamul_rca32_and8_14
.subckt fa a=u_csamul_rca32_and8_14 b=u_csamul_rca32_fa9_13_xor1 cin=u_csamul_rca32_fa8_13_or0 fa_xor1=u_csamul_rca32_fa8_14_xor1 fa_or0=u_csamul_rca32_fa8_14_or0
.subckt and_gate a=a[9] b=b[14] out=u_csamul_rca32_and9_14
.subckt fa a=u_csamul_rca32_and9_14 b=u_csamul_rca32_fa10_13_xor1 cin=u_csamul_rca32_fa9_13_or0 fa_xor1=u_csamul_rca32_fa9_14_xor1 fa_or0=u_csamul_rca32_fa9_14_or0
.subckt and_gate a=a[10] b=b[14] out=u_csamul_rca32_and10_14
.subckt fa a=u_csamul_rca32_and10_14 b=u_csamul_rca32_fa11_13_xor1 cin=u_csamul_rca32_fa10_13_or0 fa_xor1=u_csamul_rca32_fa10_14_xor1 fa_or0=u_csamul_rca32_fa10_14_or0
.subckt and_gate a=a[11] b=b[14] out=u_csamul_rca32_and11_14
.subckt fa a=u_csamul_rca32_and11_14 b=u_csamul_rca32_fa12_13_xor1 cin=u_csamul_rca32_fa11_13_or0 fa_xor1=u_csamul_rca32_fa11_14_xor1 fa_or0=u_csamul_rca32_fa11_14_or0
.subckt and_gate a=a[12] b=b[14] out=u_csamul_rca32_and12_14
.subckt fa a=u_csamul_rca32_and12_14 b=u_csamul_rca32_fa13_13_xor1 cin=u_csamul_rca32_fa12_13_or0 fa_xor1=u_csamul_rca32_fa12_14_xor1 fa_or0=u_csamul_rca32_fa12_14_or0
.subckt and_gate a=a[13] b=b[14] out=u_csamul_rca32_and13_14
.subckt fa a=u_csamul_rca32_and13_14 b=u_csamul_rca32_fa14_13_xor1 cin=u_csamul_rca32_fa13_13_or0 fa_xor1=u_csamul_rca32_fa13_14_xor1 fa_or0=u_csamul_rca32_fa13_14_or0
.subckt and_gate a=a[14] b=b[14] out=u_csamul_rca32_and14_14
.subckt fa a=u_csamul_rca32_and14_14 b=u_csamul_rca32_fa15_13_xor1 cin=u_csamul_rca32_fa14_13_or0 fa_xor1=u_csamul_rca32_fa14_14_xor1 fa_or0=u_csamul_rca32_fa14_14_or0
.subckt and_gate a=a[15] b=b[14] out=u_csamul_rca32_and15_14
.subckt fa a=u_csamul_rca32_and15_14 b=u_csamul_rca32_fa16_13_xor1 cin=u_csamul_rca32_fa15_13_or0 fa_xor1=u_csamul_rca32_fa15_14_xor1 fa_or0=u_csamul_rca32_fa15_14_or0
.subckt and_gate a=a[16] b=b[14] out=u_csamul_rca32_and16_14
.subckt fa a=u_csamul_rca32_and16_14 b=u_csamul_rca32_fa17_13_xor1 cin=u_csamul_rca32_fa16_13_or0 fa_xor1=u_csamul_rca32_fa16_14_xor1 fa_or0=u_csamul_rca32_fa16_14_or0
.subckt and_gate a=a[17] b=b[14] out=u_csamul_rca32_and17_14
.subckt fa a=u_csamul_rca32_and17_14 b=u_csamul_rca32_fa18_13_xor1 cin=u_csamul_rca32_fa17_13_or0 fa_xor1=u_csamul_rca32_fa17_14_xor1 fa_or0=u_csamul_rca32_fa17_14_or0
.subckt and_gate a=a[18] b=b[14] out=u_csamul_rca32_and18_14
.subckt fa a=u_csamul_rca32_and18_14 b=u_csamul_rca32_fa19_13_xor1 cin=u_csamul_rca32_fa18_13_or0 fa_xor1=u_csamul_rca32_fa18_14_xor1 fa_or0=u_csamul_rca32_fa18_14_or0
.subckt and_gate a=a[19] b=b[14] out=u_csamul_rca32_and19_14
.subckt fa a=u_csamul_rca32_and19_14 b=u_csamul_rca32_fa20_13_xor1 cin=u_csamul_rca32_fa19_13_or0 fa_xor1=u_csamul_rca32_fa19_14_xor1 fa_or0=u_csamul_rca32_fa19_14_or0
.subckt and_gate a=a[20] b=b[14] out=u_csamul_rca32_and20_14
.subckt fa a=u_csamul_rca32_and20_14 b=u_csamul_rca32_fa21_13_xor1 cin=u_csamul_rca32_fa20_13_or0 fa_xor1=u_csamul_rca32_fa20_14_xor1 fa_or0=u_csamul_rca32_fa20_14_or0
.subckt and_gate a=a[21] b=b[14] out=u_csamul_rca32_and21_14
.subckt fa a=u_csamul_rca32_and21_14 b=u_csamul_rca32_fa22_13_xor1 cin=u_csamul_rca32_fa21_13_or0 fa_xor1=u_csamul_rca32_fa21_14_xor1 fa_or0=u_csamul_rca32_fa21_14_or0
.subckt and_gate a=a[22] b=b[14] out=u_csamul_rca32_and22_14
.subckt fa a=u_csamul_rca32_and22_14 b=u_csamul_rca32_fa23_13_xor1 cin=u_csamul_rca32_fa22_13_or0 fa_xor1=u_csamul_rca32_fa22_14_xor1 fa_or0=u_csamul_rca32_fa22_14_or0
.subckt and_gate a=a[23] b=b[14] out=u_csamul_rca32_and23_14
.subckt fa a=u_csamul_rca32_and23_14 b=u_csamul_rca32_fa24_13_xor1 cin=u_csamul_rca32_fa23_13_or0 fa_xor1=u_csamul_rca32_fa23_14_xor1 fa_or0=u_csamul_rca32_fa23_14_or0
.subckt and_gate a=a[24] b=b[14] out=u_csamul_rca32_and24_14
.subckt fa a=u_csamul_rca32_and24_14 b=u_csamul_rca32_fa25_13_xor1 cin=u_csamul_rca32_fa24_13_or0 fa_xor1=u_csamul_rca32_fa24_14_xor1 fa_or0=u_csamul_rca32_fa24_14_or0
.subckt and_gate a=a[25] b=b[14] out=u_csamul_rca32_and25_14
.subckt fa a=u_csamul_rca32_and25_14 b=u_csamul_rca32_fa26_13_xor1 cin=u_csamul_rca32_fa25_13_or0 fa_xor1=u_csamul_rca32_fa25_14_xor1 fa_or0=u_csamul_rca32_fa25_14_or0
.subckt and_gate a=a[26] b=b[14] out=u_csamul_rca32_and26_14
.subckt fa a=u_csamul_rca32_and26_14 b=u_csamul_rca32_fa27_13_xor1 cin=u_csamul_rca32_fa26_13_or0 fa_xor1=u_csamul_rca32_fa26_14_xor1 fa_or0=u_csamul_rca32_fa26_14_or0
.subckt and_gate a=a[27] b=b[14] out=u_csamul_rca32_and27_14
.subckt fa a=u_csamul_rca32_and27_14 b=u_csamul_rca32_fa28_13_xor1 cin=u_csamul_rca32_fa27_13_or0 fa_xor1=u_csamul_rca32_fa27_14_xor1 fa_or0=u_csamul_rca32_fa27_14_or0
.subckt and_gate a=a[28] b=b[14] out=u_csamul_rca32_and28_14
.subckt fa a=u_csamul_rca32_and28_14 b=u_csamul_rca32_fa29_13_xor1 cin=u_csamul_rca32_fa28_13_or0 fa_xor1=u_csamul_rca32_fa28_14_xor1 fa_or0=u_csamul_rca32_fa28_14_or0
.subckt and_gate a=a[29] b=b[14] out=u_csamul_rca32_and29_14
.subckt fa a=u_csamul_rca32_and29_14 b=u_csamul_rca32_fa30_13_xor1 cin=u_csamul_rca32_fa29_13_or0 fa_xor1=u_csamul_rca32_fa29_14_xor1 fa_or0=u_csamul_rca32_fa29_14_or0
.subckt and_gate a=a[30] b=b[14] out=u_csamul_rca32_and30_14
.subckt fa a=u_csamul_rca32_and30_14 b=u_csamul_rca32_and31_13 cin=u_csamul_rca32_fa30_13_or0 fa_xor1=u_csamul_rca32_fa30_14_xor1 fa_or0=u_csamul_rca32_fa30_14_or0
.subckt and_gate a=a[31] b=b[14] out=u_csamul_rca32_and31_14
.subckt and_gate a=a[0] b=b[15] out=u_csamul_rca32_and0_15
.subckt fa a=u_csamul_rca32_and0_15 b=u_csamul_rca32_fa1_14_xor1 cin=u_csamul_rca32_fa0_14_or0 fa_xor1=u_csamul_rca32_fa0_15_xor1 fa_or0=u_csamul_rca32_fa0_15_or0
.subckt and_gate a=a[1] b=b[15] out=u_csamul_rca32_and1_15
.subckt fa a=u_csamul_rca32_and1_15 b=u_csamul_rca32_fa2_14_xor1 cin=u_csamul_rca32_fa1_14_or0 fa_xor1=u_csamul_rca32_fa1_15_xor1 fa_or0=u_csamul_rca32_fa1_15_or0
.subckt and_gate a=a[2] b=b[15] out=u_csamul_rca32_and2_15
.subckt fa a=u_csamul_rca32_and2_15 b=u_csamul_rca32_fa3_14_xor1 cin=u_csamul_rca32_fa2_14_or0 fa_xor1=u_csamul_rca32_fa2_15_xor1 fa_or0=u_csamul_rca32_fa2_15_or0
.subckt and_gate a=a[3] b=b[15] out=u_csamul_rca32_and3_15
.subckt fa a=u_csamul_rca32_and3_15 b=u_csamul_rca32_fa4_14_xor1 cin=u_csamul_rca32_fa3_14_or0 fa_xor1=u_csamul_rca32_fa3_15_xor1 fa_or0=u_csamul_rca32_fa3_15_or0
.subckt and_gate a=a[4] b=b[15] out=u_csamul_rca32_and4_15
.subckt fa a=u_csamul_rca32_and4_15 b=u_csamul_rca32_fa5_14_xor1 cin=u_csamul_rca32_fa4_14_or0 fa_xor1=u_csamul_rca32_fa4_15_xor1 fa_or0=u_csamul_rca32_fa4_15_or0
.subckt and_gate a=a[5] b=b[15] out=u_csamul_rca32_and5_15
.subckt fa a=u_csamul_rca32_and5_15 b=u_csamul_rca32_fa6_14_xor1 cin=u_csamul_rca32_fa5_14_or0 fa_xor1=u_csamul_rca32_fa5_15_xor1 fa_or0=u_csamul_rca32_fa5_15_or0
.subckt and_gate a=a[6] b=b[15] out=u_csamul_rca32_and6_15
.subckt fa a=u_csamul_rca32_and6_15 b=u_csamul_rca32_fa7_14_xor1 cin=u_csamul_rca32_fa6_14_or0 fa_xor1=u_csamul_rca32_fa6_15_xor1 fa_or0=u_csamul_rca32_fa6_15_or0
.subckt and_gate a=a[7] b=b[15] out=u_csamul_rca32_and7_15
.subckt fa a=u_csamul_rca32_and7_15 b=u_csamul_rca32_fa8_14_xor1 cin=u_csamul_rca32_fa7_14_or0 fa_xor1=u_csamul_rca32_fa7_15_xor1 fa_or0=u_csamul_rca32_fa7_15_or0
.subckt and_gate a=a[8] b=b[15] out=u_csamul_rca32_and8_15
.subckt fa a=u_csamul_rca32_and8_15 b=u_csamul_rca32_fa9_14_xor1 cin=u_csamul_rca32_fa8_14_or0 fa_xor1=u_csamul_rca32_fa8_15_xor1 fa_or0=u_csamul_rca32_fa8_15_or0
.subckt and_gate a=a[9] b=b[15] out=u_csamul_rca32_and9_15
.subckt fa a=u_csamul_rca32_and9_15 b=u_csamul_rca32_fa10_14_xor1 cin=u_csamul_rca32_fa9_14_or0 fa_xor1=u_csamul_rca32_fa9_15_xor1 fa_or0=u_csamul_rca32_fa9_15_or0
.subckt and_gate a=a[10] b=b[15] out=u_csamul_rca32_and10_15
.subckt fa a=u_csamul_rca32_and10_15 b=u_csamul_rca32_fa11_14_xor1 cin=u_csamul_rca32_fa10_14_or0 fa_xor1=u_csamul_rca32_fa10_15_xor1 fa_or0=u_csamul_rca32_fa10_15_or0
.subckt and_gate a=a[11] b=b[15] out=u_csamul_rca32_and11_15
.subckt fa a=u_csamul_rca32_and11_15 b=u_csamul_rca32_fa12_14_xor1 cin=u_csamul_rca32_fa11_14_or0 fa_xor1=u_csamul_rca32_fa11_15_xor1 fa_or0=u_csamul_rca32_fa11_15_or0
.subckt and_gate a=a[12] b=b[15] out=u_csamul_rca32_and12_15
.subckt fa a=u_csamul_rca32_and12_15 b=u_csamul_rca32_fa13_14_xor1 cin=u_csamul_rca32_fa12_14_or0 fa_xor1=u_csamul_rca32_fa12_15_xor1 fa_or0=u_csamul_rca32_fa12_15_or0
.subckt and_gate a=a[13] b=b[15] out=u_csamul_rca32_and13_15
.subckt fa a=u_csamul_rca32_and13_15 b=u_csamul_rca32_fa14_14_xor1 cin=u_csamul_rca32_fa13_14_or0 fa_xor1=u_csamul_rca32_fa13_15_xor1 fa_or0=u_csamul_rca32_fa13_15_or0
.subckt and_gate a=a[14] b=b[15] out=u_csamul_rca32_and14_15
.subckt fa a=u_csamul_rca32_and14_15 b=u_csamul_rca32_fa15_14_xor1 cin=u_csamul_rca32_fa14_14_or0 fa_xor1=u_csamul_rca32_fa14_15_xor1 fa_or0=u_csamul_rca32_fa14_15_or0
.subckt and_gate a=a[15] b=b[15] out=u_csamul_rca32_and15_15
.subckt fa a=u_csamul_rca32_and15_15 b=u_csamul_rca32_fa16_14_xor1 cin=u_csamul_rca32_fa15_14_or0 fa_xor1=u_csamul_rca32_fa15_15_xor1 fa_or0=u_csamul_rca32_fa15_15_or0
.subckt and_gate a=a[16] b=b[15] out=u_csamul_rca32_and16_15
.subckt fa a=u_csamul_rca32_and16_15 b=u_csamul_rca32_fa17_14_xor1 cin=u_csamul_rca32_fa16_14_or0 fa_xor1=u_csamul_rca32_fa16_15_xor1 fa_or0=u_csamul_rca32_fa16_15_or0
.subckt and_gate a=a[17] b=b[15] out=u_csamul_rca32_and17_15
.subckt fa a=u_csamul_rca32_and17_15 b=u_csamul_rca32_fa18_14_xor1 cin=u_csamul_rca32_fa17_14_or0 fa_xor1=u_csamul_rca32_fa17_15_xor1 fa_or0=u_csamul_rca32_fa17_15_or0
.subckt and_gate a=a[18] b=b[15] out=u_csamul_rca32_and18_15
.subckt fa a=u_csamul_rca32_and18_15 b=u_csamul_rca32_fa19_14_xor1 cin=u_csamul_rca32_fa18_14_or0 fa_xor1=u_csamul_rca32_fa18_15_xor1 fa_or0=u_csamul_rca32_fa18_15_or0
.subckt and_gate a=a[19] b=b[15] out=u_csamul_rca32_and19_15
.subckt fa a=u_csamul_rca32_and19_15 b=u_csamul_rca32_fa20_14_xor1 cin=u_csamul_rca32_fa19_14_or0 fa_xor1=u_csamul_rca32_fa19_15_xor1 fa_or0=u_csamul_rca32_fa19_15_or0
.subckt and_gate a=a[20] b=b[15] out=u_csamul_rca32_and20_15
.subckt fa a=u_csamul_rca32_and20_15 b=u_csamul_rca32_fa21_14_xor1 cin=u_csamul_rca32_fa20_14_or0 fa_xor1=u_csamul_rca32_fa20_15_xor1 fa_or0=u_csamul_rca32_fa20_15_or0
.subckt and_gate a=a[21] b=b[15] out=u_csamul_rca32_and21_15
.subckt fa a=u_csamul_rca32_and21_15 b=u_csamul_rca32_fa22_14_xor1 cin=u_csamul_rca32_fa21_14_or0 fa_xor1=u_csamul_rca32_fa21_15_xor1 fa_or0=u_csamul_rca32_fa21_15_or0
.subckt and_gate a=a[22] b=b[15] out=u_csamul_rca32_and22_15
.subckt fa a=u_csamul_rca32_and22_15 b=u_csamul_rca32_fa23_14_xor1 cin=u_csamul_rca32_fa22_14_or0 fa_xor1=u_csamul_rca32_fa22_15_xor1 fa_or0=u_csamul_rca32_fa22_15_or0
.subckt and_gate a=a[23] b=b[15] out=u_csamul_rca32_and23_15
.subckt fa a=u_csamul_rca32_and23_15 b=u_csamul_rca32_fa24_14_xor1 cin=u_csamul_rca32_fa23_14_or0 fa_xor1=u_csamul_rca32_fa23_15_xor1 fa_or0=u_csamul_rca32_fa23_15_or0
.subckt and_gate a=a[24] b=b[15] out=u_csamul_rca32_and24_15
.subckt fa a=u_csamul_rca32_and24_15 b=u_csamul_rca32_fa25_14_xor1 cin=u_csamul_rca32_fa24_14_or0 fa_xor1=u_csamul_rca32_fa24_15_xor1 fa_or0=u_csamul_rca32_fa24_15_or0
.subckt and_gate a=a[25] b=b[15] out=u_csamul_rca32_and25_15
.subckt fa a=u_csamul_rca32_and25_15 b=u_csamul_rca32_fa26_14_xor1 cin=u_csamul_rca32_fa25_14_or0 fa_xor1=u_csamul_rca32_fa25_15_xor1 fa_or0=u_csamul_rca32_fa25_15_or0
.subckt and_gate a=a[26] b=b[15] out=u_csamul_rca32_and26_15
.subckt fa a=u_csamul_rca32_and26_15 b=u_csamul_rca32_fa27_14_xor1 cin=u_csamul_rca32_fa26_14_or0 fa_xor1=u_csamul_rca32_fa26_15_xor1 fa_or0=u_csamul_rca32_fa26_15_or0
.subckt and_gate a=a[27] b=b[15] out=u_csamul_rca32_and27_15
.subckt fa a=u_csamul_rca32_and27_15 b=u_csamul_rca32_fa28_14_xor1 cin=u_csamul_rca32_fa27_14_or0 fa_xor1=u_csamul_rca32_fa27_15_xor1 fa_or0=u_csamul_rca32_fa27_15_or0
.subckt and_gate a=a[28] b=b[15] out=u_csamul_rca32_and28_15
.subckt fa a=u_csamul_rca32_and28_15 b=u_csamul_rca32_fa29_14_xor1 cin=u_csamul_rca32_fa28_14_or0 fa_xor1=u_csamul_rca32_fa28_15_xor1 fa_or0=u_csamul_rca32_fa28_15_or0
.subckt and_gate a=a[29] b=b[15] out=u_csamul_rca32_and29_15
.subckt fa a=u_csamul_rca32_and29_15 b=u_csamul_rca32_fa30_14_xor1 cin=u_csamul_rca32_fa29_14_or0 fa_xor1=u_csamul_rca32_fa29_15_xor1 fa_or0=u_csamul_rca32_fa29_15_or0
.subckt and_gate a=a[30] b=b[15] out=u_csamul_rca32_and30_15
.subckt fa a=u_csamul_rca32_and30_15 b=u_csamul_rca32_and31_14 cin=u_csamul_rca32_fa30_14_or0 fa_xor1=u_csamul_rca32_fa30_15_xor1 fa_or0=u_csamul_rca32_fa30_15_or0
.subckt and_gate a=a[31] b=b[15] out=u_csamul_rca32_and31_15
.subckt and_gate a=a[0] b=b[16] out=u_csamul_rca32_and0_16
.subckt fa a=u_csamul_rca32_and0_16 b=u_csamul_rca32_fa1_15_xor1 cin=u_csamul_rca32_fa0_15_or0 fa_xor1=u_csamul_rca32_fa0_16_xor1 fa_or0=u_csamul_rca32_fa0_16_or0
.subckt and_gate a=a[1] b=b[16] out=u_csamul_rca32_and1_16
.subckt fa a=u_csamul_rca32_and1_16 b=u_csamul_rca32_fa2_15_xor1 cin=u_csamul_rca32_fa1_15_or0 fa_xor1=u_csamul_rca32_fa1_16_xor1 fa_or0=u_csamul_rca32_fa1_16_or0
.subckt and_gate a=a[2] b=b[16] out=u_csamul_rca32_and2_16
.subckt fa a=u_csamul_rca32_and2_16 b=u_csamul_rca32_fa3_15_xor1 cin=u_csamul_rca32_fa2_15_or0 fa_xor1=u_csamul_rca32_fa2_16_xor1 fa_or0=u_csamul_rca32_fa2_16_or0
.subckt and_gate a=a[3] b=b[16] out=u_csamul_rca32_and3_16
.subckt fa a=u_csamul_rca32_and3_16 b=u_csamul_rca32_fa4_15_xor1 cin=u_csamul_rca32_fa3_15_or0 fa_xor1=u_csamul_rca32_fa3_16_xor1 fa_or0=u_csamul_rca32_fa3_16_or0
.subckt and_gate a=a[4] b=b[16] out=u_csamul_rca32_and4_16
.subckt fa a=u_csamul_rca32_and4_16 b=u_csamul_rca32_fa5_15_xor1 cin=u_csamul_rca32_fa4_15_or0 fa_xor1=u_csamul_rca32_fa4_16_xor1 fa_or0=u_csamul_rca32_fa4_16_or0
.subckt and_gate a=a[5] b=b[16] out=u_csamul_rca32_and5_16
.subckt fa a=u_csamul_rca32_and5_16 b=u_csamul_rca32_fa6_15_xor1 cin=u_csamul_rca32_fa5_15_or0 fa_xor1=u_csamul_rca32_fa5_16_xor1 fa_or0=u_csamul_rca32_fa5_16_or0
.subckt and_gate a=a[6] b=b[16] out=u_csamul_rca32_and6_16
.subckt fa a=u_csamul_rca32_and6_16 b=u_csamul_rca32_fa7_15_xor1 cin=u_csamul_rca32_fa6_15_or0 fa_xor1=u_csamul_rca32_fa6_16_xor1 fa_or0=u_csamul_rca32_fa6_16_or0
.subckt and_gate a=a[7] b=b[16] out=u_csamul_rca32_and7_16
.subckt fa a=u_csamul_rca32_and7_16 b=u_csamul_rca32_fa8_15_xor1 cin=u_csamul_rca32_fa7_15_or0 fa_xor1=u_csamul_rca32_fa7_16_xor1 fa_or0=u_csamul_rca32_fa7_16_or0
.subckt and_gate a=a[8] b=b[16] out=u_csamul_rca32_and8_16
.subckt fa a=u_csamul_rca32_and8_16 b=u_csamul_rca32_fa9_15_xor1 cin=u_csamul_rca32_fa8_15_or0 fa_xor1=u_csamul_rca32_fa8_16_xor1 fa_or0=u_csamul_rca32_fa8_16_or0
.subckt and_gate a=a[9] b=b[16] out=u_csamul_rca32_and9_16
.subckt fa a=u_csamul_rca32_and9_16 b=u_csamul_rca32_fa10_15_xor1 cin=u_csamul_rca32_fa9_15_or0 fa_xor1=u_csamul_rca32_fa9_16_xor1 fa_or0=u_csamul_rca32_fa9_16_or0
.subckt and_gate a=a[10] b=b[16] out=u_csamul_rca32_and10_16
.subckt fa a=u_csamul_rca32_and10_16 b=u_csamul_rca32_fa11_15_xor1 cin=u_csamul_rca32_fa10_15_or0 fa_xor1=u_csamul_rca32_fa10_16_xor1 fa_or0=u_csamul_rca32_fa10_16_or0
.subckt and_gate a=a[11] b=b[16] out=u_csamul_rca32_and11_16
.subckt fa a=u_csamul_rca32_and11_16 b=u_csamul_rca32_fa12_15_xor1 cin=u_csamul_rca32_fa11_15_or0 fa_xor1=u_csamul_rca32_fa11_16_xor1 fa_or0=u_csamul_rca32_fa11_16_or0
.subckt and_gate a=a[12] b=b[16] out=u_csamul_rca32_and12_16
.subckt fa a=u_csamul_rca32_and12_16 b=u_csamul_rca32_fa13_15_xor1 cin=u_csamul_rca32_fa12_15_or0 fa_xor1=u_csamul_rca32_fa12_16_xor1 fa_or0=u_csamul_rca32_fa12_16_or0
.subckt and_gate a=a[13] b=b[16] out=u_csamul_rca32_and13_16
.subckt fa a=u_csamul_rca32_and13_16 b=u_csamul_rca32_fa14_15_xor1 cin=u_csamul_rca32_fa13_15_or0 fa_xor1=u_csamul_rca32_fa13_16_xor1 fa_or0=u_csamul_rca32_fa13_16_or0
.subckt and_gate a=a[14] b=b[16] out=u_csamul_rca32_and14_16
.subckt fa a=u_csamul_rca32_and14_16 b=u_csamul_rca32_fa15_15_xor1 cin=u_csamul_rca32_fa14_15_or0 fa_xor1=u_csamul_rca32_fa14_16_xor1 fa_or0=u_csamul_rca32_fa14_16_or0
.subckt and_gate a=a[15] b=b[16] out=u_csamul_rca32_and15_16
.subckt fa a=u_csamul_rca32_and15_16 b=u_csamul_rca32_fa16_15_xor1 cin=u_csamul_rca32_fa15_15_or0 fa_xor1=u_csamul_rca32_fa15_16_xor1 fa_or0=u_csamul_rca32_fa15_16_or0
.subckt and_gate a=a[16] b=b[16] out=u_csamul_rca32_and16_16
.subckt fa a=u_csamul_rca32_and16_16 b=u_csamul_rca32_fa17_15_xor1 cin=u_csamul_rca32_fa16_15_or0 fa_xor1=u_csamul_rca32_fa16_16_xor1 fa_or0=u_csamul_rca32_fa16_16_or0
.subckt and_gate a=a[17] b=b[16] out=u_csamul_rca32_and17_16
.subckt fa a=u_csamul_rca32_and17_16 b=u_csamul_rca32_fa18_15_xor1 cin=u_csamul_rca32_fa17_15_or0 fa_xor1=u_csamul_rca32_fa17_16_xor1 fa_or0=u_csamul_rca32_fa17_16_or0
.subckt and_gate a=a[18] b=b[16] out=u_csamul_rca32_and18_16
.subckt fa a=u_csamul_rca32_and18_16 b=u_csamul_rca32_fa19_15_xor1 cin=u_csamul_rca32_fa18_15_or0 fa_xor1=u_csamul_rca32_fa18_16_xor1 fa_or0=u_csamul_rca32_fa18_16_or0
.subckt and_gate a=a[19] b=b[16] out=u_csamul_rca32_and19_16
.subckt fa a=u_csamul_rca32_and19_16 b=u_csamul_rca32_fa20_15_xor1 cin=u_csamul_rca32_fa19_15_or0 fa_xor1=u_csamul_rca32_fa19_16_xor1 fa_or0=u_csamul_rca32_fa19_16_or0
.subckt and_gate a=a[20] b=b[16] out=u_csamul_rca32_and20_16
.subckt fa a=u_csamul_rca32_and20_16 b=u_csamul_rca32_fa21_15_xor1 cin=u_csamul_rca32_fa20_15_or0 fa_xor1=u_csamul_rca32_fa20_16_xor1 fa_or0=u_csamul_rca32_fa20_16_or0
.subckt and_gate a=a[21] b=b[16] out=u_csamul_rca32_and21_16
.subckt fa a=u_csamul_rca32_and21_16 b=u_csamul_rca32_fa22_15_xor1 cin=u_csamul_rca32_fa21_15_or0 fa_xor1=u_csamul_rca32_fa21_16_xor1 fa_or0=u_csamul_rca32_fa21_16_or0
.subckt and_gate a=a[22] b=b[16] out=u_csamul_rca32_and22_16
.subckt fa a=u_csamul_rca32_and22_16 b=u_csamul_rca32_fa23_15_xor1 cin=u_csamul_rca32_fa22_15_or0 fa_xor1=u_csamul_rca32_fa22_16_xor1 fa_or0=u_csamul_rca32_fa22_16_or0
.subckt and_gate a=a[23] b=b[16] out=u_csamul_rca32_and23_16
.subckt fa a=u_csamul_rca32_and23_16 b=u_csamul_rca32_fa24_15_xor1 cin=u_csamul_rca32_fa23_15_or0 fa_xor1=u_csamul_rca32_fa23_16_xor1 fa_or0=u_csamul_rca32_fa23_16_or0
.subckt and_gate a=a[24] b=b[16] out=u_csamul_rca32_and24_16
.subckt fa a=u_csamul_rca32_and24_16 b=u_csamul_rca32_fa25_15_xor1 cin=u_csamul_rca32_fa24_15_or0 fa_xor1=u_csamul_rca32_fa24_16_xor1 fa_or0=u_csamul_rca32_fa24_16_or0
.subckt and_gate a=a[25] b=b[16] out=u_csamul_rca32_and25_16
.subckt fa a=u_csamul_rca32_and25_16 b=u_csamul_rca32_fa26_15_xor1 cin=u_csamul_rca32_fa25_15_or0 fa_xor1=u_csamul_rca32_fa25_16_xor1 fa_or0=u_csamul_rca32_fa25_16_or0
.subckt and_gate a=a[26] b=b[16] out=u_csamul_rca32_and26_16
.subckt fa a=u_csamul_rca32_and26_16 b=u_csamul_rca32_fa27_15_xor1 cin=u_csamul_rca32_fa26_15_or0 fa_xor1=u_csamul_rca32_fa26_16_xor1 fa_or0=u_csamul_rca32_fa26_16_or0
.subckt and_gate a=a[27] b=b[16] out=u_csamul_rca32_and27_16
.subckt fa a=u_csamul_rca32_and27_16 b=u_csamul_rca32_fa28_15_xor1 cin=u_csamul_rca32_fa27_15_or0 fa_xor1=u_csamul_rca32_fa27_16_xor1 fa_or0=u_csamul_rca32_fa27_16_or0
.subckt and_gate a=a[28] b=b[16] out=u_csamul_rca32_and28_16
.subckt fa a=u_csamul_rca32_and28_16 b=u_csamul_rca32_fa29_15_xor1 cin=u_csamul_rca32_fa28_15_or0 fa_xor1=u_csamul_rca32_fa28_16_xor1 fa_or0=u_csamul_rca32_fa28_16_or0
.subckt and_gate a=a[29] b=b[16] out=u_csamul_rca32_and29_16
.subckt fa a=u_csamul_rca32_and29_16 b=u_csamul_rca32_fa30_15_xor1 cin=u_csamul_rca32_fa29_15_or0 fa_xor1=u_csamul_rca32_fa29_16_xor1 fa_or0=u_csamul_rca32_fa29_16_or0
.subckt and_gate a=a[30] b=b[16] out=u_csamul_rca32_and30_16
.subckt fa a=u_csamul_rca32_and30_16 b=u_csamul_rca32_and31_15 cin=u_csamul_rca32_fa30_15_or0 fa_xor1=u_csamul_rca32_fa30_16_xor1 fa_or0=u_csamul_rca32_fa30_16_or0
.subckt and_gate a=a[31] b=b[16] out=u_csamul_rca32_and31_16
.subckt and_gate a=a[0] b=b[17] out=u_csamul_rca32_and0_17
.subckt fa a=u_csamul_rca32_and0_17 b=u_csamul_rca32_fa1_16_xor1 cin=u_csamul_rca32_fa0_16_or0 fa_xor1=u_csamul_rca32_fa0_17_xor1 fa_or0=u_csamul_rca32_fa0_17_or0
.subckt and_gate a=a[1] b=b[17] out=u_csamul_rca32_and1_17
.subckt fa a=u_csamul_rca32_and1_17 b=u_csamul_rca32_fa2_16_xor1 cin=u_csamul_rca32_fa1_16_or0 fa_xor1=u_csamul_rca32_fa1_17_xor1 fa_or0=u_csamul_rca32_fa1_17_or0
.subckt and_gate a=a[2] b=b[17] out=u_csamul_rca32_and2_17
.subckt fa a=u_csamul_rca32_and2_17 b=u_csamul_rca32_fa3_16_xor1 cin=u_csamul_rca32_fa2_16_or0 fa_xor1=u_csamul_rca32_fa2_17_xor1 fa_or0=u_csamul_rca32_fa2_17_or0
.subckt and_gate a=a[3] b=b[17] out=u_csamul_rca32_and3_17
.subckt fa a=u_csamul_rca32_and3_17 b=u_csamul_rca32_fa4_16_xor1 cin=u_csamul_rca32_fa3_16_or0 fa_xor1=u_csamul_rca32_fa3_17_xor1 fa_or0=u_csamul_rca32_fa3_17_or0
.subckt and_gate a=a[4] b=b[17] out=u_csamul_rca32_and4_17
.subckt fa a=u_csamul_rca32_and4_17 b=u_csamul_rca32_fa5_16_xor1 cin=u_csamul_rca32_fa4_16_or0 fa_xor1=u_csamul_rca32_fa4_17_xor1 fa_or0=u_csamul_rca32_fa4_17_or0
.subckt and_gate a=a[5] b=b[17] out=u_csamul_rca32_and5_17
.subckt fa a=u_csamul_rca32_and5_17 b=u_csamul_rca32_fa6_16_xor1 cin=u_csamul_rca32_fa5_16_or0 fa_xor1=u_csamul_rca32_fa5_17_xor1 fa_or0=u_csamul_rca32_fa5_17_or0
.subckt and_gate a=a[6] b=b[17] out=u_csamul_rca32_and6_17
.subckt fa a=u_csamul_rca32_and6_17 b=u_csamul_rca32_fa7_16_xor1 cin=u_csamul_rca32_fa6_16_or0 fa_xor1=u_csamul_rca32_fa6_17_xor1 fa_or0=u_csamul_rca32_fa6_17_or0
.subckt and_gate a=a[7] b=b[17] out=u_csamul_rca32_and7_17
.subckt fa a=u_csamul_rca32_and7_17 b=u_csamul_rca32_fa8_16_xor1 cin=u_csamul_rca32_fa7_16_or0 fa_xor1=u_csamul_rca32_fa7_17_xor1 fa_or0=u_csamul_rca32_fa7_17_or0
.subckt and_gate a=a[8] b=b[17] out=u_csamul_rca32_and8_17
.subckt fa a=u_csamul_rca32_and8_17 b=u_csamul_rca32_fa9_16_xor1 cin=u_csamul_rca32_fa8_16_or0 fa_xor1=u_csamul_rca32_fa8_17_xor1 fa_or0=u_csamul_rca32_fa8_17_or0
.subckt and_gate a=a[9] b=b[17] out=u_csamul_rca32_and9_17
.subckt fa a=u_csamul_rca32_and9_17 b=u_csamul_rca32_fa10_16_xor1 cin=u_csamul_rca32_fa9_16_or0 fa_xor1=u_csamul_rca32_fa9_17_xor1 fa_or0=u_csamul_rca32_fa9_17_or0
.subckt and_gate a=a[10] b=b[17] out=u_csamul_rca32_and10_17
.subckt fa a=u_csamul_rca32_and10_17 b=u_csamul_rca32_fa11_16_xor1 cin=u_csamul_rca32_fa10_16_or0 fa_xor1=u_csamul_rca32_fa10_17_xor1 fa_or0=u_csamul_rca32_fa10_17_or0
.subckt and_gate a=a[11] b=b[17] out=u_csamul_rca32_and11_17
.subckt fa a=u_csamul_rca32_and11_17 b=u_csamul_rca32_fa12_16_xor1 cin=u_csamul_rca32_fa11_16_or0 fa_xor1=u_csamul_rca32_fa11_17_xor1 fa_or0=u_csamul_rca32_fa11_17_or0
.subckt and_gate a=a[12] b=b[17] out=u_csamul_rca32_and12_17
.subckt fa a=u_csamul_rca32_and12_17 b=u_csamul_rca32_fa13_16_xor1 cin=u_csamul_rca32_fa12_16_or0 fa_xor1=u_csamul_rca32_fa12_17_xor1 fa_or0=u_csamul_rca32_fa12_17_or0
.subckt and_gate a=a[13] b=b[17] out=u_csamul_rca32_and13_17
.subckt fa a=u_csamul_rca32_and13_17 b=u_csamul_rca32_fa14_16_xor1 cin=u_csamul_rca32_fa13_16_or0 fa_xor1=u_csamul_rca32_fa13_17_xor1 fa_or0=u_csamul_rca32_fa13_17_or0
.subckt and_gate a=a[14] b=b[17] out=u_csamul_rca32_and14_17
.subckt fa a=u_csamul_rca32_and14_17 b=u_csamul_rca32_fa15_16_xor1 cin=u_csamul_rca32_fa14_16_or0 fa_xor1=u_csamul_rca32_fa14_17_xor1 fa_or0=u_csamul_rca32_fa14_17_or0
.subckt and_gate a=a[15] b=b[17] out=u_csamul_rca32_and15_17
.subckt fa a=u_csamul_rca32_and15_17 b=u_csamul_rca32_fa16_16_xor1 cin=u_csamul_rca32_fa15_16_or0 fa_xor1=u_csamul_rca32_fa15_17_xor1 fa_or0=u_csamul_rca32_fa15_17_or0
.subckt and_gate a=a[16] b=b[17] out=u_csamul_rca32_and16_17
.subckt fa a=u_csamul_rca32_and16_17 b=u_csamul_rca32_fa17_16_xor1 cin=u_csamul_rca32_fa16_16_or0 fa_xor1=u_csamul_rca32_fa16_17_xor1 fa_or0=u_csamul_rca32_fa16_17_or0
.subckt and_gate a=a[17] b=b[17] out=u_csamul_rca32_and17_17
.subckt fa a=u_csamul_rca32_and17_17 b=u_csamul_rca32_fa18_16_xor1 cin=u_csamul_rca32_fa17_16_or0 fa_xor1=u_csamul_rca32_fa17_17_xor1 fa_or0=u_csamul_rca32_fa17_17_or0
.subckt and_gate a=a[18] b=b[17] out=u_csamul_rca32_and18_17
.subckt fa a=u_csamul_rca32_and18_17 b=u_csamul_rca32_fa19_16_xor1 cin=u_csamul_rca32_fa18_16_or0 fa_xor1=u_csamul_rca32_fa18_17_xor1 fa_or0=u_csamul_rca32_fa18_17_or0
.subckt and_gate a=a[19] b=b[17] out=u_csamul_rca32_and19_17
.subckt fa a=u_csamul_rca32_and19_17 b=u_csamul_rca32_fa20_16_xor1 cin=u_csamul_rca32_fa19_16_or0 fa_xor1=u_csamul_rca32_fa19_17_xor1 fa_or0=u_csamul_rca32_fa19_17_or0
.subckt and_gate a=a[20] b=b[17] out=u_csamul_rca32_and20_17
.subckt fa a=u_csamul_rca32_and20_17 b=u_csamul_rca32_fa21_16_xor1 cin=u_csamul_rca32_fa20_16_or0 fa_xor1=u_csamul_rca32_fa20_17_xor1 fa_or0=u_csamul_rca32_fa20_17_or0
.subckt and_gate a=a[21] b=b[17] out=u_csamul_rca32_and21_17
.subckt fa a=u_csamul_rca32_and21_17 b=u_csamul_rca32_fa22_16_xor1 cin=u_csamul_rca32_fa21_16_or0 fa_xor1=u_csamul_rca32_fa21_17_xor1 fa_or0=u_csamul_rca32_fa21_17_or0
.subckt and_gate a=a[22] b=b[17] out=u_csamul_rca32_and22_17
.subckt fa a=u_csamul_rca32_and22_17 b=u_csamul_rca32_fa23_16_xor1 cin=u_csamul_rca32_fa22_16_or0 fa_xor1=u_csamul_rca32_fa22_17_xor1 fa_or0=u_csamul_rca32_fa22_17_or0
.subckt and_gate a=a[23] b=b[17] out=u_csamul_rca32_and23_17
.subckt fa a=u_csamul_rca32_and23_17 b=u_csamul_rca32_fa24_16_xor1 cin=u_csamul_rca32_fa23_16_or0 fa_xor1=u_csamul_rca32_fa23_17_xor1 fa_or0=u_csamul_rca32_fa23_17_or0
.subckt and_gate a=a[24] b=b[17] out=u_csamul_rca32_and24_17
.subckt fa a=u_csamul_rca32_and24_17 b=u_csamul_rca32_fa25_16_xor1 cin=u_csamul_rca32_fa24_16_or0 fa_xor1=u_csamul_rca32_fa24_17_xor1 fa_or0=u_csamul_rca32_fa24_17_or0
.subckt and_gate a=a[25] b=b[17] out=u_csamul_rca32_and25_17
.subckt fa a=u_csamul_rca32_and25_17 b=u_csamul_rca32_fa26_16_xor1 cin=u_csamul_rca32_fa25_16_or0 fa_xor1=u_csamul_rca32_fa25_17_xor1 fa_or0=u_csamul_rca32_fa25_17_or0
.subckt and_gate a=a[26] b=b[17] out=u_csamul_rca32_and26_17
.subckt fa a=u_csamul_rca32_and26_17 b=u_csamul_rca32_fa27_16_xor1 cin=u_csamul_rca32_fa26_16_or0 fa_xor1=u_csamul_rca32_fa26_17_xor1 fa_or0=u_csamul_rca32_fa26_17_or0
.subckt and_gate a=a[27] b=b[17] out=u_csamul_rca32_and27_17
.subckt fa a=u_csamul_rca32_and27_17 b=u_csamul_rca32_fa28_16_xor1 cin=u_csamul_rca32_fa27_16_or0 fa_xor1=u_csamul_rca32_fa27_17_xor1 fa_or0=u_csamul_rca32_fa27_17_or0
.subckt and_gate a=a[28] b=b[17] out=u_csamul_rca32_and28_17
.subckt fa a=u_csamul_rca32_and28_17 b=u_csamul_rca32_fa29_16_xor1 cin=u_csamul_rca32_fa28_16_or0 fa_xor1=u_csamul_rca32_fa28_17_xor1 fa_or0=u_csamul_rca32_fa28_17_or0
.subckt and_gate a=a[29] b=b[17] out=u_csamul_rca32_and29_17
.subckt fa a=u_csamul_rca32_and29_17 b=u_csamul_rca32_fa30_16_xor1 cin=u_csamul_rca32_fa29_16_or0 fa_xor1=u_csamul_rca32_fa29_17_xor1 fa_or0=u_csamul_rca32_fa29_17_or0
.subckt and_gate a=a[30] b=b[17] out=u_csamul_rca32_and30_17
.subckt fa a=u_csamul_rca32_and30_17 b=u_csamul_rca32_and31_16 cin=u_csamul_rca32_fa30_16_or0 fa_xor1=u_csamul_rca32_fa30_17_xor1 fa_or0=u_csamul_rca32_fa30_17_or0
.subckt and_gate a=a[31] b=b[17] out=u_csamul_rca32_and31_17
.subckt and_gate a=a[0] b=b[18] out=u_csamul_rca32_and0_18
.subckt fa a=u_csamul_rca32_and0_18 b=u_csamul_rca32_fa1_17_xor1 cin=u_csamul_rca32_fa0_17_or0 fa_xor1=u_csamul_rca32_fa0_18_xor1 fa_or0=u_csamul_rca32_fa0_18_or0
.subckt and_gate a=a[1] b=b[18] out=u_csamul_rca32_and1_18
.subckt fa a=u_csamul_rca32_and1_18 b=u_csamul_rca32_fa2_17_xor1 cin=u_csamul_rca32_fa1_17_or0 fa_xor1=u_csamul_rca32_fa1_18_xor1 fa_or0=u_csamul_rca32_fa1_18_or0
.subckt and_gate a=a[2] b=b[18] out=u_csamul_rca32_and2_18
.subckt fa a=u_csamul_rca32_and2_18 b=u_csamul_rca32_fa3_17_xor1 cin=u_csamul_rca32_fa2_17_or0 fa_xor1=u_csamul_rca32_fa2_18_xor1 fa_or0=u_csamul_rca32_fa2_18_or0
.subckt and_gate a=a[3] b=b[18] out=u_csamul_rca32_and3_18
.subckt fa a=u_csamul_rca32_and3_18 b=u_csamul_rca32_fa4_17_xor1 cin=u_csamul_rca32_fa3_17_or0 fa_xor1=u_csamul_rca32_fa3_18_xor1 fa_or0=u_csamul_rca32_fa3_18_or0
.subckt and_gate a=a[4] b=b[18] out=u_csamul_rca32_and4_18
.subckt fa a=u_csamul_rca32_and4_18 b=u_csamul_rca32_fa5_17_xor1 cin=u_csamul_rca32_fa4_17_or0 fa_xor1=u_csamul_rca32_fa4_18_xor1 fa_or0=u_csamul_rca32_fa4_18_or0
.subckt and_gate a=a[5] b=b[18] out=u_csamul_rca32_and5_18
.subckt fa a=u_csamul_rca32_and5_18 b=u_csamul_rca32_fa6_17_xor1 cin=u_csamul_rca32_fa5_17_or0 fa_xor1=u_csamul_rca32_fa5_18_xor1 fa_or0=u_csamul_rca32_fa5_18_or0
.subckt and_gate a=a[6] b=b[18] out=u_csamul_rca32_and6_18
.subckt fa a=u_csamul_rca32_and6_18 b=u_csamul_rca32_fa7_17_xor1 cin=u_csamul_rca32_fa6_17_or0 fa_xor1=u_csamul_rca32_fa6_18_xor1 fa_or0=u_csamul_rca32_fa6_18_or0
.subckt and_gate a=a[7] b=b[18] out=u_csamul_rca32_and7_18
.subckt fa a=u_csamul_rca32_and7_18 b=u_csamul_rca32_fa8_17_xor1 cin=u_csamul_rca32_fa7_17_or0 fa_xor1=u_csamul_rca32_fa7_18_xor1 fa_or0=u_csamul_rca32_fa7_18_or0
.subckt and_gate a=a[8] b=b[18] out=u_csamul_rca32_and8_18
.subckt fa a=u_csamul_rca32_and8_18 b=u_csamul_rca32_fa9_17_xor1 cin=u_csamul_rca32_fa8_17_or0 fa_xor1=u_csamul_rca32_fa8_18_xor1 fa_or0=u_csamul_rca32_fa8_18_or0
.subckt and_gate a=a[9] b=b[18] out=u_csamul_rca32_and9_18
.subckt fa a=u_csamul_rca32_and9_18 b=u_csamul_rca32_fa10_17_xor1 cin=u_csamul_rca32_fa9_17_or0 fa_xor1=u_csamul_rca32_fa9_18_xor1 fa_or0=u_csamul_rca32_fa9_18_or0
.subckt and_gate a=a[10] b=b[18] out=u_csamul_rca32_and10_18
.subckt fa a=u_csamul_rca32_and10_18 b=u_csamul_rca32_fa11_17_xor1 cin=u_csamul_rca32_fa10_17_or0 fa_xor1=u_csamul_rca32_fa10_18_xor1 fa_or0=u_csamul_rca32_fa10_18_or0
.subckt and_gate a=a[11] b=b[18] out=u_csamul_rca32_and11_18
.subckt fa a=u_csamul_rca32_and11_18 b=u_csamul_rca32_fa12_17_xor1 cin=u_csamul_rca32_fa11_17_or0 fa_xor1=u_csamul_rca32_fa11_18_xor1 fa_or0=u_csamul_rca32_fa11_18_or0
.subckt and_gate a=a[12] b=b[18] out=u_csamul_rca32_and12_18
.subckt fa a=u_csamul_rca32_and12_18 b=u_csamul_rca32_fa13_17_xor1 cin=u_csamul_rca32_fa12_17_or0 fa_xor1=u_csamul_rca32_fa12_18_xor1 fa_or0=u_csamul_rca32_fa12_18_or0
.subckt and_gate a=a[13] b=b[18] out=u_csamul_rca32_and13_18
.subckt fa a=u_csamul_rca32_and13_18 b=u_csamul_rca32_fa14_17_xor1 cin=u_csamul_rca32_fa13_17_or0 fa_xor1=u_csamul_rca32_fa13_18_xor1 fa_or0=u_csamul_rca32_fa13_18_or0
.subckt and_gate a=a[14] b=b[18] out=u_csamul_rca32_and14_18
.subckt fa a=u_csamul_rca32_and14_18 b=u_csamul_rca32_fa15_17_xor1 cin=u_csamul_rca32_fa14_17_or0 fa_xor1=u_csamul_rca32_fa14_18_xor1 fa_or0=u_csamul_rca32_fa14_18_or0
.subckt and_gate a=a[15] b=b[18] out=u_csamul_rca32_and15_18
.subckt fa a=u_csamul_rca32_and15_18 b=u_csamul_rca32_fa16_17_xor1 cin=u_csamul_rca32_fa15_17_or0 fa_xor1=u_csamul_rca32_fa15_18_xor1 fa_or0=u_csamul_rca32_fa15_18_or0
.subckt and_gate a=a[16] b=b[18] out=u_csamul_rca32_and16_18
.subckt fa a=u_csamul_rca32_and16_18 b=u_csamul_rca32_fa17_17_xor1 cin=u_csamul_rca32_fa16_17_or0 fa_xor1=u_csamul_rca32_fa16_18_xor1 fa_or0=u_csamul_rca32_fa16_18_or0
.subckt and_gate a=a[17] b=b[18] out=u_csamul_rca32_and17_18
.subckt fa a=u_csamul_rca32_and17_18 b=u_csamul_rca32_fa18_17_xor1 cin=u_csamul_rca32_fa17_17_or0 fa_xor1=u_csamul_rca32_fa17_18_xor1 fa_or0=u_csamul_rca32_fa17_18_or0
.subckt and_gate a=a[18] b=b[18] out=u_csamul_rca32_and18_18
.subckt fa a=u_csamul_rca32_and18_18 b=u_csamul_rca32_fa19_17_xor1 cin=u_csamul_rca32_fa18_17_or0 fa_xor1=u_csamul_rca32_fa18_18_xor1 fa_or0=u_csamul_rca32_fa18_18_or0
.subckt and_gate a=a[19] b=b[18] out=u_csamul_rca32_and19_18
.subckt fa a=u_csamul_rca32_and19_18 b=u_csamul_rca32_fa20_17_xor1 cin=u_csamul_rca32_fa19_17_or0 fa_xor1=u_csamul_rca32_fa19_18_xor1 fa_or0=u_csamul_rca32_fa19_18_or0
.subckt and_gate a=a[20] b=b[18] out=u_csamul_rca32_and20_18
.subckt fa a=u_csamul_rca32_and20_18 b=u_csamul_rca32_fa21_17_xor1 cin=u_csamul_rca32_fa20_17_or0 fa_xor1=u_csamul_rca32_fa20_18_xor1 fa_or0=u_csamul_rca32_fa20_18_or0
.subckt and_gate a=a[21] b=b[18] out=u_csamul_rca32_and21_18
.subckt fa a=u_csamul_rca32_and21_18 b=u_csamul_rca32_fa22_17_xor1 cin=u_csamul_rca32_fa21_17_or0 fa_xor1=u_csamul_rca32_fa21_18_xor1 fa_or0=u_csamul_rca32_fa21_18_or0
.subckt and_gate a=a[22] b=b[18] out=u_csamul_rca32_and22_18
.subckt fa a=u_csamul_rca32_and22_18 b=u_csamul_rca32_fa23_17_xor1 cin=u_csamul_rca32_fa22_17_or0 fa_xor1=u_csamul_rca32_fa22_18_xor1 fa_or0=u_csamul_rca32_fa22_18_or0
.subckt and_gate a=a[23] b=b[18] out=u_csamul_rca32_and23_18
.subckt fa a=u_csamul_rca32_and23_18 b=u_csamul_rca32_fa24_17_xor1 cin=u_csamul_rca32_fa23_17_or0 fa_xor1=u_csamul_rca32_fa23_18_xor1 fa_or0=u_csamul_rca32_fa23_18_or0
.subckt and_gate a=a[24] b=b[18] out=u_csamul_rca32_and24_18
.subckt fa a=u_csamul_rca32_and24_18 b=u_csamul_rca32_fa25_17_xor1 cin=u_csamul_rca32_fa24_17_or0 fa_xor1=u_csamul_rca32_fa24_18_xor1 fa_or0=u_csamul_rca32_fa24_18_or0
.subckt and_gate a=a[25] b=b[18] out=u_csamul_rca32_and25_18
.subckt fa a=u_csamul_rca32_and25_18 b=u_csamul_rca32_fa26_17_xor1 cin=u_csamul_rca32_fa25_17_or0 fa_xor1=u_csamul_rca32_fa25_18_xor1 fa_or0=u_csamul_rca32_fa25_18_or0
.subckt and_gate a=a[26] b=b[18] out=u_csamul_rca32_and26_18
.subckt fa a=u_csamul_rca32_and26_18 b=u_csamul_rca32_fa27_17_xor1 cin=u_csamul_rca32_fa26_17_or0 fa_xor1=u_csamul_rca32_fa26_18_xor1 fa_or0=u_csamul_rca32_fa26_18_or0
.subckt and_gate a=a[27] b=b[18] out=u_csamul_rca32_and27_18
.subckt fa a=u_csamul_rca32_and27_18 b=u_csamul_rca32_fa28_17_xor1 cin=u_csamul_rca32_fa27_17_or0 fa_xor1=u_csamul_rca32_fa27_18_xor1 fa_or0=u_csamul_rca32_fa27_18_or0
.subckt and_gate a=a[28] b=b[18] out=u_csamul_rca32_and28_18
.subckt fa a=u_csamul_rca32_and28_18 b=u_csamul_rca32_fa29_17_xor1 cin=u_csamul_rca32_fa28_17_or0 fa_xor1=u_csamul_rca32_fa28_18_xor1 fa_or0=u_csamul_rca32_fa28_18_or0
.subckt and_gate a=a[29] b=b[18] out=u_csamul_rca32_and29_18
.subckt fa a=u_csamul_rca32_and29_18 b=u_csamul_rca32_fa30_17_xor1 cin=u_csamul_rca32_fa29_17_or0 fa_xor1=u_csamul_rca32_fa29_18_xor1 fa_or0=u_csamul_rca32_fa29_18_or0
.subckt and_gate a=a[30] b=b[18] out=u_csamul_rca32_and30_18
.subckt fa a=u_csamul_rca32_and30_18 b=u_csamul_rca32_and31_17 cin=u_csamul_rca32_fa30_17_or0 fa_xor1=u_csamul_rca32_fa30_18_xor1 fa_or0=u_csamul_rca32_fa30_18_or0
.subckt and_gate a=a[31] b=b[18] out=u_csamul_rca32_and31_18
.subckt and_gate a=a[0] b=b[19] out=u_csamul_rca32_and0_19
.subckt fa a=u_csamul_rca32_and0_19 b=u_csamul_rca32_fa1_18_xor1 cin=u_csamul_rca32_fa0_18_or0 fa_xor1=u_csamul_rca32_fa0_19_xor1 fa_or0=u_csamul_rca32_fa0_19_or0
.subckt and_gate a=a[1] b=b[19] out=u_csamul_rca32_and1_19
.subckt fa a=u_csamul_rca32_and1_19 b=u_csamul_rca32_fa2_18_xor1 cin=u_csamul_rca32_fa1_18_or0 fa_xor1=u_csamul_rca32_fa1_19_xor1 fa_or0=u_csamul_rca32_fa1_19_or0
.subckt and_gate a=a[2] b=b[19] out=u_csamul_rca32_and2_19
.subckt fa a=u_csamul_rca32_and2_19 b=u_csamul_rca32_fa3_18_xor1 cin=u_csamul_rca32_fa2_18_or0 fa_xor1=u_csamul_rca32_fa2_19_xor1 fa_or0=u_csamul_rca32_fa2_19_or0
.subckt and_gate a=a[3] b=b[19] out=u_csamul_rca32_and3_19
.subckt fa a=u_csamul_rca32_and3_19 b=u_csamul_rca32_fa4_18_xor1 cin=u_csamul_rca32_fa3_18_or0 fa_xor1=u_csamul_rca32_fa3_19_xor1 fa_or0=u_csamul_rca32_fa3_19_or0
.subckt and_gate a=a[4] b=b[19] out=u_csamul_rca32_and4_19
.subckt fa a=u_csamul_rca32_and4_19 b=u_csamul_rca32_fa5_18_xor1 cin=u_csamul_rca32_fa4_18_or0 fa_xor1=u_csamul_rca32_fa4_19_xor1 fa_or0=u_csamul_rca32_fa4_19_or0
.subckt and_gate a=a[5] b=b[19] out=u_csamul_rca32_and5_19
.subckt fa a=u_csamul_rca32_and5_19 b=u_csamul_rca32_fa6_18_xor1 cin=u_csamul_rca32_fa5_18_or0 fa_xor1=u_csamul_rca32_fa5_19_xor1 fa_or0=u_csamul_rca32_fa5_19_or0
.subckt and_gate a=a[6] b=b[19] out=u_csamul_rca32_and6_19
.subckt fa a=u_csamul_rca32_and6_19 b=u_csamul_rca32_fa7_18_xor1 cin=u_csamul_rca32_fa6_18_or0 fa_xor1=u_csamul_rca32_fa6_19_xor1 fa_or0=u_csamul_rca32_fa6_19_or0
.subckt and_gate a=a[7] b=b[19] out=u_csamul_rca32_and7_19
.subckt fa a=u_csamul_rca32_and7_19 b=u_csamul_rca32_fa8_18_xor1 cin=u_csamul_rca32_fa7_18_or0 fa_xor1=u_csamul_rca32_fa7_19_xor1 fa_or0=u_csamul_rca32_fa7_19_or0
.subckt and_gate a=a[8] b=b[19] out=u_csamul_rca32_and8_19
.subckt fa a=u_csamul_rca32_and8_19 b=u_csamul_rca32_fa9_18_xor1 cin=u_csamul_rca32_fa8_18_or0 fa_xor1=u_csamul_rca32_fa8_19_xor1 fa_or0=u_csamul_rca32_fa8_19_or0
.subckt and_gate a=a[9] b=b[19] out=u_csamul_rca32_and9_19
.subckt fa a=u_csamul_rca32_and9_19 b=u_csamul_rca32_fa10_18_xor1 cin=u_csamul_rca32_fa9_18_or0 fa_xor1=u_csamul_rca32_fa9_19_xor1 fa_or0=u_csamul_rca32_fa9_19_or0
.subckt and_gate a=a[10] b=b[19] out=u_csamul_rca32_and10_19
.subckt fa a=u_csamul_rca32_and10_19 b=u_csamul_rca32_fa11_18_xor1 cin=u_csamul_rca32_fa10_18_or0 fa_xor1=u_csamul_rca32_fa10_19_xor1 fa_or0=u_csamul_rca32_fa10_19_or0
.subckt and_gate a=a[11] b=b[19] out=u_csamul_rca32_and11_19
.subckt fa a=u_csamul_rca32_and11_19 b=u_csamul_rca32_fa12_18_xor1 cin=u_csamul_rca32_fa11_18_or0 fa_xor1=u_csamul_rca32_fa11_19_xor1 fa_or0=u_csamul_rca32_fa11_19_or0
.subckt and_gate a=a[12] b=b[19] out=u_csamul_rca32_and12_19
.subckt fa a=u_csamul_rca32_and12_19 b=u_csamul_rca32_fa13_18_xor1 cin=u_csamul_rca32_fa12_18_or0 fa_xor1=u_csamul_rca32_fa12_19_xor1 fa_or0=u_csamul_rca32_fa12_19_or0
.subckt and_gate a=a[13] b=b[19] out=u_csamul_rca32_and13_19
.subckt fa a=u_csamul_rca32_and13_19 b=u_csamul_rca32_fa14_18_xor1 cin=u_csamul_rca32_fa13_18_or0 fa_xor1=u_csamul_rca32_fa13_19_xor1 fa_or0=u_csamul_rca32_fa13_19_or0
.subckt and_gate a=a[14] b=b[19] out=u_csamul_rca32_and14_19
.subckt fa a=u_csamul_rca32_and14_19 b=u_csamul_rca32_fa15_18_xor1 cin=u_csamul_rca32_fa14_18_or0 fa_xor1=u_csamul_rca32_fa14_19_xor1 fa_or0=u_csamul_rca32_fa14_19_or0
.subckt and_gate a=a[15] b=b[19] out=u_csamul_rca32_and15_19
.subckt fa a=u_csamul_rca32_and15_19 b=u_csamul_rca32_fa16_18_xor1 cin=u_csamul_rca32_fa15_18_or0 fa_xor1=u_csamul_rca32_fa15_19_xor1 fa_or0=u_csamul_rca32_fa15_19_or0
.subckt and_gate a=a[16] b=b[19] out=u_csamul_rca32_and16_19
.subckt fa a=u_csamul_rca32_and16_19 b=u_csamul_rca32_fa17_18_xor1 cin=u_csamul_rca32_fa16_18_or0 fa_xor1=u_csamul_rca32_fa16_19_xor1 fa_or0=u_csamul_rca32_fa16_19_or0
.subckt and_gate a=a[17] b=b[19] out=u_csamul_rca32_and17_19
.subckt fa a=u_csamul_rca32_and17_19 b=u_csamul_rca32_fa18_18_xor1 cin=u_csamul_rca32_fa17_18_or0 fa_xor1=u_csamul_rca32_fa17_19_xor1 fa_or0=u_csamul_rca32_fa17_19_or0
.subckt and_gate a=a[18] b=b[19] out=u_csamul_rca32_and18_19
.subckt fa a=u_csamul_rca32_and18_19 b=u_csamul_rca32_fa19_18_xor1 cin=u_csamul_rca32_fa18_18_or0 fa_xor1=u_csamul_rca32_fa18_19_xor1 fa_or0=u_csamul_rca32_fa18_19_or0
.subckt and_gate a=a[19] b=b[19] out=u_csamul_rca32_and19_19
.subckt fa a=u_csamul_rca32_and19_19 b=u_csamul_rca32_fa20_18_xor1 cin=u_csamul_rca32_fa19_18_or0 fa_xor1=u_csamul_rca32_fa19_19_xor1 fa_or0=u_csamul_rca32_fa19_19_or0
.subckt and_gate a=a[20] b=b[19] out=u_csamul_rca32_and20_19
.subckt fa a=u_csamul_rca32_and20_19 b=u_csamul_rca32_fa21_18_xor1 cin=u_csamul_rca32_fa20_18_or0 fa_xor1=u_csamul_rca32_fa20_19_xor1 fa_or0=u_csamul_rca32_fa20_19_or0
.subckt and_gate a=a[21] b=b[19] out=u_csamul_rca32_and21_19
.subckt fa a=u_csamul_rca32_and21_19 b=u_csamul_rca32_fa22_18_xor1 cin=u_csamul_rca32_fa21_18_or0 fa_xor1=u_csamul_rca32_fa21_19_xor1 fa_or0=u_csamul_rca32_fa21_19_or0
.subckt and_gate a=a[22] b=b[19] out=u_csamul_rca32_and22_19
.subckt fa a=u_csamul_rca32_and22_19 b=u_csamul_rca32_fa23_18_xor1 cin=u_csamul_rca32_fa22_18_or0 fa_xor1=u_csamul_rca32_fa22_19_xor1 fa_or0=u_csamul_rca32_fa22_19_or0
.subckt and_gate a=a[23] b=b[19] out=u_csamul_rca32_and23_19
.subckt fa a=u_csamul_rca32_and23_19 b=u_csamul_rca32_fa24_18_xor1 cin=u_csamul_rca32_fa23_18_or0 fa_xor1=u_csamul_rca32_fa23_19_xor1 fa_or0=u_csamul_rca32_fa23_19_or0
.subckt and_gate a=a[24] b=b[19] out=u_csamul_rca32_and24_19
.subckt fa a=u_csamul_rca32_and24_19 b=u_csamul_rca32_fa25_18_xor1 cin=u_csamul_rca32_fa24_18_or0 fa_xor1=u_csamul_rca32_fa24_19_xor1 fa_or0=u_csamul_rca32_fa24_19_or0
.subckt and_gate a=a[25] b=b[19] out=u_csamul_rca32_and25_19
.subckt fa a=u_csamul_rca32_and25_19 b=u_csamul_rca32_fa26_18_xor1 cin=u_csamul_rca32_fa25_18_or0 fa_xor1=u_csamul_rca32_fa25_19_xor1 fa_or0=u_csamul_rca32_fa25_19_or0
.subckt and_gate a=a[26] b=b[19] out=u_csamul_rca32_and26_19
.subckt fa a=u_csamul_rca32_and26_19 b=u_csamul_rca32_fa27_18_xor1 cin=u_csamul_rca32_fa26_18_or0 fa_xor1=u_csamul_rca32_fa26_19_xor1 fa_or0=u_csamul_rca32_fa26_19_or0
.subckt and_gate a=a[27] b=b[19] out=u_csamul_rca32_and27_19
.subckt fa a=u_csamul_rca32_and27_19 b=u_csamul_rca32_fa28_18_xor1 cin=u_csamul_rca32_fa27_18_or0 fa_xor1=u_csamul_rca32_fa27_19_xor1 fa_or0=u_csamul_rca32_fa27_19_or0
.subckt and_gate a=a[28] b=b[19] out=u_csamul_rca32_and28_19
.subckt fa a=u_csamul_rca32_and28_19 b=u_csamul_rca32_fa29_18_xor1 cin=u_csamul_rca32_fa28_18_or0 fa_xor1=u_csamul_rca32_fa28_19_xor1 fa_or0=u_csamul_rca32_fa28_19_or0
.subckt and_gate a=a[29] b=b[19] out=u_csamul_rca32_and29_19
.subckt fa a=u_csamul_rca32_and29_19 b=u_csamul_rca32_fa30_18_xor1 cin=u_csamul_rca32_fa29_18_or0 fa_xor1=u_csamul_rca32_fa29_19_xor1 fa_or0=u_csamul_rca32_fa29_19_or0
.subckt and_gate a=a[30] b=b[19] out=u_csamul_rca32_and30_19
.subckt fa a=u_csamul_rca32_and30_19 b=u_csamul_rca32_and31_18 cin=u_csamul_rca32_fa30_18_or0 fa_xor1=u_csamul_rca32_fa30_19_xor1 fa_or0=u_csamul_rca32_fa30_19_or0
.subckt and_gate a=a[31] b=b[19] out=u_csamul_rca32_and31_19
.subckt and_gate a=a[0] b=b[20] out=u_csamul_rca32_and0_20
.subckt fa a=u_csamul_rca32_and0_20 b=u_csamul_rca32_fa1_19_xor1 cin=u_csamul_rca32_fa0_19_or0 fa_xor1=u_csamul_rca32_fa0_20_xor1 fa_or0=u_csamul_rca32_fa0_20_or0
.subckt and_gate a=a[1] b=b[20] out=u_csamul_rca32_and1_20
.subckt fa a=u_csamul_rca32_and1_20 b=u_csamul_rca32_fa2_19_xor1 cin=u_csamul_rca32_fa1_19_or0 fa_xor1=u_csamul_rca32_fa1_20_xor1 fa_or0=u_csamul_rca32_fa1_20_or0
.subckt and_gate a=a[2] b=b[20] out=u_csamul_rca32_and2_20
.subckt fa a=u_csamul_rca32_and2_20 b=u_csamul_rca32_fa3_19_xor1 cin=u_csamul_rca32_fa2_19_or0 fa_xor1=u_csamul_rca32_fa2_20_xor1 fa_or0=u_csamul_rca32_fa2_20_or0
.subckt and_gate a=a[3] b=b[20] out=u_csamul_rca32_and3_20
.subckt fa a=u_csamul_rca32_and3_20 b=u_csamul_rca32_fa4_19_xor1 cin=u_csamul_rca32_fa3_19_or0 fa_xor1=u_csamul_rca32_fa3_20_xor1 fa_or0=u_csamul_rca32_fa3_20_or0
.subckt and_gate a=a[4] b=b[20] out=u_csamul_rca32_and4_20
.subckt fa a=u_csamul_rca32_and4_20 b=u_csamul_rca32_fa5_19_xor1 cin=u_csamul_rca32_fa4_19_or0 fa_xor1=u_csamul_rca32_fa4_20_xor1 fa_or0=u_csamul_rca32_fa4_20_or0
.subckt and_gate a=a[5] b=b[20] out=u_csamul_rca32_and5_20
.subckt fa a=u_csamul_rca32_and5_20 b=u_csamul_rca32_fa6_19_xor1 cin=u_csamul_rca32_fa5_19_or0 fa_xor1=u_csamul_rca32_fa5_20_xor1 fa_or0=u_csamul_rca32_fa5_20_or0
.subckt and_gate a=a[6] b=b[20] out=u_csamul_rca32_and6_20
.subckt fa a=u_csamul_rca32_and6_20 b=u_csamul_rca32_fa7_19_xor1 cin=u_csamul_rca32_fa6_19_or0 fa_xor1=u_csamul_rca32_fa6_20_xor1 fa_or0=u_csamul_rca32_fa6_20_or0
.subckt and_gate a=a[7] b=b[20] out=u_csamul_rca32_and7_20
.subckt fa a=u_csamul_rca32_and7_20 b=u_csamul_rca32_fa8_19_xor1 cin=u_csamul_rca32_fa7_19_or0 fa_xor1=u_csamul_rca32_fa7_20_xor1 fa_or0=u_csamul_rca32_fa7_20_or0
.subckt and_gate a=a[8] b=b[20] out=u_csamul_rca32_and8_20
.subckt fa a=u_csamul_rca32_and8_20 b=u_csamul_rca32_fa9_19_xor1 cin=u_csamul_rca32_fa8_19_or0 fa_xor1=u_csamul_rca32_fa8_20_xor1 fa_or0=u_csamul_rca32_fa8_20_or0
.subckt and_gate a=a[9] b=b[20] out=u_csamul_rca32_and9_20
.subckt fa a=u_csamul_rca32_and9_20 b=u_csamul_rca32_fa10_19_xor1 cin=u_csamul_rca32_fa9_19_or0 fa_xor1=u_csamul_rca32_fa9_20_xor1 fa_or0=u_csamul_rca32_fa9_20_or0
.subckt and_gate a=a[10] b=b[20] out=u_csamul_rca32_and10_20
.subckt fa a=u_csamul_rca32_and10_20 b=u_csamul_rca32_fa11_19_xor1 cin=u_csamul_rca32_fa10_19_or0 fa_xor1=u_csamul_rca32_fa10_20_xor1 fa_or0=u_csamul_rca32_fa10_20_or0
.subckt and_gate a=a[11] b=b[20] out=u_csamul_rca32_and11_20
.subckt fa a=u_csamul_rca32_and11_20 b=u_csamul_rca32_fa12_19_xor1 cin=u_csamul_rca32_fa11_19_or0 fa_xor1=u_csamul_rca32_fa11_20_xor1 fa_or0=u_csamul_rca32_fa11_20_or0
.subckt and_gate a=a[12] b=b[20] out=u_csamul_rca32_and12_20
.subckt fa a=u_csamul_rca32_and12_20 b=u_csamul_rca32_fa13_19_xor1 cin=u_csamul_rca32_fa12_19_or0 fa_xor1=u_csamul_rca32_fa12_20_xor1 fa_or0=u_csamul_rca32_fa12_20_or0
.subckt and_gate a=a[13] b=b[20] out=u_csamul_rca32_and13_20
.subckt fa a=u_csamul_rca32_and13_20 b=u_csamul_rca32_fa14_19_xor1 cin=u_csamul_rca32_fa13_19_or0 fa_xor1=u_csamul_rca32_fa13_20_xor1 fa_or0=u_csamul_rca32_fa13_20_or0
.subckt and_gate a=a[14] b=b[20] out=u_csamul_rca32_and14_20
.subckt fa a=u_csamul_rca32_and14_20 b=u_csamul_rca32_fa15_19_xor1 cin=u_csamul_rca32_fa14_19_or0 fa_xor1=u_csamul_rca32_fa14_20_xor1 fa_or0=u_csamul_rca32_fa14_20_or0
.subckt and_gate a=a[15] b=b[20] out=u_csamul_rca32_and15_20
.subckt fa a=u_csamul_rca32_and15_20 b=u_csamul_rca32_fa16_19_xor1 cin=u_csamul_rca32_fa15_19_or0 fa_xor1=u_csamul_rca32_fa15_20_xor1 fa_or0=u_csamul_rca32_fa15_20_or0
.subckt and_gate a=a[16] b=b[20] out=u_csamul_rca32_and16_20
.subckt fa a=u_csamul_rca32_and16_20 b=u_csamul_rca32_fa17_19_xor1 cin=u_csamul_rca32_fa16_19_or0 fa_xor1=u_csamul_rca32_fa16_20_xor1 fa_or0=u_csamul_rca32_fa16_20_or0
.subckt and_gate a=a[17] b=b[20] out=u_csamul_rca32_and17_20
.subckt fa a=u_csamul_rca32_and17_20 b=u_csamul_rca32_fa18_19_xor1 cin=u_csamul_rca32_fa17_19_or0 fa_xor1=u_csamul_rca32_fa17_20_xor1 fa_or0=u_csamul_rca32_fa17_20_or0
.subckt and_gate a=a[18] b=b[20] out=u_csamul_rca32_and18_20
.subckt fa a=u_csamul_rca32_and18_20 b=u_csamul_rca32_fa19_19_xor1 cin=u_csamul_rca32_fa18_19_or0 fa_xor1=u_csamul_rca32_fa18_20_xor1 fa_or0=u_csamul_rca32_fa18_20_or0
.subckt and_gate a=a[19] b=b[20] out=u_csamul_rca32_and19_20
.subckt fa a=u_csamul_rca32_and19_20 b=u_csamul_rca32_fa20_19_xor1 cin=u_csamul_rca32_fa19_19_or0 fa_xor1=u_csamul_rca32_fa19_20_xor1 fa_or0=u_csamul_rca32_fa19_20_or0
.subckt and_gate a=a[20] b=b[20] out=u_csamul_rca32_and20_20
.subckt fa a=u_csamul_rca32_and20_20 b=u_csamul_rca32_fa21_19_xor1 cin=u_csamul_rca32_fa20_19_or0 fa_xor1=u_csamul_rca32_fa20_20_xor1 fa_or0=u_csamul_rca32_fa20_20_or0
.subckt and_gate a=a[21] b=b[20] out=u_csamul_rca32_and21_20
.subckt fa a=u_csamul_rca32_and21_20 b=u_csamul_rca32_fa22_19_xor1 cin=u_csamul_rca32_fa21_19_or0 fa_xor1=u_csamul_rca32_fa21_20_xor1 fa_or0=u_csamul_rca32_fa21_20_or0
.subckt and_gate a=a[22] b=b[20] out=u_csamul_rca32_and22_20
.subckt fa a=u_csamul_rca32_and22_20 b=u_csamul_rca32_fa23_19_xor1 cin=u_csamul_rca32_fa22_19_or0 fa_xor1=u_csamul_rca32_fa22_20_xor1 fa_or0=u_csamul_rca32_fa22_20_or0
.subckt and_gate a=a[23] b=b[20] out=u_csamul_rca32_and23_20
.subckt fa a=u_csamul_rca32_and23_20 b=u_csamul_rca32_fa24_19_xor1 cin=u_csamul_rca32_fa23_19_or0 fa_xor1=u_csamul_rca32_fa23_20_xor1 fa_or0=u_csamul_rca32_fa23_20_or0
.subckt and_gate a=a[24] b=b[20] out=u_csamul_rca32_and24_20
.subckt fa a=u_csamul_rca32_and24_20 b=u_csamul_rca32_fa25_19_xor1 cin=u_csamul_rca32_fa24_19_or0 fa_xor1=u_csamul_rca32_fa24_20_xor1 fa_or0=u_csamul_rca32_fa24_20_or0
.subckt and_gate a=a[25] b=b[20] out=u_csamul_rca32_and25_20
.subckt fa a=u_csamul_rca32_and25_20 b=u_csamul_rca32_fa26_19_xor1 cin=u_csamul_rca32_fa25_19_or0 fa_xor1=u_csamul_rca32_fa25_20_xor1 fa_or0=u_csamul_rca32_fa25_20_or0
.subckt and_gate a=a[26] b=b[20] out=u_csamul_rca32_and26_20
.subckt fa a=u_csamul_rca32_and26_20 b=u_csamul_rca32_fa27_19_xor1 cin=u_csamul_rca32_fa26_19_or0 fa_xor1=u_csamul_rca32_fa26_20_xor1 fa_or0=u_csamul_rca32_fa26_20_or0
.subckt and_gate a=a[27] b=b[20] out=u_csamul_rca32_and27_20
.subckt fa a=u_csamul_rca32_and27_20 b=u_csamul_rca32_fa28_19_xor1 cin=u_csamul_rca32_fa27_19_or0 fa_xor1=u_csamul_rca32_fa27_20_xor1 fa_or0=u_csamul_rca32_fa27_20_or0
.subckt and_gate a=a[28] b=b[20] out=u_csamul_rca32_and28_20
.subckt fa a=u_csamul_rca32_and28_20 b=u_csamul_rca32_fa29_19_xor1 cin=u_csamul_rca32_fa28_19_or0 fa_xor1=u_csamul_rca32_fa28_20_xor1 fa_or0=u_csamul_rca32_fa28_20_or0
.subckt and_gate a=a[29] b=b[20] out=u_csamul_rca32_and29_20
.subckt fa a=u_csamul_rca32_and29_20 b=u_csamul_rca32_fa30_19_xor1 cin=u_csamul_rca32_fa29_19_or0 fa_xor1=u_csamul_rca32_fa29_20_xor1 fa_or0=u_csamul_rca32_fa29_20_or0
.subckt and_gate a=a[30] b=b[20] out=u_csamul_rca32_and30_20
.subckt fa a=u_csamul_rca32_and30_20 b=u_csamul_rca32_and31_19 cin=u_csamul_rca32_fa30_19_or0 fa_xor1=u_csamul_rca32_fa30_20_xor1 fa_or0=u_csamul_rca32_fa30_20_or0
.subckt and_gate a=a[31] b=b[20] out=u_csamul_rca32_and31_20
.subckt and_gate a=a[0] b=b[21] out=u_csamul_rca32_and0_21
.subckt fa a=u_csamul_rca32_and0_21 b=u_csamul_rca32_fa1_20_xor1 cin=u_csamul_rca32_fa0_20_or0 fa_xor1=u_csamul_rca32_fa0_21_xor1 fa_or0=u_csamul_rca32_fa0_21_or0
.subckt and_gate a=a[1] b=b[21] out=u_csamul_rca32_and1_21
.subckt fa a=u_csamul_rca32_and1_21 b=u_csamul_rca32_fa2_20_xor1 cin=u_csamul_rca32_fa1_20_or0 fa_xor1=u_csamul_rca32_fa1_21_xor1 fa_or0=u_csamul_rca32_fa1_21_or0
.subckt and_gate a=a[2] b=b[21] out=u_csamul_rca32_and2_21
.subckt fa a=u_csamul_rca32_and2_21 b=u_csamul_rca32_fa3_20_xor1 cin=u_csamul_rca32_fa2_20_or0 fa_xor1=u_csamul_rca32_fa2_21_xor1 fa_or0=u_csamul_rca32_fa2_21_or0
.subckt and_gate a=a[3] b=b[21] out=u_csamul_rca32_and3_21
.subckt fa a=u_csamul_rca32_and3_21 b=u_csamul_rca32_fa4_20_xor1 cin=u_csamul_rca32_fa3_20_or0 fa_xor1=u_csamul_rca32_fa3_21_xor1 fa_or0=u_csamul_rca32_fa3_21_or0
.subckt and_gate a=a[4] b=b[21] out=u_csamul_rca32_and4_21
.subckt fa a=u_csamul_rca32_and4_21 b=u_csamul_rca32_fa5_20_xor1 cin=u_csamul_rca32_fa4_20_or0 fa_xor1=u_csamul_rca32_fa4_21_xor1 fa_or0=u_csamul_rca32_fa4_21_or0
.subckt and_gate a=a[5] b=b[21] out=u_csamul_rca32_and5_21
.subckt fa a=u_csamul_rca32_and5_21 b=u_csamul_rca32_fa6_20_xor1 cin=u_csamul_rca32_fa5_20_or0 fa_xor1=u_csamul_rca32_fa5_21_xor1 fa_or0=u_csamul_rca32_fa5_21_or0
.subckt and_gate a=a[6] b=b[21] out=u_csamul_rca32_and6_21
.subckt fa a=u_csamul_rca32_and6_21 b=u_csamul_rca32_fa7_20_xor1 cin=u_csamul_rca32_fa6_20_or0 fa_xor1=u_csamul_rca32_fa6_21_xor1 fa_or0=u_csamul_rca32_fa6_21_or0
.subckt and_gate a=a[7] b=b[21] out=u_csamul_rca32_and7_21
.subckt fa a=u_csamul_rca32_and7_21 b=u_csamul_rca32_fa8_20_xor1 cin=u_csamul_rca32_fa7_20_or0 fa_xor1=u_csamul_rca32_fa7_21_xor1 fa_or0=u_csamul_rca32_fa7_21_or0
.subckt and_gate a=a[8] b=b[21] out=u_csamul_rca32_and8_21
.subckt fa a=u_csamul_rca32_and8_21 b=u_csamul_rca32_fa9_20_xor1 cin=u_csamul_rca32_fa8_20_or0 fa_xor1=u_csamul_rca32_fa8_21_xor1 fa_or0=u_csamul_rca32_fa8_21_or0
.subckt and_gate a=a[9] b=b[21] out=u_csamul_rca32_and9_21
.subckt fa a=u_csamul_rca32_and9_21 b=u_csamul_rca32_fa10_20_xor1 cin=u_csamul_rca32_fa9_20_or0 fa_xor1=u_csamul_rca32_fa9_21_xor1 fa_or0=u_csamul_rca32_fa9_21_or0
.subckt and_gate a=a[10] b=b[21] out=u_csamul_rca32_and10_21
.subckt fa a=u_csamul_rca32_and10_21 b=u_csamul_rca32_fa11_20_xor1 cin=u_csamul_rca32_fa10_20_or0 fa_xor1=u_csamul_rca32_fa10_21_xor1 fa_or0=u_csamul_rca32_fa10_21_or0
.subckt and_gate a=a[11] b=b[21] out=u_csamul_rca32_and11_21
.subckt fa a=u_csamul_rca32_and11_21 b=u_csamul_rca32_fa12_20_xor1 cin=u_csamul_rca32_fa11_20_or0 fa_xor1=u_csamul_rca32_fa11_21_xor1 fa_or0=u_csamul_rca32_fa11_21_or0
.subckt and_gate a=a[12] b=b[21] out=u_csamul_rca32_and12_21
.subckt fa a=u_csamul_rca32_and12_21 b=u_csamul_rca32_fa13_20_xor1 cin=u_csamul_rca32_fa12_20_or0 fa_xor1=u_csamul_rca32_fa12_21_xor1 fa_or0=u_csamul_rca32_fa12_21_or0
.subckt and_gate a=a[13] b=b[21] out=u_csamul_rca32_and13_21
.subckt fa a=u_csamul_rca32_and13_21 b=u_csamul_rca32_fa14_20_xor1 cin=u_csamul_rca32_fa13_20_or0 fa_xor1=u_csamul_rca32_fa13_21_xor1 fa_or0=u_csamul_rca32_fa13_21_or0
.subckt and_gate a=a[14] b=b[21] out=u_csamul_rca32_and14_21
.subckt fa a=u_csamul_rca32_and14_21 b=u_csamul_rca32_fa15_20_xor1 cin=u_csamul_rca32_fa14_20_or0 fa_xor1=u_csamul_rca32_fa14_21_xor1 fa_or0=u_csamul_rca32_fa14_21_or0
.subckt and_gate a=a[15] b=b[21] out=u_csamul_rca32_and15_21
.subckt fa a=u_csamul_rca32_and15_21 b=u_csamul_rca32_fa16_20_xor1 cin=u_csamul_rca32_fa15_20_or0 fa_xor1=u_csamul_rca32_fa15_21_xor1 fa_or0=u_csamul_rca32_fa15_21_or0
.subckt and_gate a=a[16] b=b[21] out=u_csamul_rca32_and16_21
.subckt fa a=u_csamul_rca32_and16_21 b=u_csamul_rca32_fa17_20_xor1 cin=u_csamul_rca32_fa16_20_or0 fa_xor1=u_csamul_rca32_fa16_21_xor1 fa_or0=u_csamul_rca32_fa16_21_or0
.subckt and_gate a=a[17] b=b[21] out=u_csamul_rca32_and17_21
.subckt fa a=u_csamul_rca32_and17_21 b=u_csamul_rca32_fa18_20_xor1 cin=u_csamul_rca32_fa17_20_or0 fa_xor1=u_csamul_rca32_fa17_21_xor1 fa_or0=u_csamul_rca32_fa17_21_or0
.subckt and_gate a=a[18] b=b[21] out=u_csamul_rca32_and18_21
.subckt fa a=u_csamul_rca32_and18_21 b=u_csamul_rca32_fa19_20_xor1 cin=u_csamul_rca32_fa18_20_or0 fa_xor1=u_csamul_rca32_fa18_21_xor1 fa_or0=u_csamul_rca32_fa18_21_or0
.subckt and_gate a=a[19] b=b[21] out=u_csamul_rca32_and19_21
.subckt fa a=u_csamul_rca32_and19_21 b=u_csamul_rca32_fa20_20_xor1 cin=u_csamul_rca32_fa19_20_or0 fa_xor1=u_csamul_rca32_fa19_21_xor1 fa_or0=u_csamul_rca32_fa19_21_or0
.subckt and_gate a=a[20] b=b[21] out=u_csamul_rca32_and20_21
.subckt fa a=u_csamul_rca32_and20_21 b=u_csamul_rca32_fa21_20_xor1 cin=u_csamul_rca32_fa20_20_or0 fa_xor1=u_csamul_rca32_fa20_21_xor1 fa_or0=u_csamul_rca32_fa20_21_or0
.subckt and_gate a=a[21] b=b[21] out=u_csamul_rca32_and21_21
.subckt fa a=u_csamul_rca32_and21_21 b=u_csamul_rca32_fa22_20_xor1 cin=u_csamul_rca32_fa21_20_or0 fa_xor1=u_csamul_rca32_fa21_21_xor1 fa_or0=u_csamul_rca32_fa21_21_or0
.subckt and_gate a=a[22] b=b[21] out=u_csamul_rca32_and22_21
.subckt fa a=u_csamul_rca32_and22_21 b=u_csamul_rca32_fa23_20_xor1 cin=u_csamul_rca32_fa22_20_or0 fa_xor1=u_csamul_rca32_fa22_21_xor1 fa_or0=u_csamul_rca32_fa22_21_or0
.subckt and_gate a=a[23] b=b[21] out=u_csamul_rca32_and23_21
.subckt fa a=u_csamul_rca32_and23_21 b=u_csamul_rca32_fa24_20_xor1 cin=u_csamul_rca32_fa23_20_or0 fa_xor1=u_csamul_rca32_fa23_21_xor1 fa_or0=u_csamul_rca32_fa23_21_or0
.subckt and_gate a=a[24] b=b[21] out=u_csamul_rca32_and24_21
.subckt fa a=u_csamul_rca32_and24_21 b=u_csamul_rca32_fa25_20_xor1 cin=u_csamul_rca32_fa24_20_or0 fa_xor1=u_csamul_rca32_fa24_21_xor1 fa_or0=u_csamul_rca32_fa24_21_or0
.subckt and_gate a=a[25] b=b[21] out=u_csamul_rca32_and25_21
.subckt fa a=u_csamul_rca32_and25_21 b=u_csamul_rca32_fa26_20_xor1 cin=u_csamul_rca32_fa25_20_or0 fa_xor1=u_csamul_rca32_fa25_21_xor1 fa_or0=u_csamul_rca32_fa25_21_or0
.subckt and_gate a=a[26] b=b[21] out=u_csamul_rca32_and26_21
.subckt fa a=u_csamul_rca32_and26_21 b=u_csamul_rca32_fa27_20_xor1 cin=u_csamul_rca32_fa26_20_or0 fa_xor1=u_csamul_rca32_fa26_21_xor1 fa_or0=u_csamul_rca32_fa26_21_or0
.subckt and_gate a=a[27] b=b[21] out=u_csamul_rca32_and27_21
.subckt fa a=u_csamul_rca32_and27_21 b=u_csamul_rca32_fa28_20_xor1 cin=u_csamul_rca32_fa27_20_or0 fa_xor1=u_csamul_rca32_fa27_21_xor1 fa_or0=u_csamul_rca32_fa27_21_or0
.subckt and_gate a=a[28] b=b[21] out=u_csamul_rca32_and28_21
.subckt fa a=u_csamul_rca32_and28_21 b=u_csamul_rca32_fa29_20_xor1 cin=u_csamul_rca32_fa28_20_or0 fa_xor1=u_csamul_rca32_fa28_21_xor1 fa_or0=u_csamul_rca32_fa28_21_or0
.subckt and_gate a=a[29] b=b[21] out=u_csamul_rca32_and29_21
.subckt fa a=u_csamul_rca32_and29_21 b=u_csamul_rca32_fa30_20_xor1 cin=u_csamul_rca32_fa29_20_or0 fa_xor1=u_csamul_rca32_fa29_21_xor1 fa_or0=u_csamul_rca32_fa29_21_or0
.subckt and_gate a=a[30] b=b[21] out=u_csamul_rca32_and30_21
.subckt fa a=u_csamul_rca32_and30_21 b=u_csamul_rca32_and31_20 cin=u_csamul_rca32_fa30_20_or0 fa_xor1=u_csamul_rca32_fa30_21_xor1 fa_or0=u_csamul_rca32_fa30_21_or0
.subckt and_gate a=a[31] b=b[21] out=u_csamul_rca32_and31_21
.subckt and_gate a=a[0] b=b[22] out=u_csamul_rca32_and0_22
.subckt fa a=u_csamul_rca32_and0_22 b=u_csamul_rca32_fa1_21_xor1 cin=u_csamul_rca32_fa0_21_or0 fa_xor1=u_csamul_rca32_fa0_22_xor1 fa_or0=u_csamul_rca32_fa0_22_or0
.subckt and_gate a=a[1] b=b[22] out=u_csamul_rca32_and1_22
.subckt fa a=u_csamul_rca32_and1_22 b=u_csamul_rca32_fa2_21_xor1 cin=u_csamul_rca32_fa1_21_or0 fa_xor1=u_csamul_rca32_fa1_22_xor1 fa_or0=u_csamul_rca32_fa1_22_or0
.subckt and_gate a=a[2] b=b[22] out=u_csamul_rca32_and2_22
.subckt fa a=u_csamul_rca32_and2_22 b=u_csamul_rca32_fa3_21_xor1 cin=u_csamul_rca32_fa2_21_or0 fa_xor1=u_csamul_rca32_fa2_22_xor1 fa_or0=u_csamul_rca32_fa2_22_or0
.subckt and_gate a=a[3] b=b[22] out=u_csamul_rca32_and3_22
.subckt fa a=u_csamul_rca32_and3_22 b=u_csamul_rca32_fa4_21_xor1 cin=u_csamul_rca32_fa3_21_or0 fa_xor1=u_csamul_rca32_fa3_22_xor1 fa_or0=u_csamul_rca32_fa3_22_or0
.subckt and_gate a=a[4] b=b[22] out=u_csamul_rca32_and4_22
.subckt fa a=u_csamul_rca32_and4_22 b=u_csamul_rca32_fa5_21_xor1 cin=u_csamul_rca32_fa4_21_or0 fa_xor1=u_csamul_rca32_fa4_22_xor1 fa_or0=u_csamul_rca32_fa4_22_or0
.subckt and_gate a=a[5] b=b[22] out=u_csamul_rca32_and5_22
.subckt fa a=u_csamul_rca32_and5_22 b=u_csamul_rca32_fa6_21_xor1 cin=u_csamul_rca32_fa5_21_or0 fa_xor1=u_csamul_rca32_fa5_22_xor1 fa_or0=u_csamul_rca32_fa5_22_or0
.subckt and_gate a=a[6] b=b[22] out=u_csamul_rca32_and6_22
.subckt fa a=u_csamul_rca32_and6_22 b=u_csamul_rca32_fa7_21_xor1 cin=u_csamul_rca32_fa6_21_or0 fa_xor1=u_csamul_rca32_fa6_22_xor1 fa_or0=u_csamul_rca32_fa6_22_or0
.subckt and_gate a=a[7] b=b[22] out=u_csamul_rca32_and7_22
.subckt fa a=u_csamul_rca32_and7_22 b=u_csamul_rca32_fa8_21_xor1 cin=u_csamul_rca32_fa7_21_or0 fa_xor1=u_csamul_rca32_fa7_22_xor1 fa_or0=u_csamul_rca32_fa7_22_or0
.subckt and_gate a=a[8] b=b[22] out=u_csamul_rca32_and8_22
.subckt fa a=u_csamul_rca32_and8_22 b=u_csamul_rca32_fa9_21_xor1 cin=u_csamul_rca32_fa8_21_or0 fa_xor1=u_csamul_rca32_fa8_22_xor1 fa_or0=u_csamul_rca32_fa8_22_or0
.subckt and_gate a=a[9] b=b[22] out=u_csamul_rca32_and9_22
.subckt fa a=u_csamul_rca32_and9_22 b=u_csamul_rca32_fa10_21_xor1 cin=u_csamul_rca32_fa9_21_or0 fa_xor1=u_csamul_rca32_fa9_22_xor1 fa_or0=u_csamul_rca32_fa9_22_or0
.subckt and_gate a=a[10] b=b[22] out=u_csamul_rca32_and10_22
.subckt fa a=u_csamul_rca32_and10_22 b=u_csamul_rca32_fa11_21_xor1 cin=u_csamul_rca32_fa10_21_or0 fa_xor1=u_csamul_rca32_fa10_22_xor1 fa_or0=u_csamul_rca32_fa10_22_or0
.subckt and_gate a=a[11] b=b[22] out=u_csamul_rca32_and11_22
.subckt fa a=u_csamul_rca32_and11_22 b=u_csamul_rca32_fa12_21_xor1 cin=u_csamul_rca32_fa11_21_or0 fa_xor1=u_csamul_rca32_fa11_22_xor1 fa_or0=u_csamul_rca32_fa11_22_or0
.subckt and_gate a=a[12] b=b[22] out=u_csamul_rca32_and12_22
.subckt fa a=u_csamul_rca32_and12_22 b=u_csamul_rca32_fa13_21_xor1 cin=u_csamul_rca32_fa12_21_or0 fa_xor1=u_csamul_rca32_fa12_22_xor1 fa_or0=u_csamul_rca32_fa12_22_or0
.subckt and_gate a=a[13] b=b[22] out=u_csamul_rca32_and13_22
.subckt fa a=u_csamul_rca32_and13_22 b=u_csamul_rca32_fa14_21_xor1 cin=u_csamul_rca32_fa13_21_or0 fa_xor1=u_csamul_rca32_fa13_22_xor1 fa_or0=u_csamul_rca32_fa13_22_or0
.subckt and_gate a=a[14] b=b[22] out=u_csamul_rca32_and14_22
.subckt fa a=u_csamul_rca32_and14_22 b=u_csamul_rca32_fa15_21_xor1 cin=u_csamul_rca32_fa14_21_or0 fa_xor1=u_csamul_rca32_fa14_22_xor1 fa_or0=u_csamul_rca32_fa14_22_or0
.subckt and_gate a=a[15] b=b[22] out=u_csamul_rca32_and15_22
.subckt fa a=u_csamul_rca32_and15_22 b=u_csamul_rca32_fa16_21_xor1 cin=u_csamul_rca32_fa15_21_or0 fa_xor1=u_csamul_rca32_fa15_22_xor1 fa_or0=u_csamul_rca32_fa15_22_or0
.subckt and_gate a=a[16] b=b[22] out=u_csamul_rca32_and16_22
.subckt fa a=u_csamul_rca32_and16_22 b=u_csamul_rca32_fa17_21_xor1 cin=u_csamul_rca32_fa16_21_or0 fa_xor1=u_csamul_rca32_fa16_22_xor1 fa_or0=u_csamul_rca32_fa16_22_or0
.subckt and_gate a=a[17] b=b[22] out=u_csamul_rca32_and17_22
.subckt fa a=u_csamul_rca32_and17_22 b=u_csamul_rca32_fa18_21_xor1 cin=u_csamul_rca32_fa17_21_or0 fa_xor1=u_csamul_rca32_fa17_22_xor1 fa_or0=u_csamul_rca32_fa17_22_or0
.subckt and_gate a=a[18] b=b[22] out=u_csamul_rca32_and18_22
.subckt fa a=u_csamul_rca32_and18_22 b=u_csamul_rca32_fa19_21_xor1 cin=u_csamul_rca32_fa18_21_or0 fa_xor1=u_csamul_rca32_fa18_22_xor1 fa_or0=u_csamul_rca32_fa18_22_or0
.subckt and_gate a=a[19] b=b[22] out=u_csamul_rca32_and19_22
.subckt fa a=u_csamul_rca32_and19_22 b=u_csamul_rca32_fa20_21_xor1 cin=u_csamul_rca32_fa19_21_or0 fa_xor1=u_csamul_rca32_fa19_22_xor1 fa_or0=u_csamul_rca32_fa19_22_or0
.subckt and_gate a=a[20] b=b[22] out=u_csamul_rca32_and20_22
.subckt fa a=u_csamul_rca32_and20_22 b=u_csamul_rca32_fa21_21_xor1 cin=u_csamul_rca32_fa20_21_or0 fa_xor1=u_csamul_rca32_fa20_22_xor1 fa_or0=u_csamul_rca32_fa20_22_or0
.subckt and_gate a=a[21] b=b[22] out=u_csamul_rca32_and21_22
.subckt fa a=u_csamul_rca32_and21_22 b=u_csamul_rca32_fa22_21_xor1 cin=u_csamul_rca32_fa21_21_or0 fa_xor1=u_csamul_rca32_fa21_22_xor1 fa_or0=u_csamul_rca32_fa21_22_or0
.subckt and_gate a=a[22] b=b[22] out=u_csamul_rca32_and22_22
.subckt fa a=u_csamul_rca32_and22_22 b=u_csamul_rca32_fa23_21_xor1 cin=u_csamul_rca32_fa22_21_or0 fa_xor1=u_csamul_rca32_fa22_22_xor1 fa_or0=u_csamul_rca32_fa22_22_or0
.subckt and_gate a=a[23] b=b[22] out=u_csamul_rca32_and23_22
.subckt fa a=u_csamul_rca32_and23_22 b=u_csamul_rca32_fa24_21_xor1 cin=u_csamul_rca32_fa23_21_or0 fa_xor1=u_csamul_rca32_fa23_22_xor1 fa_or0=u_csamul_rca32_fa23_22_or0
.subckt and_gate a=a[24] b=b[22] out=u_csamul_rca32_and24_22
.subckt fa a=u_csamul_rca32_and24_22 b=u_csamul_rca32_fa25_21_xor1 cin=u_csamul_rca32_fa24_21_or0 fa_xor1=u_csamul_rca32_fa24_22_xor1 fa_or0=u_csamul_rca32_fa24_22_or0
.subckt and_gate a=a[25] b=b[22] out=u_csamul_rca32_and25_22
.subckt fa a=u_csamul_rca32_and25_22 b=u_csamul_rca32_fa26_21_xor1 cin=u_csamul_rca32_fa25_21_or0 fa_xor1=u_csamul_rca32_fa25_22_xor1 fa_or0=u_csamul_rca32_fa25_22_or0
.subckt and_gate a=a[26] b=b[22] out=u_csamul_rca32_and26_22
.subckt fa a=u_csamul_rca32_and26_22 b=u_csamul_rca32_fa27_21_xor1 cin=u_csamul_rca32_fa26_21_or0 fa_xor1=u_csamul_rca32_fa26_22_xor1 fa_or0=u_csamul_rca32_fa26_22_or0
.subckt and_gate a=a[27] b=b[22] out=u_csamul_rca32_and27_22
.subckt fa a=u_csamul_rca32_and27_22 b=u_csamul_rca32_fa28_21_xor1 cin=u_csamul_rca32_fa27_21_or0 fa_xor1=u_csamul_rca32_fa27_22_xor1 fa_or0=u_csamul_rca32_fa27_22_or0
.subckt and_gate a=a[28] b=b[22] out=u_csamul_rca32_and28_22
.subckt fa a=u_csamul_rca32_and28_22 b=u_csamul_rca32_fa29_21_xor1 cin=u_csamul_rca32_fa28_21_or0 fa_xor1=u_csamul_rca32_fa28_22_xor1 fa_or0=u_csamul_rca32_fa28_22_or0
.subckt and_gate a=a[29] b=b[22] out=u_csamul_rca32_and29_22
.subckt fa a=u_csamul_rca32_and29_22 b=u_csamul_rca32_fa30_21_xor1 cin=u_csamul_rca32_fa29_21_or0 fa_xor1=u_csamul_rca32_fa29_22_xor1 fa_or0=u_csamul_rca32_fa29_22_or0
.subckt and_gate a=a[30] b=b[22] out=u_csamul_rca32_and30_22
.subckt fa a=u_csamul_rca32_and30_22 b=u_csamul_rca32_and31_21 cin=u_csamul_rca32_fa30_21_or0 fa_xor1=u_csamul_rca32_fa30_22_xor1 fa_or0=u_csamul_rca32_fa30_22_or0
.subckt and_gate a=a[31] b=b[22] out=u_csamul_rca32_and31_22
.subckt and_gate a=a[0] b=b[23] out=u_csamul_rca32_and0_23
.subckt fa a=u_csamul_rca32_and0_23 b=u_csamul_rca32_fa1_22_xor1 cin=u_csamul_rca32_fa0_22_or0 fa_xor1=u_csamul_rca32_fa0_23_xor1 fa_or0=u_csamul_rca32_fa0_23_or0
.subckt and_gate a=a[1] b=b[23] out=u_csamul_rca32_and1_23
.subckt fa a=u_csamul_rca32_and1_23 b=u_csamul_rca32_fa2_22_xor1 cin=u_csamul_rca32_fa1_22_or0 fa_xor1=u_csamul_rca32_fa1_23_xor1 fa_or0=u_csamul_rca32_fa1_23_or0
.subckt and_gate a=a[2] b=b[23] out=u_csamul_rca32_and2_23
.subckt fa a=u_csamul_rca32_and2_23 b=u_csamul_rca32_fa3_22_xor1 cin=u_csamul_rca32_fa2_22_or0 fa_xor1=u_csamul_rca32_fa2_23_xor1 fa_or0=u_csamul_rca32_fa2_23_or0
.subckt and_gate a=a[3] b=b[23] out=u_csamul_rca32_and3_23
.subckt fa a=u_csamul_rca32_and3_23 b=u_csamul_rca32_fa4_22_xor1 cin=u_csamul_rca32_fa3_22_or0 fa_xor1=u_csamul_rca32_fa3_23_xor1 fa_or0=u_csamul_rca32_fa3_23_or0
.subckt and_gate a=a[4] b=b[23] out=u_csamul_rca32_and4_23
.subckt fa a=u_csamul_rca32_and4_23 b=u_csamul_rca32_fa5_22_xor1 cin=u_csamul_rca32_fa4_22_or0 fa_xor1=u_csamul_rca32_fa4_23_xor1 fa_or0=u_csamul_rca32_fa4_23_or0
.subckt and_gate a=a[5] b=b[23] out=u_csamul_rca32_and5_23
.subckt fa a=u_csamul_rca32_and5_23 b=u_csamul_rca32_fa6_22_xor1 cin=u_csamul_rca32_fa5_22_or0 fa_xor1=u_csamul_rca32_fa5_23_xor1 fa_or0=u_csamul_rca32_fa5_23_or0
.subckt and_gate a=a[6] b=b[23] out=u_csamul_rca32_and6_23
.subckt fa a=u_csamul_rca32_and6_23 b=u_csamul_rca32_fa7_22_xor1 cin=u_csamul_rca32_fa6_22_or0 fa_xor1=u_csamul_rca32_fa6_23_xor1 fa_or0=u_csamul_rca32_fa6_23_or0
.subckt and_gate a=a[7] b=b[23] out=u_csamul_rca32_and7_23
.subckt fa a=u_csamul_rca32_and7_23 b=u_csamul_rca32_fa8_22_xor1 cin=u_csamul_rca32_fa7_22_or0 fa_xor1=u_csamul_rca32_fa7_23_xor1 fa_or0=u_csamul_rca32_fa7_23_or0
.subckt and_gate a=a[8] b=b[23] out=u_csamul_rca32_and8_23
.subckt fa a=u_csamul_rca32_and8_23 b=u_csamul_rca32_fa9_22_xor1 cin=u_csamul_rca32_fa8_22_or0 fa_xor1=u_csamul_rca32_fa8_23_xor1 fa_or0=u_csamul_rca32_fa8_23_or0
.subckt and_gate a=a[9] b=b[23] out=u_csamul_rca32_and9_23
.subckt fa a=u_csamul_rca32_and9_23 b=u_csamul_rca32_fa10_22_xor1 cin=u_csamul_rca32_fa9_22_or0 fa_xor1=u_csamul_rca32_fa9_23_xor1 fa_or0=u_csamul_rca32_fa9_23_or0
.subckt and_gate a=a[10] b=b[23] out=u_csamul_rca32_and10_23
.subckt fa a=u_csamul_rca32_and10_23 b=u_csamul_rca32_fa11_22_xor1 cin=u_csamul_rca32_fa10_22_or0 fa_xor1=u_csamul_rca32_fa10_23_xor1 fa_or0=u_csamul_rca32_fa10_23_or0
.subckt and_gate a=a[11] b=b[23] out=u_csamul_rca32_and11_23
.subckt fa a=u_csamul_rca32_and11_23 b=u_csamul_rca32_fa12_22_xor1 cin=u_csamul_rca32_fa11_22_or0 fa_xor1=u_csamul_rca32_fa11_23_xor1 fa_or0=u_csamul_rca32_fa11_23_or0
.subckt and_gate a=a[12] b=b[23] out=u_csamul_rca32_and12_23
.subckt fa a=u_csamul_rca32_and12_23 b=u_csamul_rca32_fa13_22_xor1 cin=u_csamul_rca32_fa12_22_or0 fa_xor1=u_csamul_rca32_fa12_23_xor1 fa_or0=u_csamul_rca32_fa12_23_or0
.subckt and_gate a=a[13] b=b[23] out=u_csamul_rca32_and13_23
.subckt fa a=u_csamul_rca32_and13_23 b=u_csamul_rca32_fa14_22_xor1 cin=u_csamul_rca32_fa13_22_or0 fa_xor1=u_csamul_rca32_fa13_23_xor1 fa_or0=u_csamul_rca32_fa13_23_or0
.subckt and_gate a=a[14] b=b[23] out=u_csamul_rca32_and14_23
.subckt fa a=u_csamul_rca32_and14_23 b=u_csamul_rca32_fa15_22_xor1 cin=u_csamul_rca32_fa14_22_or0 fa_xor1=u_csamul_rca32_fa14_23_xor1 fa_or0=u_csamul_rca32_fa14_23_or0
.subckt and_gate a=a[15] b=b[23] out=u_csamul_rca32_and15_23
.subckt fa a=u_csamul_rca32_and15_23 b=u_csamul_rca32_fa16_22_xor1 cin=u_csamul_rca32_fa15_22_or0 fa_xor1=u_csamul_rca32_fa15_23_xor1 fa_or0=u_csamul_rca32_fa15_23_or0
.subckt and_gate a=a[16] b=b[23] out=u_csamul_rca32_and16_23
.subckt fa a=u_csamul_rca32_and16_23 b=u_csamul_rca32_fa17_22_xor1 cin=u_csamul_rca32_fa16_22_or0 fa_xor1=u_csamul_rca32_fa16_23_xor1 fa_or0=u_csamul_rca32_fa16_23_or0
.subckt and_gate a=a[17] b=b[23] out=u_csamul_rca32_and17_23
.subckt fa a=u_csamul_rca32_and17_23 b=u_csamul_rca32_fa18_22_xor1 cin=u_csamul_rca32_fa17_22_or0 fa_xor1=u_csamul_rca32_fa17_23_xor1 fa_or0=u_csamul_rca32_fa17_23_or0
.subckt and_gate a=a[18] b=b[23] out=u_csamul_rca32_and18_23
.subckt fa a=u_csamul_rca32_and18_23 b=u_csamul_rca32_fa19_22_xor1 cin=u_csamul_rca32_fa18_22_or0 fa_xor1=u_csamul_rca32_fa18_23_xor1 fa_or0=u_csamul_rca32_fa18_23_or0
.subckt and_gate a=a[19] b=b[23] out=u_csamul_rca32_and19_23
.subckt fa a=u_csamul_rca32_and19_23 b=u_csamul_rca32_fa20_22_xor1 cin=u_csamul_rca32_fa19_22_or0 fa_xor1=u_csamul_rca32_fa19_23_xor1 fa_or0=u_csamul_rca32_fa19_23_or0
.subckt and_gate a=a[20] b=b[23] out=u_csamul_rca32_and20_23
.subckt fa a=u_csamul_rca32_and20_23 b=u_csamul_rca32_fa21_22_xor1 cin=u_csamul_rca32_fa20_22_or0 fa_xor1=u_csamul_rca32_fa20_23_xor1 fa_or0=u_csamul_rca32_fa20_23_or0
.subckt and_gate a=a[21] b=b[23] out=u_csamul_rca32_and21_23
.subckt fa a=u_csamul_rca32_and21_23 b=u_csamul_rca32_fa22_22_xor1 cin=u_csamul_rca32_fa21_22_or0 fa_xor1=u_csamul_rca32_fa21_23_xor1 fa_or0=u_csamul_rca32_fa21_23_or0
.subckt and_gate a=a[22] b=b[23] out=u_csamul_rca32_and22_23
.subckt fa a=u_csamul_rca32_and22_23 b=u_csamul_rca32_fa23_22_xor1 cin=u_csamul_rca32_fa22_22_or0 fa_xor1=u_csamul_rca32_fa22_23_xor1 fa_or0=u_csamul_rca32_fa22_23_or0
.subckt and_gate a=a[23] b=b[23] out=u_csamul_rca32_and23_23
.subckt fa a=u_csamul_rca32_and23_23 b=u_csamul_rca32_fa24_22_xor1 cin=u_csamul_rca32_fa23_22_or0 fa_xor1=u_csamul_rca32_fa23_23_xor1 fa_or0=u_csamul_rca32_fa23_23_or0
.subckt and_gate a=a[24] b=b[23] out=u_csamul_rca32_and24_23
.subckt fa a=u_csamul_rca32_and24_23 b=u_csamul_rca32_fa25_22_xor1 cin=u_csamul_rca32_fa24_22_or0 fa_xor1=u_csamul_rca32_fa24_23_xor1 fa_or0=u_csamul_rca32_fa24_23_or0
.subckt and_gate a=a[25] b=b[23] out=u_csamul_rca32_and25_23
.subckt fa a=u_csamul_rca32_and25_23 b=u_csamul_rca32_fa26_22_xor1 cin=u_csamul_rca32_fa25_22_or0 fa_xor1=u_csamul_rca32_fa25_23_xor1 fa_or0=u_csamul_rca32_fa25_23_or0
.subckt and_gate a=a[26] b=b[23] out=u_csamul_rca32_and26_23
.subckt fa a=u_csamul_rca32_and26_23 b=u_csamul_rca32_fa27_22_xor1 cin=u_csamul_rca32_fa26_22_or0 fa_xor1=u_csamul_rca32_fa26_23_xor1 fa_or0=u_csamul_rca32_fa26_23_or0
.subckt and_gate a=a[27] b=b[23] out=u_csamul_rca32_and27_23
.subckt fa a=u_csamul_rca32_and27_23 b=u_csamul_rca32_fa28_22_xor1 cin=u_csamul_rca32_fa27_22_or0 fa_xor1=u_csamul_rca32_fa27_23_xor1 fa_or0=u_csamul_rca32_fa27_23_or0
.subckt and_gate a=a[28] b=b[23] out=u_csamul_rca32_and28_23
.subckt fa a=u_csamul_rca32_and28_23 b=u_csamul_rca32_fa29_22_xor1 cin=u_csamul_rca32_fa28_22_or0 fa_xor1=u_csamul_rca32_fa28_23_xor1 fa_or0=u_csamul_rca32_fa28_23_or0
.subckt and_gate a=a[29] b=b[23] out=u_csamul_rca32_and29_23
.subckt fa a=u_csamul_rca32_and29_23 b=u_csamul_rca32_fa30_22_xor1 cin=u_csamul_rca32_fa29_22_or0 fa_xor1=u_csamul_rca32_fa29_23_xor1 fa_or0=u_csamul_rca32_fa29_23_or0
.subckt and_gate a=a[30] b=b[23] out=u_csamul_rca32_and30_23
.subckt fa a=u_csamul_rca32_and30_23 b=u_csamul_rca32_and31_22 cin=u_csamul_rca32_fa30_22_or0 fa_xor1=u_csamul_rca32_fa30_23_xor1 fa_or0=u_csamul_rca32_fa30_23_or0
.subckt and_gate a=a[31] b=b[23] out=u_csamul_rca32_and31_23
.subckt and_gate a=a[0] b=b[24] out=u_csamul_rca32_and0_24
.subckt fa a=u_csamul_rca32_and0_24 b=u_csamul_rca32_fa1_23_xor1 cin=u_csamul_rca32_fa0_23_or0 fa_xor1=u_csamul_rca32_fa0_24_xor1 fa_or0=u_csamul_rca32_fa0_24_or0
.subckt and_gate a=a[1] b=b[24] out=u_csamul_rca32_and1_24
.subckt fa a=u_csamul_rca32_and1_24 b=u_csamul_rca32_fa2_23_xor1 cin=u_csamul_rca32_fa1_23_or0 fa_xor1=u_csamul_rca32_fa1_24_xor1 fa_or0=u_csamul_rca32_fa1_24_or0
.subckt and_gate a=a[2] b=b[24] out=u_csamul_rca32_and2_24
.subckt fa a=u_csamul_rca32_and2_24 b=u_csamul_rca32_fa3_23_xor1 cin=u_csamul_rca32_fa2_23_or0 fa_xor1=u_csamul_rca32_fa2_24_xor1 fa_or0=u_csamul_rca32_fa2_24_or0
.subckt and_gate a=a[3] b=b[24] out=u_csamul_rca32_and3_24
.subckt fa a=u_csamul_rca32_and3_24 b=u_csamul_rca32_fa4_23_xor1 cin=u_csamul_rca32_fa3_23_or0 fa_xor1=u_csamul_rca32_fa3_24_xor1 fa_or0=u_csamul_rca32_fa3_24_or0
.subckt and_gate a=a[4] b=b[24] out=u_csamul_rca32_and4_24
.subckt fa a=u_csamul_rca32_and4_24 b=u_csamul_rca32_fa5_23_xor1 cin=u_csamul_rca32_fa4_23_or0 fa_xor1=u_csamul_rca32_fa4_24_xor1 fa_or0=u_csamul_rca32_fa4_24_or0
.subckt and_gate a=a[5] b=b[24] out=u_csamul_rca32_and5_24
.subckt fa a=u_csamul_rca32_and5_24 b=u_csamul_rca32_fa6_23_xor1 cin=u_csamul_rca32_fa5_23_or0 fa_xor1=u_csamul_rca32_fa5_24_xor1 fa_or0=u_csamul_rca32_fa5_24_or0
.subckt and_gate a=a[6] b=b[24] out=u_csamul_rca32_and6_24
.subckt fa a=u_csamul_rca32_and6_24 b=u_csamul_rca32_fa7_23_xor1 cin=u_csamul_rca32_fa6_23_or0 fa_xor1=u_csamul_rca32_fa6_24_xor1 fa_or0=u_csamul_rca32_fa6_24_or0
.subckt and_gate a=a[7] b=b[24] out=u_csamul_rca32_and7_24
.subckt fa a=u_csamul_rca32_and7_24 b=u_csamul_rca32_fa8_23_xor1 cin=u_csamul_rca32_fa7_23_or0 fa_xor1=u_csamul_rca32_fa7_24_xor1 fa_or0=u_csamul_rca32_fa7_24_or0
.subckt and_gate a=a[8] b=b[24] out=u_csamul_rca32_and8_24
.subckt fa a=u_csamul_rca32_and8_24 b=u_csamul_rca32_fa9_23_xor1 cin=u_csamul_rca32_fa8_23_or0 fa_xor1=u_csamul_rca32_fa8_24_xor1 fa_or0=u_csamul_rca32_fa8_24_or0
.subckt and_gate a=a[9] b=b[24] out=u_csamul_rca32_and9_24
.subckt fa a=u_csamul_rca32_and9_24 b=u_csamul_rca32_fa10_23_xor1 cin=u_csamul_rca32_fa9_23_or0 fa_xor1=u_csamul_rca32_fa9_24_xor1 fa_or0=u_csamul_rca32_fa9_24_or0
.subckt and_gate a=a[10] b=b[24] out=u_csamul_rca32_and10_24
.subckt fa a=u_csamul_rca32_and10_24 b=u_csamul_rca32_fa11_23_xor1 cin=u_csamul_rca32_fa10_23_or0 fa_xor1=u_csamul_rca32_fa10_24_xor1 fa_or0=u_csamul_rca32_fa10_24_or0
.subckt and_gate a=a[11] b=b[24] out=u_csamul_rca32_and11_24
.subckt fa a=u_csamul_rca32_and11_24 b=u_csamul_rca32_fa12_23_xor1 cin=u_csamul_rca32_fa11_23_or0 fa_xor1=u_csamul_rca32_fa11_24_xor1 fa_or0=u_csamul_rca32_fa11_24_or0
.subckt and_gate a=a[12] b=b[24] out=u_csamul_rca32_and12_24
.subckt fa a=u_csamul_rca32_and12_24 b=u_csamul_rca32_fa13_23_xor1 cin=u_csamul_rca32_fa12_23_or0 fa_xor1=u_csamul_rca32_fa12_24_xor1 fa_or0=u_csamul_rca32_fa12_24_or0
.subckt and_gate a=a[13] b=b[24] out=u_csamul_rca32_and13_24
.subckt fa a=u_csamul_rca32_and13_24 b=u_csamul_rca32_fa14_23_xor1 cin=u_csamul_rca32_fa13_23_or0 fa_xor1=u_csamul_rca32_fa13_24_xor1 fa_or0=u_csamul_rca32_fa13_24_or0
.subckt and_gate a=a[14] b=b[24] out=u_csamul_rca32_and14_24
.subckt fa a=u_csamul_rca32_and14_24 b=u_csamul_rca32_fa15_23_xor1 cin=u_csamul_rca32_fa14_23_or0 fa_xor1=u_csamul_rca32_fa14_24_xor1 fa_or0=u_csamul_rca32_fa14_24_or0
.subckt and_gate a=a[15] b=b[24] out=u_csamul_rca32_and15_24
.subckt fa a=u_csamul_rca32_and15_24 b=u_csamul_rca32_fa16_23_xor1 cin=u_csamul_rca32_fa15_23_or0 fa_xor1=u_csamul_rca32_fa15_24_xor1 fa_or0=u_csamul_rca32_fa15_24_or0
.subckt and_gate a=a[16] b=b[24] out=u_csamul_rca32_and16_24
.subckt fa a=u_csamul_rca32_and16_24 b=u_csamul_rca32_fa17_23_xor1 cin=u_csamul_rca32_fa16_23_or0 fa_xor1=u_csamul_rca32_fa16_24_xor1 fa_or0=u_csamul_rca32_fa16_24_or0
.subckt and_gate a=a[17] b=b[24] out=u_csamul_rca32_and17_24
.subckt fa a=u_csamul_rca32_and17_24 b=u_csamul_rca32_fa18_23_xor1 cin=u_csamul_rca32_fa17_23_or0 fa_xor1=u_csamul_rca32_fa17_24_xor1 fa_or0=u_csamul_rca32_fa17_24_or0
.subckt and_gate a=a[18] b=b[24] out=u_csamul_rca32_and18_24
.subckt fa a=u_csamul_rca32_and18_24 b=u_csamul_rca32_fa19_23_xor1 cin=u_csamul_rca32_fa18_23_or0 fa_xor1=u_csamul_rca32_fa18_24_xor1 fa_or0=u_csamul_rca32_fa18_24_or0
.subckt and_gate a=a[19] b=b[24] out=u_csamul_rca32_and19_24
.subckt fa a=u_csamul_rca32_and19_24 b=u_csamul_rca32_fa20_23_xor1 cin=u_csamul_rca32_fa19_23_or0 fa_xor1=u_csamul_rca32_fa19_24_xor1 fa_or0=u_csamul_rca32_fa19_24_or0
.subckt and_gate a=a[20] b=b[24] out=u_csamul_rca32_and20_24
.subckt fa a=u_csamul_rca32_and20_24 b=u_csamul_rca32_fa21_23_xor1 cin=u_csamul_rca32_fa20_23_or0 fa_xor1=u_csamul_rca32_fa20_24_xor1 fa_or0=u_csamul_rca32_fa20_24_or0
.subckt and_gate a=a[21] b=b[24] out=u_csamul_rca32_and21_24
.subckt fa a=u_csamul_rca32_and21_24 b=u_csamul_rca32_fa22_23_xor1 cin=u_csamul_rca32_fa21_23_or0 fa_xor1=u_csamul_rca32_fa21_24_xor1 fa_or0=u_csamul_rca32_fa21_24_or0
.subckt and_gate a=a[22] b=b[24] out=u_csamul_rca32_and22_24
.subckt fa a=u_csamul_rca32_and22_24 b=u_csamul_rca32_fa23_23_xor1 cin=u_csamul_rca32_fa22_23_or0 fa_xor1=u_csamul_rca32_fa22_24_xor1 fa_or0=u_csamul_rca32_fa22_24_or0
.subckt and_gate a=a[23] b=b[24] out=u_csamul_rca32_and23_24
.subckt fa a=u_csamul_rca32_and23_24 b=u_csamul_rca32_fa24_23_xor1 cin=u_csamul_rca32_fa23_23_or0 fa_xor1=u_csamul_rca32_fa23_24_xor1 fa_or0=u_csamul_rca32_fa23_24_or0
.subckt and_gate a=a[24] b=b[24] out=u_csamul_rca32_and24_24
.subckt fa a=u_csamul_rca32_and24_24 b=u_csamul_rca32_fa25_23_xor1 cin=u_csamul_rca32_fa24_23_or0 fa_xor1=u_csamul_rca32_fa24_24_xor1 fa_or0=u_csamul_rca32_fa24_24_or0
.subckt and_gate a=a[25] b=b[24] out=u_csamul_rca32_and25_24
.subckt fa a=u_csamul_rca32_and25_24 b=u_csamul_rca32_fa26_23_xor1 cin=u_csamul_rca32_fa25_23_or0 fa_xor1=u_csamul_rca32_fa25_24_xor1 fa_or0=u_csamul_rca32_fa25_24_or0
.subckt and_gate a=a[26] b=b[24] out=u_csamul_rca32_and26_24
.subckt fa a=u_csamul_rca32_and26_24 b=u_csamul_rca32_fa27_23_xor1 cin=u_csamul_rca32_fa26_23_or0 fa_xor1=u_csamul_rca32_fa26_24_xor1 fa_or0=u_csamul_rca32_fa26_24_or0
.subckt and_gate a=a[27] b=b[24] out=u_csamul_rca32_and27_24
.subckt fa a=u_csamul_rca32_and27_24 b=u_csamul_rca32_fa28_23_xor1 cin=u_csamul_rca32_fa27_23_or0 fa_xor1=u_csamul_rca32_fa27_24_xor1 fa_or0=u_csamul_rca32_fa27_24_or0
.subckt and_gate a=a[28] b=b[24] out=u_csamul_rca32_and28_24
.subckt fa a=u_csamul_rca32_and28_24 b=u_csamul_rca32_fa29_23_xor1 cin=u_csamul_rca32_fa28_23_or0 fa_xor1=u_csamul_rca32_fa28_24_xor1 fa_or0=u_csamul_rca32_fa28_24_or0
.subckt and_gate a=a[29] b=b[24] out=u_csamul_rca32_and29_24
.subckt fa a=u_csamul_rca32_and29_24 b=u_csamul_rca32_fa30_23_xor1 cin=u_csamul_rca32_fa29_23_or0 fa_xor1=u_csamul_rca32_fa29_24_xor1 fa_or0=u_csamul_rca32_fa29_24_or0
.subckt and_gate a=a[30] b=b[24] out=u_csamul_rca32_and30_24
.subckt fa a=u_csamul_rca32_and30_24 b=u_csamul_rca32_and31_23 cin=u_csamul_rca32_fa30_23_or0 fa_xor1=u_csamul_rca32_fa30_24_xor1 fa_or0=u_csamul_rca32_fa30_24_or0
.subckt and_gate a=a[31] b=b[24] out=u_csamul_rca32_and31_24
.subckt and_gate a=a[0] b=b[25] out=u_csamul_rca32_and0_25
.subckt fa a=u_csamul_rca32_and0_25 b=u_csamul_rca32_fa1_24_xor1 cin=u_csamul_rca32_fa0_24_or0 fa_xor1=u_csamul_rca32_fa0_25_xor1 fa_or0=u_csamul_rca32_fa0_25_or0
.subckt and_gate a=a[1] b=b[25] out=u_csamul_rca32_and1_25
.subckt fa a=u_csamul_rca32_and1_25 b=u_csamul_rca32_fa2_24_xor1 cin=u_csamul_rca32_fa1_24_or0 fa_xor1=u_csamul_rca32_fa1_25_xor1 fa_or0=u_csamul_rca32_fa1_25_or0
.subckt and_gate a=a[2] b=b[25] out=u_csamul_rca32_and2_25
.subckt fa a=u_csamul_rca32_and2_25 b=u_csamul_rca32_fa3_24_xor1 cin=u_csamul_rca32_fa2_24_or0 fa_xor1=u_csamul_rca32_fa2_25_xor1 fa_or0=u_csamul_rca32_fa2_25_or0
.subckt and_gate a=a[3] b=b[25] out=u_csamul_rca32_and3_25
.subckt fa a=u_csamul_rca32_and3_25 b=u_csamul_rca32_fa4_24_xor1 cin=u_csamul_rca32_fa3_24_or0 fa_xor1=u_csamul_rca32_fa3_25_xor1 fa_or0=u_csamul_rca32_fa3_25_or0
.subckt and_gate a=a[4] b=b[25] out=u_csamul_rca32_and4_25
.subckt fa a=u_csamul_rca32_and4_25 b=u_csamul_rca32_fa5_24_xor1 cin=u_csamul_rca32_fa4_24_or0 fa_xor1=u_csamul_rca32_fa4_25_xor1 fa_or0=u_csamul_rca32_fa4_25_or0
.subckt and_gate a=a[5] b=b[25] out=u_csamul_rca32_and5_25
.subckt fa a=u_csamul_rca32_and5_25 b=u_csamul_rca32_fa6_24_xor1 cin=u_csamul_rca32_fa5_24_or0 fa_xor1=u_csamul_rca32_fa5_25_xor1 fa_or0=u_csamul_rca32_fa5_25_or0
.subckt and_gate a=a[6] b=b[25] out=u_csamul_rca32_and6_25
.subckt fa a=u_csamul_rca32_and6_25 b=u_csamul_rca32_fa7_24_xor1 cin=u_csamul_rca32_fa6_24_or0 fa_xor1=u_csamul_rca32_fa6_25_xor1 fa_or0=u_csamul_rca32_fa6_25_or0
.subckt and_gate a=a[7] b=b[25] out=u_csamul_rca32_and7_25
.subckt fa a=u_csamul_rca32_and7_25 b=u_csamul_rca32_fa8_24_xor1 cin=u_csamul_rca32_fa7_24_or0 fa_xor1=u_csamul_rca32_fa7_25_xor1 fa_or0=u_csamul_rca32_fa7_25_or0
.subckt and_gate a=a[8] b=b[25] out=u_csamul_rca32_and8_25
.subckt fa a=u_csamul_rca32_and8_25 b=u_csamul_rca32_fa9_24_xor1 cin=u_csamul_rca32_fa8_24_or0 fa_xor1=u_csamul_rca32_fa8_25_xor1 fa_or0=u_csamul_rca32_fa8_25_or0
.subckt and_gate a=a[9] b=b[25] out=u_csamul_rca32_and9_25
.subckt fa a=u_csamul_rca32_and9_25 b=u_csamul_rca32_fa10_24_xor1 cin=u_csamul_rca32_fa9_24_or0 fa_xor1=u_csamul_rca32_fa9_25_xor1 fa_or0=u_csamul_rca32_fa9_25_or0
.subckt and_gate a=a[10] b=b[25] out=u_csamul_rca32_and10_25
.subckt fa a=u_csamul_rca32_and10_25 b=u_csamul_rca32_fa11_24_xor1 cin=u_csamul_rca32_fa10_24_or0 fa_xor1=u_csamul_rca32_fa10_25_xor1 fa_or0=u_csamul_rca32_fa10_25_or0
.subckt and_gate a=a[11] b=b[25] out=u_csamul_rca32_and11_25
.subckt fa a=u_csamul_rca32_and11_25 b=u_csamul_rca32_fa12_24_xor1 cin=u_csamul_rca32_fa11_24_or0 fa_xor1=u_csamul_rca32_fa11_25_xor1 fa_or0=u_csamul_rca32_fa11_25_or0
.subckt and_gate a=a[12] b=b[25] out=u_csamul_rca32_and12_25
.subckt fa a=u_csamul_rca32_and12_25 b=u_csamul_rca32_fa13_24_xor1 cin=u_csamul_rca32_fa12_24_or0 fa_xor1=u_csamul_rca32_fa12_25_xor1 fa_or0=u_csamul_rca32_fa12_25_or0
.subckt and_gate a=a[13] b=b[25] out=u_csamul_rca32_and13_25
.subckt fa a=u_csamul_rca32_and13_25 b=u_csamul_rca32_fa14_24_xor1 cin=u_csamul_rca32_fa13_24_or0 fa_xor1=u_csamul_rca32_fa13_25_xor1 fa_or0=u_csamul_rca32_fa13_25_or0
.subckt and_gate a=a[14] b=b[25] out=u_csamul_rca32_and14_25
.subckt fa a=u_csamul_rca32_and14_25 b=u_csamul_rca32_fa15_24_xor1 cin=u_csamul_rca32_fa14_24_or0 fa_xor1=u_csamul_rca32_fa14_25_xor1 fa_or0=u_csamul_rca32_fa14_25_or0
.subckt and_gate a=a[15] b=b[25] out=u_csamul_rca32_and15_25
.subckt fa a=u_csamul_rca32_and15_25 b=u_csamul_rca32_fa16_24_xor1 cin=u_csamul_rca32_fa15_24_or0 fa_xor1=u_csamul_rca32_fa15_25_xor1 fa_or0=u_csamul_rca32_fa15_25_or0
.subckt and_gate a=a[16] b=b[25] out=u_csamul_rca32_and16_25
.subckt fa a=u_csamul_rca32_and16_25 b=u_csamul_rca32_fa17_24_xor1 cin=u_csamul_rca32_fa16_24_or0 fa_xor1=u_csamul_rca32_fa16_25_xor1 fa_or0=u_csamul_rca32_fa16_25_or0
.subckt and_gate a=a[17] b=b[25] out=u_csamul_rca32_and17_25
.subckt fa a=u_csamul_rca32_and17_25 b=u_csamul_rca32_fa18_24_xor1 cin=u_csamul_rca32_fa17_24_or0 fa_xor1=u_csamul_rca32_fa17_25_xor1 fa_or0=u_csamul_rca32_fa17_25_or0
.subckt and_gate a=a[18] b=b[25] out=u_csamul_rca32_and18_25
.subckt fa a=u_csamul_rca32_and18_25 b=u_csamul_rca32_fa19_24_xor1 cin=u_csamul_rca32_fa18_24_or0 fa_xor1=u_csamul_rca32_fa18_25_xor1 fa_or0=u_csamul_rca32_fa18_25_or0
.subckt and_gate a=a[19] b=b[25] out=u_csamul_rca32_and19_25
.subckt fa a=u_csamul_rca32_and19_25 b=u_csamul_rca32_fa20_24_xor1 cin=u_csamul_rca32_fa19_24_or0 fa_xor1=u_csamul_rca32_fa19_25_xor1 fa_or0=u_csamul_rca32_fa19_25_or0
.subckt and_gate a=a[20] b=b[25] out=u_csamul_rca32_and20_25
.subckt fa a=u_csamul_rca32_and20_25 b=u_csamul_rca32_fa21_24_xor1 cin=u_csamul_rca32_fa20_24_or0 fa_xor1=u_csamul_rca32_fa20_25_xor1 fa_or0=u_csamul_rca32_fa20_25_or0
.subckt and_gate a=a[21] b=b[25] out=u_csamul_rca32_and21_25
.subckt fa a=u_csamul_rca32_and21_25 b=u_csamul_rca32_fa22_24_xor1 cin=u_csamul_rca32_fa21_24_or0 fa_xor1=u_csamul_rca32_fa21_25_xor1 fa_or0=u_csamul_rca32_fa21_25_or0
.subckt and_gate a=a[22] b=b[25] out=u_csamul_rca32_and22_25
.subckt fa a=u_csamul_rca32_and22_25 b=u_csamul_rca32_fa23_24_xor1 cin=u_csamul_rca32_fa22_24_or0 fa_xor1=u_csamul_rca32_fa22_25_xor1 fa_or0=u_csamul_rca32_fa22_25_or0
.subckt and_gate a=a[23] b=b[25] out=u_csamul_rca32_and23_25
.subckt fa a=u_csamul_rca32_and23_25 b=u_csamul_rca32_fa24_24_xor1 cin=u_csamul_rca32_fa23_24_or0 fa_xor1=u_csamul_rca32_fa23_25_xor1 fa_or0=u_csamul_rca32_fa23_25_or0
.subckt and_gate a=a[24] b=b[25] out=u_csamul_rca32_and24_25
.subckt fa a=u_csamul_rca32_and24_25 b=u_csamul_rca32_fa25_24_xor1 cin=u_csamul_rca32_fa24_24_or0 fa_xor1=u_csamul_rca32_fa24_25_xor1 fa_or0=u_csamul_rca32_fa24_25_or0
.subckt and_gate a=a[25] b=b[25] out=u_csamul_rca32_and25_25
.subckt fa a=u_csamul_rca32_and25_25 b=u_csamul_rca32_fa26_24_xor1 cin=u_csamul_rca32_fa25_24_or0 fa_xor1=u_csamul_rca32_fa25_25_xor1 fa_or0=u_csamul_rca32_fa25_25_or0
.subckt and_gate a=a[26] b=b[25] out=u_csamul_rca32_and26_25
.subckt fa a=u_csamul_rca32_and26_25 b=u_csamul_rca32_fa27_24_xor1 cin=u_csamul_rca32_fa26_24_or0 fa_xor1=u_csamul_rca32_fa26_25_xor1 fa_or0=u_csamul_rca32_fa26_25_or0
.subckt and_gate a=a[27] b=b[25] out=u_csamul_rca32_and27_25
.subckt fa a=u_csamul_rca32_and27_25 b=u_csamul_rca32_fa28_24_xor1 cin=u_csamul_rca32_fa27_24_or0 fa_xor1=u_csamul_rca32_fa27_25_xor1 fa_or0=u_csamul_rca32_fa27_25_or0
.subckt and_gate a=a[28] b=b[25] out=u_csamul_rca32_and28_25
.subckt fa a=u_csamul_rca32_and28_25 b=u_csamul_rca32_fa29_24_xor1 cin=u_csamul_rca32_fa28_24_or0 fa_xor1=u_csamul_rca32_fa28_25_xor1 fa_or0=u_csamul_rca32_fa28_25_or0
.subckt and_gate a=a[29] b=b[25] out=u_csamul_rca32_and29_25
.subckt fa a=u_csamul_rca32_and29_25 b=u_csamul_rca32_fa30_24_xor1 cin=u_csamul_rca32_fa29_24_or0 fa_xor1=u_csamul_rca32_fa29_25_xor1 fa_or0=u_csamul_rca32_fa29_25_or0
.subckt and_gate a=a[30] b=b[25] out=u_csamul_rca32_and30_25
.subckt fa a=u_csamul_rca32_and30_25 b=u_csamul_rca32_and31_24 cin=u_csamul_rca32_fa30_24_or0 fa_xor1=u_csamul_rca32_fa30_25_xor1 fa_or0=u_csamul_rca32_fa30_25_or0
.subckt and_gate a=a[31] b=b[25] out=u_csamul_rca32_and31_25
.subckt and_gate a=a[0] b=b[26] out=u_csamul_rca32_and0_26
.subckt fa a=u_csamul_rca32_and0_26 b=u_csamul_rca32_fa1_25_xor1 cin=u_csamul_rca32_fa0_25_or0 fa_xor1=u_csamul_rca32_fa0_26_xor1 fa_or0=u_csamul_rca32_fa0_26_or0
.subckt and_gate a=a[1] b=b[26] out=u_csamul_rca32_and1_26
.subckt fa a=u_csamul_rca32_and1_26 b=u_csamul_rca32_fa2_25_xor1 cin=u_csamul_rca32_fa1_25_or0 fa_xor1=u_csamul_rca32_fa1_26_xor1 fa_or0=u_csamul_rca32_fa1_26_or0
.subckt and_gate a=a[2] b=b[26] out=u_csamul_rca32_and2_26
.subckt fa a=u_csamul_rca32_and2_26 b=u_csamul_rca32_fa3_25_xor1 cin=u_csamul_rca32_fa2_25_or0 fa_xor1=u_csamul_rca32_fa2_26_xor1 fa_or0=u_csamul_rca32_fa2_26_or0
.subckt and_gate a=a[3] b=b[26] out=u_csamul_rca32_and3_26
.subckt fa a=u_csamul_rca32_and3_26 b=u_csamul_rca32_fa4_25_xor1 cin=u_csamul_rca32_fa3_25_or0 fa_xor1=u_csamul_rca32_fa3_26_xor1 fa_or0=u_csamul_rca32_fa3_26_or0
.subckt and_gate a=a[4] b=b[26] out=u_csamul_rca32_and4_26
.subckt fa a=u_csamul_rca32_and4_26 b=u_csamul_rca32_fa5_25_xor1 cin=u_csamul_rca32_fa4_25_or0 fa_xor1=u_csamul_rca32_fa4_26_xor1 fa_or0=u_csamul_rca32_fa4_26_or0
.subckt and_gate a=a[5] b=b[26] out=u_csamul_rca32_and5_26
.subckt fa a=u_csamul_rca32_and5_26 b=u_csamul_rca32_fa6_25_xor1 cin=u_csamul_rca32_fa5_25_or0 fa_xor1=u_csamul_rca32_fa5_26_xor1 fa_or0=u_csamul_rca32_fa5_26_or0
.subckt and_gate a=a[6] b=b[26] out=u_csamul_rca32_and6_26
.subckt fa a=u_csamul_rca32_and6_26 b=u_csamul_rca32_fa7_25_xor1 cin=u_csamul_rca32_fa6_25_or0 fa_xor1=u_csamul_rca32_fa6_26_xor1 fa_or0=u_csamul_rca32_fa6_26_or0
.subckt and_gate a=a[7] b=b[26] out=u_csamul_rca32_and7_26
.subckt fa a=u_csamul_rca32_and7_26 b=u_csamul_rca32_fa8_25_xor1 cin=u_csamul_rca32_fa7_25_or0 fa_xor1=u_csamul_rca32_fa7_26_xor1 fa_or0=u_csamul_rca32_fa7_26_or0
.subckt and_gate a=a[8] b=b[26] out=u_csamul_rca32_and8_26
.subckt fa a=u_csamul_rca32_and8_26 b=u_csamul_rca32_fa9_25_xor1 cin=u_csamul_rca32_fa8_25_or0 fa_xor1=u_csamul_rca32_fa8_26_xor1 fa_or0=u_csamul_rca32_fa8_26_or0
.subckt and_gate a=a[9] b=b[26] out=u_csamul_rca32_and9_26
.subckt fa a=u_csamul_rca32_and9_26 b=u_csamul_rca32_fa10_25_xor1 cin=u_csamul_rca32_fa9_25_or0 fa_xor1=u_csamul_rca32_fa9_26_xor1 fa_or0=u_csamul_rca32_fa9_26_or0
.subckt and_gate a=a[10] b=b[26] out=u_csamul_rca32_and10_26
.subckt fa a=u_csamul_rca32_and10_26 b=u_csamul_rca32_fa11_25_xor1 cin=u_csamul_rca32_fa10_25_or0 fa_xor1=u_csamul_rca32_fa10_26_xor1 fa_or0=u_csamul_rca32_fa10_26_or0
.subckt and_gate a=a[11] b=b[26] out=u_csamul_rca32_and11_26
.subckt fa a=u_csamul_rca32_and11_26 b=u_csamul_rca32_fa12_25_xor1 cin=u_csamul_rca32_fa11_25_or0 fa_xor1=u_csamul_rca32_fa11_26_xor1 fa_or0=u_csamul_rca32_fa11_26_or0
.subckt and_gate a=a[12] b=b[26] out=u_csamul_rca32_and12_26
.subckt fa a=u_csamul_rca32_and12_26 b=u_csamul_rca32_fa13_25_xor1 cin=u_csamul_rca32_fa12_25_or0 fa_xor1=u_csamul_rca32_fa12_26_xor1 fa_or0=u_csamul_rca32_fa12_26_or0
.subckt and_gate a=a[13] b=b[26] out=u_csamul_rca32_and13_26
.subckt fa a=u_csamul_rca32_and13_26 b=u_csamul_rca32_fa14_25_xor1 cin=u_csamul_rca32_fa13_25_or0 fa_xor1=u_csamul_rca32_fa13_26_xor1 fa_or0=u_csamul_rca32_fa13_26_or0
.subckt and_gate a=a[14] b=b[26] out=u_csamul_rca32_and14_26
.subckt fa a=u_csamul_rca32_and14_26 b=u_csamul_rca32_fa15_25_xor1 cin=u_csamul_rca32_fa14_25_or0 fa_xor1=u_csamul_rca32_fa14_26_xor1 fa_or0=u_csamul_rca32_fa14_26_or0
.subckt and_gate a=a[15] b=b[26] out=u_csamul_rca32_and15_26
.subckt fa a=u_csamul_rca32_and15_26 b=u_csamul_rca32_fa16_25_xor1 cin=u_csamul_rca32_fa15_25_or0 fa_xor1=u_csamul_rca32_fa15_26_xor1 fa_or0=u_csamul_rca32_fa15_26_or0
.subckt and_gate a=a[16] b=b[26] out=u_csamul_rca32_and16_26
.subckt fa a=u_csamul_rca32_and16_26 b=u_csamul_rca32_fa17_25_xor1 cin=u_csamul_rca32_fa16_25_or0 fa_xor1=u_csamul_rca32_fa16_26_xor1 fa_or0=u_csamul_rca32_fa16_26_or0
.subckt and_gate a=a[17] b=b[26] out=u_csamul_rca32_and17_26
.subckt fa a=u_csamul_rca32_and17_26 b=u_csamul_rca32_fa18_25_xor1 cin=u_csamul_rca32_fa17_25_or0 fa_xor1=u_csamul_rca32_fa17_26_xor1 fa_or0=u_csamul_rca32_fa17_26_or0
.subckt and_gate a=a[18] b=b[26] out=u_csamul_rca32_and18_26
.subckt fa a=u_csamul_rca32_and18_26 b=u_csamul_rca32_fa19_25_xor1 cin=u_csamul_rca32_fa18_25_or0 fa_xor1=u_csamul_rca32_fa18_26_xor1 fa_or0=u_csamul_rca32_fa18_26_or0
.subckt and_gate a=a[19] b=b[26] out=u_csamul_rca32_and19_26
.subckt fa a=u_csamul_rca32_and19_26 b=u_csamul_rca32_fa20_25_xor1 cin=u_csamul_rca32_fa19_25_or0 fa_xor1=u_csamul_rca32_fa19_26_xor1 fa_or0=u_csamul_rca32_fa19_26_or0
.subckt and_gate a=a[20] b=b[26] out=u_csamul_rca32_and20_26
.subckt fa a=u_csamul_rca32_and20_26 b=u_csamul_rca32_fa21_25_xor1 cin=u_csamul_rca32_fa20_25_or0 fa_xor1=u_csamul_rca32_fa20_26_xor1 fa_or0=u_csamul_rca32_fa20_26_or0
.subckt and_gate a=a[21] b=b[26] out=u_csamul_rca32_and21_26
.subckt fa a=u_csamul_rca32_and21_26 b=u_csamul_rca32_fa22_25_xor1 cin=u_csamul_rca32_fa21_25_or0 fa_xor1=u_csamul_rca32_fa21_26_xor1 fa_or0=u_csamul_rca32_fa21_26_or0
.subckt and_gate a=a[22] b=b[26] out=u_csamul_rca32_and22_26
.subckt fa a=u_csamul_rca32_and22_26 b=u_csamul_rca32_fa23_25_xor1 cin=u_csamul_rca32_fa22_25_or0 fa_xor1=u_csamul_rca32_fa22_26_xor1 fa_or0=u_csamul_rca32_fa22_26_or0
.subckt and_gate a=a[23] b=b[26] out=u_csamul_rca32_and23_26
.subckt fa a=u_csamul_rca32_and23_26 b=u_csamul_rca32_fa24_25_xor1 cin=u_csamul_rca32_fa23_25_or0 fa_xor1=u_csamul_rca32_fa23_26_xor1 fa_or0=u_csamul_rca32_fa23_26_or0
.subckt and_gate a=a[24] b=b[26] out=u_csamul_rca32_and24_26
.subckt fa a=u_csamul_rca32_and24_26 b=u_csamul_rca32_fa25_25_xor1 cin=u_csamul_rca32_fa24_25_or0 fa_xor1=u_csamul_rca32_fa24_26_xor1 fa_or0=u_csamul_rca32_fa24_26_or0
.subckt and_gate a=a[25] b=b[26] out=u_csamul_rca32_and25_26
.subckt fa a=u_csamul_rca32_and25_26 b=u_csamul_rca32_fa26_25_xor1 cin=u_csamul_rca32_fa25_25_or0 fa_xor1=u_csamul_rca32_fa25_26_xor1 fa_or0=u_csamul_rca32_fa25_26_or0
.subckt and_gate a=a[26] b=b[26] out=u_csamul_rca32_and26_26
.subckt fa a=u_csamul_rca32_and26_26 b=u_csamul_rca32_fa27_25_xor1 cin=u_csamul_rca32_fa26_25_or0 fa_xor1=u_csamul_rca32_fa26_26_xor1 fa_or0=u_csamul_rca32_fa26_26_or0
.subckt and_gate a=a[27] b=b[26] out=u_csamul_rca32_and27_26
.subckt fa a=u_csamul_rca32_and27_26 b=u_csamul_rca32_fa28_25_xor1 cin=u_csamul_rca32_fa27_25_or0 fa_xor1=u_csamul_rca32_fa27_26_xor1 fa_or0=u_csamul_rca32_fa27_26_or0
.subckt and_gate a=a[28] b=b[26] out=u_csamul_rca32_and28_26
.subckt fa a=u_csamul_rca32_and28_26 b=u_csamul_rca32_fa29_25_xor1 cin=u_csamul_rca32_fa28_25_or0 fa_xor1=u_csamul_rca32_fa28_26_xor1 fa_or0=u_csamul_rca32_fa28_26_or0
.subckt and_gate a=a[29] b=b[26] out=u_csamul_rca32_and29_26
.subckt fa a=u_csamul_rca32_and29_26 b=u_csamul_rca32_fa30_25_xor1 cin=u_csamul_rca32_fa29_25_or0 fa_xor1=u_csamul_rca32_fa29_26_xor1 fa_or0=u_csamul_rca32_fa29_26_or0
.subckt and_gate a=a[30] b=b[26] out=u_csamul_rca32_and30_26
.subckt fa a=u_csamul_rca32_and30_26 b=u_csamul_rca32_and31_25 cin=u_csamul_rca32_fa30_25_or0 fa_xor1=u_csamul_rca32_fa30_26_xor1 fa_or0=u_csamul_rca32_fa30_26_or0
.subckt and_gate a=a[31] b=b[26] out=u_csamul_rca32_and31_26
.subckt and_gate a=a[0] b=b[27] out=u_csamul_rca32_and0_27
.subckt fa a=u_csamul_rca32_and0_27 b=u_csamul_rca32_fa1_26_xor1 cin=u_csamul_rca32_fa0_26_or0 fa_xor1=u_csamul_rca32_fa0_27_xor1 fa_or0=u_csamul_rca32_fa0_27_or0
.subckt and_gate a=a[1] b=b[27] out=u_csamul_rca32_and1_27
.subckt fa a=u_csamul_rca32_and1_27 b=u_csamul_rca32_fa2_26_xor1 cin=u_csamul_rca32_fa1_26_or0 fa_xor1=u_csamul_rca32_fa1_27_xor1 fa_or0=u_csamul_rca32_fa1_27_or0
.subckt and_gate a=a[2] b=b[27] out=u_csamul_rca32_and2_27
.subckt fa a=u_csamul_rca32_and2_27 b=u_csamul_rca32_fa3_26_xor1 cin=u_csamul_rca32_fa2_26_or0 fa_xor1=u_csamul_rca32_fa2_27_xor1 fa_or0=u_csamul_rca32_fa2_27_or0
.subckt and_gate a=a[3] b=b[27] out=u_csamul_rca32_and3_27
.subckt fa a=u_csamul_rca32_and3_27 b=u_csamul_rca32_fa4_26_xor1 cin=u_csamul_rca32_fa3_26_or0 fa_xor1=u_csamul_rca32_fa3_27_xor1 fa_or0=u_csamul_rca32_fa3_27_or0
.subckt and_gate a=a[4] b=b[27] out=u_csamul_rca32_and4_27
.subckt fa a=u_csamul_rca32_and4_27 b=u_csamul_rca32_fa5_26_xor1 cin=u_csamul_rca32_fa4_26_or0 fa_xor1=u_csamul_rca32_fa4_27_xor1 fa_or0=u_csamul_rca32_fa4_27_or0
.subckt and_gate a=a[5] b=b[27] out=u_csamul_rca32_and5_27
.subckt fa a=u_csamul_rca32_and5_27 b=u_csamul_rca32_fa6_26_xor1 cin=u_csamul_rca32_fa5_26_or0 fa_xor1=u_csamul_rca32_fa5_27_xor1 fa_or0=u_csamul_rca32_fa5_27_or0
.subckt and_gate a=a[6] b=b[27] out=u_csamul_rca32_and6_27
.subckt fa a=u_csamul_rca32_and6_27 b=u_csamul_rca32_fa7_26_xor1 cin=u_csamul_rca32_fa6_26_or0 fa_xor1=u_csamul_rca32_fa6_27_xor1 fa_or0=u_csamul_rca32_fa6_27_or0
.subckt and_gate a=a[7] b=b[27] out=u_csamul_rca32_and7_27
.subckt fa a=u_csamul_rca32_and7_27 b=u_csamul_rca32_fa8_26_xor1 cin=u_csamul_rca32_fa7_26_or0 fa_xor1=u_csamul_rca32_fa7_27_xor1 fa_or0=u_csamul_rca32_fa7_27_or0
.subckt and_gate a=a[8] b=b[27] out=u_csamul_rca32_and8_27
.subckt fa a=u_csamul_rca32_and8_27 b=u_csamul_rca32_fa9_26_xor1 cin=u_csamul_rca32_fa8_26_or0 fa_xor1=u_csamul_rca32_fa8_27_xor1 fa_or0=u_csamul_rca32_fa8_27_or0
.subckt and_gate a=a[9] b=b[27] out=u_csamul_rca32_and9_27
.subckt fa a=u_csamul_rca32_and9_27 b=u_csamul_rca32_fa10_26_xor1 cin=u_csamul_rca32_fa9_26_or0 fa_xor1=u_csamul_rca32_fa9_27_xor1 fa_or0=u_csamul_rca32_fa9_27_or0
.subckt and_gate a=a[10] b=b[27] out=u_csamul_rca32_and10_27
.subckt fa a=u_csamul_rca32_and10_27 b=u_csamul_rca32_fa11_26_xor1 cin=u_csamul_rca32_fa10_26_or0 fa_xor1=u_csamul_rca32_fa10_27_xor1 fa_or0=u_csamul_rca32_fa10_27_or0
.subckt and_gate a=a[11] b=b[27] out=u_csamul_rca32_and11_27
.subckt fa a=u_csamul_rca32_and11_27 b=u_csamul_rca32_fa12_26_xor1 cin=u_csamul_rca32_fa11_26_or0 fa_xor1=u_csamul_rca32_fa11_27_xor1 fa_or0=u_csamul_rca32_fa11_27_or0
.subckt and_gate a=a[12] b=b[27] out=u_csamul_rca32_and12_27
.subckt fa a=u_csamul_rca32_and12_27 b=u_csamul_rca32_fa13_26_xor1 cin=u_csamul_rca32_fa12_26_or0 fa_xor1=u_csamul_rca32_fa12_27_xor1 fa_or0=u_csamul_rca32_fa12_27_or0
.subckt and_gate a=a[13] b=b[27] out=u_csamul_rca32_and13_27
.subckt fa a=u_csamul_rca32_and13_27 b=u_csamul_rca32_fa14_26_xor1 cin=u_csamul_rca32_fa13_26_or0 fa_xor1=u_csamul_rca32_fa13_27_xor1 fa_or0=u_csamul_rca32_fa13_27_or0
.subckt and_gate a=a[14] b=b[27] out=u_csamul_rca32_and14_27
.subckt fa a=u_csamul_rca32_and14_27 b=u_csamul_rca32_fa15_26_xor1 cin=u_csamul_rca32_fa14_26_or0 fa_xor1=u_csamul_rca32_fa14_27_xor1 fa_or0=u_csamul_rca32_fa14_27_or0
.subckt and_gate a=a[15] b=b[27] out=u_csamul_rca32_and15_27
.subckt fa a=u_csamul_rca32_and15_27 b=u_csamul_rca32_fa16_26_xor1 cin=u_csamul_rca32_fa15_26_or0 fa_xor1=u_csamul_rca32_fa15_27_xor1 fa_or0=u_csamul_rca32_fa15_27_or0
.subckt and_gate a=a[16] b=b[27] out=u_csamul_rca32_and16_27
.subckt fa a=u_csamul_rca32_and16_27 b=u_csamul_rca32_fa17_26_xor1 cin=u_csamul_rca32_fa16_26_or0 fa_xor1=u_csamul_rca32_fa16_27_xor1 fa_or0=u_csamul_rca32_fa16_27_or0
.subckt and_gate a=a[17] b=b[27] out=u_csamul_rca32_and17_27
.subckt fa a=u_csamul_rca32_and17_27 b=u_csamul_rca32_fa18_26_xor1 cin=u_csamul_rca32_fa17_26_or0 fa_xor1=u_csamul_rca32_fa17_27_xor1 fa_or0=u_csamul_rca32_fa17_27_or0
.subckt and_gate a=a[18] b=b[27] out=u_csamul_rca32_and18_27
.subckt fa a=u_csamul_rca32_and18_27 b=u_csamul_rca32_fa19_26_xor1 cin=u_csamul_rca32_fa18_26_or0 fa_xor1=u_csamul_rca32_fa18_27_xor1 fa_or0=u_csamul_rca32_fa18_27_or0
.subckt and_gate a=a[19] b=b[27] out=u_csamul_rca32_and19_27
.subckt fa a=u_csamul_rca32_and19_27 b=u_csamul_rca32_fa20_26_xor1 cin=u_csamul_rca32_fa19_26_or0 fa_xor1=u_csamul_rca32_fa19_27_xor1 fa_or0=u_csamul_rca32_fa19_27_or0
.subckt and_gate a=a[20] b=b[27] out=u_csamul_rca32_and20_27
.subckt fa a=u_csamul_rca32_and20_27 b=u_csamul_rca32_fa21_26_xor1 cin=u_csamul_rca32_fa20_26_or0 fa_xor1=u_csamul_rca32_fa20_27_xor1 fa_or0=u_csamul_rca32_fa20_27_or0
.subckt and_gate a=a[21] b=b[27] out=u_csamul_rca32_and21_27
.subckt fa a=u_csamul_rca32_and21_27 b=u_csamul_rca32_fa22_26_xor1 cin=u_csamul_rca32_fa21_26_or0 fa_xor1=u_csamul_rca32_fa21_27_xor1 fa_or0=u_csamul_rca32_fa21_27_or0
.subckt and_gate a=a[22] b=b[27] out=u_csamul_rca32_and22_27
.subckt fa a=u_csamul_rca32_and22_27 b=u_csamul_rca32_fa23_26_xor1 cin=u_csamul_rca32_fa22_26_or0 fa_xor1=u_csamul_rca32_fa22_27_xor1 fa_or0=u_csamul_rca32_fa22_27_or0
.subckt and_gate a=a[23] b=b[27] out=u_csamul_rca32_and23_27
.subckt fa a=u_csamul_rca32_and23_27 b=u_csamul_rca32_fa24_26_xor1 cin=u_csamul_rca32_fa23_26_or0 fa_xor1=u_csamul_rca32_fa23_27_xor1 fa_or0=u_csamul_rca32_fa23_27_or0
.subckt and_gate a=a[24] b=b[27] out=u_csamul_rca32_and24_27
.subckt fa a=u_csamul_rca32_and24_27 b=u_csamul_rca32_fa25_26_xor1 cin=u_csamul_rca32_fa24_26_or0 fa_xor1=u_csamul_rca32_fa24_27_xor1 fa_or0=u_csamul_rca32_fa24_27_or0
.subckt and_gate a=a[25] b=b[27] out=u_csamul_rca32_and25_27
.subckt fa a=u_csamul_rca32_and25_27 b=u_csamul_rca32_fa26_26_xor1 cin=u_csamul_rca32_fa25_26_or0 fa_xor1=u_csamul_rca32_fa25_27_xor1 fa_or0=u_csamul_rca32_fa25_27_or0
.subckt and_gate a=a[26] b=b[27] out=u_csamul_rca32_and26_27
.subckt fa a=u_csamul_rca32_and26_27 b=u_csamul_rca32_fa27_26_xor1 cin=u_csamul_rca32_fa26_26_or0 fa_xor1=u_csamul_rca32_fa26_27_xor1 fa_or0=u_csamul_rca32_fa26_27_or0
.subckt and_gate a=a[27] b=b[27] out=u_csamul_rca32_and27_27
.subckt fa a=u_csamul_rca32_and27_27 b=u_csamul_rca32_fa28_26_xor1 cin=u_csamul_rca32_fa27_26_or0 fa_xor1=u_csamul_rca32_fa27_27_xor1 fa_or0=u_csamul_rca32_fa27_27_or0
.subckt and_gate a=a[28] b=b[27] out=u_csamul_rca32_and28_27
.subckt fa a=u_csamul_rca32_and28_27 b=u_csamul_rca32_fa29_26_xor1 cin=u_csamul_rca32_fa28_26_or0 fa_xor1=u_csamul_rca32_fa28_27_xor1 fa_or0=u_csamul_rca32_fa28_27_or0
.subckt and_gate a=a[29] b=b[27] out=u_csamul_rca32_and29_27
.subckt fa a=u_csamul_rca32_and29_27 b=u_csamul_rca32_fa30_26_xor1 cin=u_csamul_rca32_fa29_26_or0 fa_xor1=u_csamul_rca32_fa29_27_xor1 fa_or0=u_csamul_rca32_fa29_27_or0
.subckt and_gate a=a[30] b=b[27] out=u_csamul_rca32_and30_27
.subckt fa a=u_csamul_rca32_and30_27 b=u_csamul_rca32_and31_26 cin=u_csamul_rca32_fa30_26_or0 fa_xor1=u_csamul_rca32_fa30_27_xor1 fa_or0=u_csamul_rca32_fa30_27_or0
.subckt and_gate a=a[31] b=b[27] out=u_csamul_rca32_and31_27
.subckt and_gate a=a[0] b=b[28] out=u_csamul_rca32_and0_28
.subckt fa a=u_csamul_rca32_and0_28 b=u_csamul_rca32_fa1_27_xor1 cin=u_csamul_rca32_fa0_27_or0 fa_xor1=u_csamul_rca32_fa0_28_xor1 fa_or0=u_csamul_rca32_fa0_28_or0
.subckt and_gate a=a[1] b=b[28] out=u_csamul_rca32_and1_28
.subckt fa a=u_csamul_rca32_and1_28 b=u_csamul_rca32_fa2_27_xor1 cin=u_csamul_rca32_fa1_27_or0 fa_xor1=u_csamul_rca32_fa1_28_xor1 fa_or0=u_csamul_rca32_fa1_28_or0
.subckt and_gate a=a[2] b=b[28] out=u_csamul_rca32_and2_28
.subckt fa a=u_csamul_rca32_and2_28 b=u_csamul_rca32_fa3_27_xor1 cin=u_csamul_rca32_fa2_27_or0 fa_xor1=u_csamul_rca32_fa2_28_xor1 fa_or0=u_csamul_rca32_fa2_28_or0
.subckt and_gate a=a[3] b=b[28] out=u_csamul_rca32_and3_28
.subckt fa a=u_csamul_rca32_and3_28 b=u_csamul_rca32_fa4_27_xor1 cin=u_csamul_rca32_fa3_27_or0 fa_xor1=u_csamul_rca32_fa3_28_xor1 fa_or0=u_csamul_rca32_fa3_28_or0
.subckt and_gate a=a[4] b=b[28] out=u_csamul_rca32_and4_28
.subckt fa a=u_csamul_rca32_and4_28 b=u_csamul_rca32_fa5_27_xor1 cin=u_csamul_rca32_fa4_27_or0 fa_xor1=u_csamul_rca32_fa4_28_xor1 fa_or0=u_csamul_rca32_fa4_28_or0
.subckt and_gate a=a[5] b=b[28] out=u_csamul_rca32_and5_28
.subckt fa a=u_csamul_rca32_and5_28 b=u_csamul_rca32_fa6_27_xor1 cin=u_csamul_rca32_fa5_27_or0 fa_xor1=u_csamul_rca32_fa5_28_xor1 fa_or0=u_csamul_rca32_fa5_28_or0
.subckt and_gate a=a[6] b=b[28] out=u_csamul_rca32_and6_28
.subckt fa a=u_csamul_rca32_and6_28 b=u_csamul_rca32_fa7_27_xor1 cin=u_csamul_rca32_fa6_27_or0 fa_xor1=u_csamul_rca32_fa6_28_xor1 fa_or0=u_csamul_rca32_fa6_28_or0
.subckt and_gate a=a[7] b=b[28] out=u_csamul_rca32_and7_28
.subckt fa a=u_csamul_rca32_and7_28 b=u_csamul_rca32_fa8_27_xor1 cin=u_csamul_rca32_fa7_27_or0 fa_xor1=u_csamul_rca32_fa7_28_xor1 fa_or0=u_csamul_rca32_fa7_28_or0
.subckt and_gate a=a[8] b=b[28] out=u_csamul_rca32_and8_28
.subckt fa a=u_csamul_rca32_and8_28 b=u_csamul_rca32_fa9_27_xor1 cin=u_csamul_rca32_fa8_27_or0 fa_xor1=u_csamul_rca32_fa8_28_xor1 fa_or0=u_csamul_rca32_fa8_28_or0
.subckt and_gate a=a[9] b=b[28] out=u_csamul_rca32_and9_28
.subckt fa a=u_csamul_rca32_and9_28 b=u_csamul_rca32_fa10_27_xor1 cin=u_csamul_rca32_fa9_27_or0 fa_xor1=u_csamul_rca32_fa9_28_xor1 fa_or0=u_csamul_rca32_fa9_28_or0
.subckt and_gate a=a[10] b=b[28] out=u_csamul_rca32_and10_28
.subckt fa a=u_csamul_rca32_and10_28 b=u_csamul_rca32_fa11_27_xor1 cin=u_csamul_rca32_fa10_27_or0 fa_xor1=u_csamul_rca32_fa10_28_xor1 fa_or0=u_csamul_rca32_fa10_28_or0
.subckt and_gate a=a[11] b=b[28] out=u_csamul_rca32_and11_28
.subckt fa a=u_csamul_rca32_and11_28 b=u_csamul_rca32_fa12_27_xor1 cin=u_csamul_rca32_fa11_27_or0 fa_xor1=u_csamul_rca32_fa11_28_xor1 fa_or0=u_csamul_rca32_fa11_28_or0
.subckt and_gate a=a[12] b=b[28] out=u_csamul_rca32_and12_28
.subckt fa a=u_csamul_rca32_and12_28 b=u_csamul_rca32_fa13_27_xor1 cin=u_csamul_rca32_fa12_27_or0 fa_xor1=u_csamul_rca32_fa12_28_xor1 fa_or0=u_csamul_rca32_fa12_28_or0
.subckt and_gate a=a[13] b=b[28] out=u_csamul_rca32_and13_28
.subckt fa a=u_csamul_rca32_and13_28 b=u_csamul_rca32_fa14_27_xor1 cin=u_csamul_rca32_fa13_27_or0 fa_xor1=u_csamul_rca32_fa13_28_xor1 fa_or0=u_csamul_rca32_fa13_28_or0
.subckt and_gate a=a[14] b=b[28] out=u_csamul_rca32_and14_28
.subckt fa a=u_csamul_rca32_and14_28 b=u_csamul_rca32_fa15_27_xor1 cin=u_csamul_rca32_fa14_27_or0 fa_xor1=u_csamul_rca32_fa14_28_xor1 fa_or0=u_csamul_rca32_fa14_28_or0
.subckt and_gate a=a[15] b=b[28] out=u_csamul_rca32_and15_28
.subckt fa a=u_csamul_rca32_and15_28 b=u_csamul_rca32_fa16_27_xor1 cin=u_csamul_rca32_fa15_27_or0 fa_xor1=u_csamul_rca32_fa15_28_xor1 fa_or0=u_csamul_rca32_fa15_28_or0
.subckt and_gate a=a[16] b=b[28] out=u_csamul_rca32_and16_28
.subckt fa a=u_csamul_rca32_and16_28 b=u_csamul_rca32_fa17_27_xor1 cin=u_csamul_rca32_fa16_27_or0 fa_xor1=u_csamul_rca32_fa16_28_xor1 fa_or0=u_csamul_rca32_fa16_28_or0
.subckt and_gate a=a[17] b=b[28] out=u_csamul_rca32_and17_28
.subckt fa a=u_csamul_rca32_and17_28 b=u_csamul_rca32_fa18_27_xor1 cin=u_csamul_rca32_fa17_27_or0 fa_xor1=u_csamul_rca32_fa17_28_xor1 fa_or0=u_csamul_rca32_fa17_28_or0
.subckt and_gate a=a[18] b=b[28] out=u_csamul_rca32_and18_28
.subckt fa a=u_csamul_rca32_and18_28 b=u_csamul_rca32_fa19_27_xor1 cin=u_csamul_rca32_fa18_27_or0 fa_xor1=u_csamul_rca32_fa18_28_xor1 fa_or0=u_csamul_rca32_fa18_28_or0
.subckt and_gate a=a[19] b=b[28] out=u_csamul_rca32_and19_28
.subckt fa a=u_csamul_rca32_and19_28 b=u_csamul_rca32_fa20_27_xor1 cin=u_csamul_rca32_fa19_27_or0 fa_xor1=u_csamul_rca32_fa19_28_xor1 fa_or0=u_csamul_rca32_fa19_28_or0
.subckt and_gate a=a[20] b=b[28] out=u_csamul_rca32_and20_28
.subckt fa a=u_csamul_rca32_and20_28 b=u_csamul_rca32_fa21_27_xor1 cin=u_csamul_rca32_fa20_27_or0 fa_xor1=u_csamul_rca32_fa20_28_xor1 fa_or0=u_csamul_rca32_fa20_28_or0
.subckt and_gate a=a[21] b=b[28] out=u_csamul_rca32_and21_28
.subckt fa a=u_csamul_rca32_and21_28 b=u_csamul_rca32_fa22_27_xor1 cin=u_csamul_rca32_fa21_27_or0 fa_xor1=u_csamul_rca32_fa21_28_xor1 fa_or0=u_csamul_rca32_fa21_28_or0
.subckt and_gate a=a[22] b=b[28] out=u_csamul_rca32_and22_28
.subckt fa a=u_csamul_rca32_and22_28 b=u_csamul_rca32_fa23_27_xor1 cin=u_csamul_rca32_fa22_27_or0 fa_xor1=u_csamul_rca32_fa22_28_xor1 fa_or0=u_csamul_rca32_fa22_28_or0
.subckt and_gate a=a[23] b=b[28] out=u_csamul_rca32_and23_28
.subckt fa a=u_csamul_rca32_and23_28 b=u_csamul_rca32_fa24_27_xor1 cin=u_csamul_rca32_fa23_27_or0 fa_xor1=u_csamul_rca32_fa23_28_xor1 fa_or0=u_csamul_rca32_fa23_28_or0
.subckt and_gate a=a[24] b=b[28] out=u_csamul_rca32_and24_28
.subckt fa a=u_csamul_rca32_and24_28 b=u_csamul_rca32_fa25_27_xor1 cin=u_csamul_rca32_fa24_27_or0 fa_xor1=u_csamul_rca32_fa24_28_xor1 fa_or0=u_csamul_rca32_fa24_28_or0
.subckt and_gate a=a[25] b=b[28] out=u_csamul_rca32_and25_28
.subckt fa a=u_csamul_rca32_and25_28 b=u_csamul_rca32_fa26_27_xor1 cin=u_csamul_rca32_fa25_27_or0 fa_xor1=u_csamul_rca32_fa25_28_xor1 fa_or0=u_csamul_rca32_fa25_28_or0
.subckt and_gate a=a[26] b=b[28] out=u_csamul_rca32_and26_28
.subckt fa a=u_csamul_rca32_and26_28 b=u_csamul_rca32_fa27_27_xor1 cin=u_csamul_rca32_fa26_27_or0 fa_xor1=u_csamul_rca32_fa26_28_xor1 fa_or0=u_csamul_rca32_fa26_28_or0
.subckt and_gate a=a[27] b=b[28] out=u_csamul_rca32_and27_28
.subckt fa a=u_csamul_rca32_and27_28 b=u_csamul_rca32_fa28_27_xor1 cin=u_csamul_rca32_fa27_27_or0 fa_xor1=u_csamul_rca32_fa27_28_xor1 fa_or0=u_csamul_rca32_fa27_28_or0
.subckt and_gate a=a[28] b=b[28] out=u_csamul_rca32_and28_28
.subckt fa a=u_csamul_rca32_and28_28 b=u_csamul_rca32_fa29_27_xor1 cin=u_csamul_rca32_fa28_27_or0 fa_xor1=u_csamul_rca32_fa28_28_xor1 fa_or0=u_csamul_rca32_fa28_28_or0
.subckt and_gate a=a[29] b=b[28] out=u_csamul_rca32_and29_28
.subckt fa a=u_csamul_rca32_and29_28 b=u_csamul_rca32_fa30_27_xor1 cin=u_csamul_rca32_fa29_27_or0 fa_xor1=u_csamul_rca32_fa29_28_xor1 fa_or0=u_csamul_rca32_fa29_28_or0
.subckt and_gate a=a[30] b=b[28] out=u_csamul_rca32_and30_28
.subckt fa a=u_csamul_rca32_and30_28 b=u_csamul_rca32_and31_27 cin=u_csamul_rca32_fa30_27_or0 fa_xor1=u_csamul_rca32_fa30_28_xor1 fa_or0=u_csamul_rca32_fa30_28_or0
.subckt and_gate a=a[31] b=b[28] out=u_csamul_rca32_and31_28
.subckt and_gate a=a[0] b=b[29] out=u_csamul_rca32_and0_29
.subckt fa a=u_csamul_rca32_and0_29 b=u_csamul_rca32_fa1_28_xor1 cin=u_csamul_rca32_fa0_28_or0 fa_xor1=u_csamul_rca32_fa0_29_xor1 fa_or0=u_csamul_rca32_fa0_29_or0
.subckt and_gate a=a[1] b=b[29] out=u_csamul_rca32_and1_29
.subckt fa a=u_csamul_rca32_and1_29 b=u_csamul_rca32_fa2_28_xor1 cin=u_csamul_rca32_fa1_28_or0 fa_xor1=u_csamul_rca32_fa1_29_xor1 fa_or0=u_csamul_rca32_fa1_29_or0
.subckt and_gate a=a[2] b=b[29] out=u_csamul_rca32_and2_29
.subckt fa a=u_csamul_rca32_and2_29 b=u_csamul_rca32_fa3_28_xor1 cin=u_csamul_rca32_fa2_28_or0 fa_xor1=u_csamul_rca32_fa2_29_xor1 fa_or0=u_csamul_rca32_fa2_29_or0
.subckt and_gate a=a[3] b=b[29] out=u_csamul_rca32_and3_29
.subckt fa a=u_csamul_rca32_and3_29 b=u_csamul_rca32_fa4_28_xor1 cin=u_csamul_rca32_fa3_28_or0 fa_xor1=u_csamul_rca32_fa3_29_xor1 fa_or0=u_csamul_rca32_fa3_29_or0
.subckt and_gate a=a[4] b=b[29] out=u_csamul_rca32_and4_29
.subckt fa a=u_csamul_rca32_and4_29 b=u_csamul_rca32_fa5_28_xor1 cin=u_csamul_rca32_fa4_28_or0 fa_xor1=u_csamul_rca32_fa4_29_xor1 fa_or0=u_csamul_rca32_fa4_29_or0
.subckt and_gate a=a[5] b=b[29] out=u_csamul_rca32_and5_29
.subckt fa a=u_csamul_rca32_and5_29 b=u_csamul_rca32_fa6_28_xor1 cin=u_csamul_rca32_fa5_28_or0 fa_xor1=u_csamul_rca32_fa5_29_xor1 fa_or0=u_csamul_rca32_fa5_29_or0
.subckt and_gate a=a[6] b=b[29] out=u_csamul_rca32_and6_29
.subckt fa a=u_csamul_rca32_and6_29 b=u_csamul_rca32_fa7_28_xor1 cin=u_csamul_rca32_fa6_28_or0 fa_xor1=u_csamul_rca32_fa6_29_xor1 fa_or0=u_csamul_rca32_fa6_29_or0
.subckt and_gate a=a[7] b=b[29] out=u_csamul_rca32_and7_29
.subckt fa a=u_csamul_rca32_and7_29 b=u_csamul_rca32_fa8_28_xor1 cin=u_csamul_rca32_fa7_28_or0 fa_xor1=u_csamul_rca32_fa7_29_xor1 fa_or0=u_csamul_rca32_fa7_29_or0
.subckt and_gate a=a[8] b=b[29] out=u_csamul_rca32_and8_29
.subckt fa a=u_csamul_rca32_and8_29 b=u_csamul_rca32_fa9_28_xor1 cin=u_csamul_rca32_fa8_28_or0 fa_xor1=u_csamul_rca32_fa8_29_xor1 fa_or0=u_csamul_rca32_fa8_29_or0
.subckt and_gate a=a[9] b=b[29] out=u_csamul_rca32_and9_29
.subckt fa a=u_csamul_rca32_and9_29 b=u_csamul_rca32_fa10_28_xor1 cin=u_csamul_rca32_fa9_28_or0 fa_xor1=u_csamul_rca32_fa9_29_xor1 fa_or0=u_csamul_rca32_fa9_29_or0
.subckt and_gate a=a[10] b=b[29] out=u_csamul_rca32_and10_29
.subckt fa a=u_csamul_rca32_and10_29 b=u_csamul_rca32_fa11_28_xor1 cin=u_csamul_rca32_fa10_28_or0 fa_xor1=u_csamul_rca32_fa10_29_xor1 fa_or0=u_csamul_rca32_fa10_29_or0
.subckt and_gate a=a[11] b=b[29] out=u_csamul_rca32_and11_29
.subckt fa a=u_csamul_rca32_and11_29 b=u_csamul_rca32_fa12_28_xor1 cin=u_csamul_rca32_fa11_28_or0 fa_xor1=u_csamul_rca32_fa11_29_xor1 fa_or0=u_csamul_rca32_fa11_29_or0
.subckt and_gate a=a[12] b=b[29] out=u_csamul_rca32_and12_29
.subckt fa a=u_csamul_rca32_and12_29 b=u_csamul_rca32_fa13_28_xor1 cin=u_csamul_rca32_fa12_28_or0 fa_xor1=u_csamul_rca32_fa12_29_xor1 fa_or0=u_csamul_rca32_fa12_29_or0
.subckt and_gate a=a[13] b=b[29] out=u_csamul_rca32_and13_29
.subckt fa a=u_csamul_rca32_and13_29 b=u_csamul_rca32_fa14_28_xor1 cin=u_csamul_rca32_fa13_28_or0 fa_xor1=u_csamul_rca32_fa13_29_xor1 fa_or0=u_csamul_rca32_fa13_29_or0
.subckt and_gate a=a[14] b=b[29] out=u_csamul_rca32_and14_29
.subckt fa a=u_csamul_rca32_and14_29 b=u_csamul_rca32_fa15_28_xor1 cin=u_csamul_rca32_fa14_28_or0 fa_xor1=u_csamul_rca32_fa14_29_xor1 fa_or0=u_csamul_rca32_fa14_29_or0
.subckt and_gate a=a[15] b=b[29] out=u_csamul_rca32_and15_29
.subckt fa a=u_csamul_rca32_and15_29 b=u_csamul_rca32_fa16_28_xor1 cin=u_csamul_rca32_fa15_28_or0 fa_xor1=u_csamul_rca32_fa15_29_xor1 fa_or0=u_csamul_rca32_fa15_29_or0
.subckt and_gate a=a[16] b=b[29] out=u_csamul_rca32_and16_29
.subckt fa a=u_csamul_rca32_and16_29 b=u_csamul_rca32_fa17_28_xor1 cin=u_csamul_rca32_fa16_28_or0 fa_xor1=u_csamul_rca32_fa16_29_xor1 fa_or0=u_csamul_rca32_fa16_29_or0
.subckt and_gate a=a[17] b=b[29] out=u_csamul_rca32_and17_29
.subckt fa a=u_csamul_rca32_and17_29 b=u_csamul_rca32_fa18_28_xor1 cin=u_csamul_rca32_fa17_28_or0 fa_xor1=u_csamul_rca32_fa17_29_xor1 fa_or0=u_csamul_rca32_fa17_29_or0
.subckt and_gate a=a[18] b=b[29] out=u_csamul_rca32_and18_29
.subckt fa a=u_csamul_rca32_and18_29 b=u_csamul_rca32_fa19_28_xor1 cin=u_csamul_rca32_fa18_28_or0 fa_xor1=u_csamul_rca32_fa18_29_xor1 fa_or0=u_csamul_rca32_fa18_29_or0
.subckt and_gate a=a[19] b=b[29] out=u_csamul_rca32_and19_29
.subckt fa a=u_csamul_rca32_and19_29 b=u_csamul_rca32_fa20_28_xor1 cin=u_csamul_rca32_fa19_28_or0 fa_xor1=u_csamul_rca32_fa19_29_xor1 fa_or0=u_csamul_rca32_fa19_29_or0
.subckt and_gate a=a[20] b=b[29] out=u_csamul_rca32_and20_29
.subckt fa a=u_csamul_rca32_and20_29 b=u_csamul_rca32_fa21_28_xor1 cin=u_csamul_rca32_fa20_28_or0 fa_xor1=u_csamul_rca32_fa20_29_xor1 fa_or0=u_csamul_rca32_fa20_29_or0
.subckt and_gate a=a[21] b=b[29] out=u_csamul_rca32_and21_29
.subckt fa a=u_csamul_rca32_and21_29 b=u_csamul_rca32_fa22_28_xor1 cin=u_csamul_rca32_fa21_28_or0 fa_xor1=u_csamul_rca32_fa21_29_xor1 fa_or0=u_csamul_rca32_fa21_29_or0
.subckt and_gate a=a[22] b=b[29] out=u_csamul_rca32_and22_29
.subckt fa a=u_csamul_rca32_and22_29 b=u_csamul_rca32_fa23_28_xor1 cin=u_csamul_rca32_fa22_28_or0 fa_xor1=u_csamul_rca32_fa22_29_xor1 fa_or0=u_csamul_rca32_fa22_29_or0
.subckt and_gate a=a[23] b=b[29] out=u_csamul_rca32_and23_29
.subckt fa a=u_csamul_rca32_and23_29 b=u_csamul_rca32_fa24_28_xor1 cin=u_csamul_rca32_fa23_28_or0 fa_xor1=u_csamul_rca32_fa23_29_xor1 fa_or0=u_csamul_rca32_fa23_29_or0
.subckt and_gate a=a[24] b=b[29] out=u_csamul_rca32_and24_29
.subckt fa a=u_csamul_rca32_and24_29 b=u_csamul_rca32_fa25_28_xor1 cin=u_csamul_rca32_fa24_28_or0 fa_xor1=u_csamul_rca32_fa24_29_xor1 fa_or0=u_csamul_rca32_fa24_29_or0
.subckt and_gate a=a[25] b=b[29] out=u_csamul_rca32_and25_29
.subckt fa a=u_csamul_rca32_and25_29 b=u_csamul_rca32_fa26_28_xor1 cin=u_csamul_rca32_fa25_28_or0 fa_xor1=u_csamul_rca32_fa25_29_xor1 fa_or0=u_csamul_rca32_fa25_29_or0
.subckt and_gate a=a[26] b=b[29] out=u_csamul_rca32_and26_29
.subckt fa a=u_csamul_rca32_and26_29 b=u_csamul_rca32_fa27_28_xor1 cin=u_csamul_rca32_fa26_28_or0 fa_xor1=u_csamul_rca32_fa26_29_xor1 fa_or0=u_csamul_rca32_fa26_29_or0
.subckt and_gate a=a[27] b=b[29] out=u_csamul_rca32_and27_29
.subckt fa a=u_csamul_rca32_and27_29 b=u_csamul_rca32_fa28_28_xor1 cin=u_csamul_rca32_fa27_28_or0 fa_xor1=u_csamul_rca32_fa27_29_xor1 fa_or0=u_csamul_rca32_fa27_29_or0
.subckt and_gate a=a[28] b=b[29] out=u_csamul_rca32_and28_29
.subckt fa a=u_csamul_rca32_and28_29 b=u_csamul_rca32_fa29_28_xor1 cin=u_csamul_rca32_fa28_28_or0 fa_xor1=u_csamul_rca32_fa28_29_xor1 fa_or0=u_csamul_rca32_fa28_29_or0
.subckt and_gate a=a[29] b=b[29] out=u_csamul_rca32_and29_29
.subckt fa a=u_csamul_rca32_and29_29 b=u_csamul_rca32_fa30_28_xor1 cin=u_csamul_rca32_fa29_28_or0 fa_xor1=u_csamul_rca32_fa29_29_xor1 fa_or0=u_csamul_rca32_fa29_29_or0
.subckt and_gate a=a[30] b=b[29] out=u_csamul_rca32_and30_29
.subckt fa a=u_csamul_rca32_and30_29 b=u_csamul_rca32_and31_28 cin=u_csamul_rca32_fa30_28_or0 fa_xor1=u_csamul_rca32_fa30_29_xor1 fa_or0=u_csamul_rca32_fa30_29_or0
.subckt and_gate a=a[31] b=b[29] out=u_csamul_rca32_and31_29
.subckt and_gate a=a[0] b=b[30] out=u_csamul_rca32_and0_30
.subckt fa a=u_csamul_rca32_and0_30 b=u_csamul_rca32_fa1_29_xor1 cin=u_csamul_rca32_fa0_29_or0 fa_xor1=u_csamul_rca32_fa0_30_xor1 fa_or0=u_csamul_rca32_fa0_30_or0
.subckt and_gate a=a[1] b=b[30] out=u_csamul_rca32_and1_30
.subckt fa a=u_csamul_rca32_and1_30 b=u_csamul_rca32_fa2_29_xor1 cin=u_csamul_rca32_fa1_29_or0 fa_xor1=u_csamul_rca32_fa1_30_xor1 fa_or0=u_csamul_rca32_fa1_30_or0
.subckt and_gate a=a[2] b=b[30] out=u_csamul_rca32_and2_30
.subckt fa a=u_csamul_rca32_and2_30 b=u_csamul_rca32_fa3_29_xor1 cin=u_csamul_rca32_fa2_29_or0 fa_xor1=u_csamul_rca32_fa2_30_xor1 fa_or0=u_csamul_rca32_fa2_30_or0
.subckt and_gate a=a[3] b=b[30] out=u_csamul_rca32_and3_30
.subckt fa a=u_csamul_rca32_and3_30 b=u_csamul_rca32_fa4_29_xor1 cin=u_csamul_rca32_fa3_29_or0 fa_xor1=u_csamul_rca32_fa3_30_xor1 fa_or0=u_csamul_rca32_fa3_30_or0
.subckt and_gate a=a[4] b=b[30] out=u_csamul_rca32_and4_30
.subckt fa a=u_csamul_rca32_and4_30 b=u_csamul_rca32_fa5_29_xor1 cin=u_csamul_rca32_fa4_29_or0 fa_xor1=u_csamul_rca32_fa4_30_xor1 fa_or0=u_csamul_rca32_fa4_30_or0
.subckt and_gate a=a[5] b=b[30] out=u_csamul_rca32_and5_30
.subckt fa a=u_csamul_rca32_and5_30 b=u_csamul_rca32_fa6_29_xor1 cin=u_csamul_rca32_fa5_29_or0 fa_xor1=u_csamul_rca32_fa5_30_xor1 fa_or0=u_csamul_rca32_fa5_30_or0
.subckt and_gate a=a[6] b=b[30] out=u_csamul_rca32_and6_30
.subckt fa a=u_csamul_rca32_and6_30 b=u_csamul_rca32_fa7_29_xor1 cin=u_csamul_rca32_fa6_29_or0 fa_xor1=u_csamul_rca32_fa6_30_xor1 fa_or0=u_csamul_rca32_fa6_30_or0
.subckt and_gate a=a[7] b=b[30] out=u_csamul_rca32_and7_30
.subckt fa a=u_csamul_rca32_and7_30 b=u_csamul_rca32_fa8_29_xor1 cin=u_csamul_rca32_fa7_29_or0 fa_xor1=u_csamul_rca32_fa7_30_xor1 fa_or0=u_csamul_rca32_fa7_30_or0
.subckt and_gate a=a[8] b=b[30] out=u_csamul_rca32_and8_30
.subckt fa a=u_csamul_rca32_and8_30 b=u_csamul_rca32_fa9_29_xor1 cin=u_csamul_rca32_fa8_29_or0 fa_xor1=u_csamul_rca32_fa8_30_xor1 fa_or0=u_csamul_rca32_fa8_30_or0
.subckt and_gate a=a[9] b=b[30] out=u_csamul_rca32_and9_30
.subckt fa a=u_csamul_rca32_and9_30 b=u_csamul_rca32_fa10_29_xor1 cin=u_csamul_rca32_fa9_29_or0 fa_xor1=u_csamul_rca32_fa9_30_xor1 fa_or0=u_csamul_rca32_fa9_30_or0
.subckt and_gate a=a[10] b=b[30] out=u_csamul_rca32_and10_30
.subckt fa a=u_csamul_rca32_and10_30 b=u_csamul_rca32_fa11_29_xor1 cin=u_csamul_rca32_fa10_29_or0 fa_xor1=u_csamul_rca32_fa10_30_xor1 fa_or0=u_csamul_rca32_fa10_30_or0
.subckt and_gate a=a[11] b=b[30] out=u_csamul_rca32_and11_30
.subckt fa a=u_csamul_rca32_and11_30 b=u_csamul_rca32_fa12_29_xor1 cin=u_csamul_rca32_fa11_29_or0 fa_xor1=u_csamul_rca32_fa11_30_xor1 fa_or0=u_csamul_rca32_fa11_30_or0
.subckt and_gate a=a[12] b=b[30] out=u_csamul_rca32_and12_30
.subckt fa a=u_csamul_rca32_and12_30 b=u_csamul_rca32_fa13_29_xor1 cin=u_csamul_rca32_fa12_29_or0 fa_xor1=u_csamul_rca32_fa12_30_xor1 fa_or0=u_csamul_rca32_fa12_30_or0
.subckt and_gate a=a[13] b=b[30] out=u_csamul_rca32_and13_30
.subckt fa a=u_csamul_rca32_and13_30 b=u_csamul_rca32_fa14_29_xor1 cin=u_csamul_rca32_fa13_29_or0 fa_xor1=u_csamul_rca32_fa13_30_xor1 fa_or0=u_csamul_rca32_fa13_30_or0
.subckt and_gate a=a[14] b=b[30] out=u_csamul_rca32_and14_30
.subckt fa a=u_csamul_rca32_and14_30 b=u_csamul_rca32_fa15_29_xor1 cin=u_csamul_rca32_fa14_29_or0 fa_xor1=u_csamul_rca32_fa14_30_xor1 fa_or0=u_csamul_rca32_fa14_30_or0
.subckt and_gate a=a[15] b=b[30] out=u_csamul_rca32_and15_30
.subckt fa a=u_csamul_rca32_and15_30 b=u_csamul_rca32_fa16_29_xor1 cin=u_csamul_rca32_fa15_29_or0 fa_xor1=u_csamul_rca32_fa15_30_xor1 fa_or0=u_csamul_rca32_fa15_30_or0
.subckt and_gate a=a[16] b=b[30] out=u_csamul_rca32_and16_30
.subckt fa a=u_csamul_rca32_and16_30 b=u_csamul_rca32_fa17_29_xor1 cin=u_csamul_rca32_fa16_29_or0 fa_xor1=u_csamul_rca32_fa16_30_xor1 fa_or0=u_csamul_rca32_fa16_30_or0
.subckt and_gate a=a[17] b=b[30] out=u_csamul_rca32_and17_30
.subckt fa a=u_csamul_rca32_and17_30 b=u_csamul_rca32_fa18_29_xor1 cin=u_csamul_rca32_fa17_29_or0 fa_xor1=u_csamul_rca32_fa17_30_xor1 fa_or0=u_csamul_rca32_fa17_30_or0
.subckt and_gate a=a[18] b=b[30] out=u_csamul_rca32_and18_30
.subckt fa a=u_csamul_rca32_and18_30 b=u_csamul_rca32_fa19_29_xor1 cin=u_csamul_rca32_fa18_29_or0 fa_xor1=u_csamul_rca32_fa18_30_xor1 fa_or0=u_csamul_rca32_fa18_30_or0
.subckt and_gate a=a[19] b=b[30] out=u_csamul_rca32_and19_30
.subckt fa a=u_csamul_rca32_and19_30 b=u_csamul_rca32_fa20_29_xor1 cin=u_csamul_rca32_fa19_29_or0 fa_xor1=u_csamul_rca32_fa19_30_xor1 fa_or0=u_csamul_rca32_fa19_30_or0
.subckt and_gate a=a[20] b=b[30] out=u_csamul_rca32_and20_30
.subckt fa a=u_csamul_rca32_and20_30 b=u_csamul_rca32_fa21_29_xor1 cin=u_csamul_rca32_fa20_29_or0 fa_xor1=u_csamul_rca32_fa20_30_xor1 fa_or0=u_csamul_rca32_fa20_30_or0
.subckt and_gate a=a[21] b=b[30] out=u_csamul_rca32_and21_30
.subckt fa a=u_csamul_rca32_and21_30 b=u_csamul_rca32_fa22_29_xor1 cin=u_csamul_rca32_fa21_29_or0 fa_xor1=u_csamul_rca32_fa21_30_xor1 fa_or0=u_csamul_rca32_fa21_30_or0
.subckt and_gate a=a[22] b=b[30] out=u_csamul_rca32_and22_30
.subckt fa a=u_csamul_rca32_and22_30 b=u_csamul_rca32_fa23_29_xor1 cin=u_csamul_rca32_fa22_29_or0 fa_xor1=u_csamul_rca32_fa22_30_xor1 fa_or0=u_csamul_rca32_fa22_30_or0
.subckt and_gate a=a[23] b=b[30] out=u_csamul_rca32_and23_30
.subckt fa a=u_csamul_rca32_and23_30 b=u_csamul_rca32_fa24_29_xor1 cin=u_csamul_rca32_fa23_29_or0 fa_xor1=u_csamul_rca32_fa23_30_xor1 fa_or0=u_csamul_rca32_fa23_30_or0
.subckt and_gate a=a[24] b=b[30] out=u_csamul_rca32_and24_30
.subckt fa a=u_csamul_rca32_and24_30 b=u_csamul_rca32_fa25_29_xor1 cin=u_csamul_rca32_fa24_29_or0 fa_xor1=u_csamul_rca32_fa24_30_xor1 fa_or0=u_csamul_rca32_fa24_30_or0
.subckt and_gate a=a[25] b=b[30] out=u_csamul_rca32_and25_30
.subckt fa a=u_csamul_rca32_and25_30 b=u_csamul_rca32_fa26_29_xor1 cin=u_csamul_rca32_fa25_29_or0 fa_xor1=u_csamul_rca32_fa25_30_xor1 fa_or0=u_csamul_rca32_fa25_30_or0
.subckt and_gate a=a[26] b=b[30] out=u_csamul_rca32_and26_30
.subckt fa a=u_csamul_rca32_and26_30 b=u_csamul_rca32_fa27_29_xor1 cin=u_csamul_rca32_fa26_29_or0 fa_xor1=u_csamul_rca32_fa26_30_xor1 fa_or0=u_csamul_rca32_fa26_30_or0
.subckt and_gate a=a[27] b=b[30] out=u_csamul_rca32_and27_30
.subckt fa a=u_csamul_rca32_and27_30 b=u_csamul_rca32_fa28_29_xor1 cin=u_csamul_rca32_fa27_29_or0 fa_xor1=u_csamul_rca32_fa27_30_xor1 fa_or0=u_csamul_rca32_fa27_30_or0
.subckt and_gate a=a[28] b=b[30] out=u_csamul_rca32_and28_30
.subckt fa a=u_csamul_rca32_and28_30 b=u_csamul_rca32_fa29_29_xor1 cin=u_csamul_rca32_fa28_29_or0 fa_xor1=u_csamul_rca32_fa28_30_xor1 fa_or0=u_csamul_rca32_fa28_30_or0
.subckt and_gate a=a[29] b=b[30] out=u_csamul_rca32_and29_30
.subckt fa a=u_csamul_rca32_and29_30 b=u_csamul_rca32_fa30_29_xor1 cin=u_csamul_rca32_fa29_29_or0 fa_xor1=u_csamul_rca32_fa29_30_xor1 fa_or0=u_csamul_rca32_fa29_30_or0
.subckt and_gate a=a[30] b=b[30] out=u_csamul_rca32_and30_30
.subckt fa a=u_csamul_rca32_and30_30 b=u_csamul_rca32_and31_29 cin=u_csamul_rca32_fa30_29_or0 fa_xor1=u_csamul_rca32_fa30_30_xor1 fa_or0=u_csamul_rca32_fa30_30_or0
.subckt and_gate a=a[31] b=b[30] out=u_csamul_rca32_and31_30
.subckt and_gate a=a[0] b=b[31] out=u_csamul_rca32_and0_31
.subckt fa a=u_csamul_rca32_and0_31 b=u_csamul_rca32_fa1_30_xor1 cin=u_csamul_rca32_fa0_30_or0 fa_xor1=u_csamul_rca32_fa0_31_xor1 fa_or0=u_csamul_rca32_fa0_31_or0
.subckt and_gate a=a[1] b=b[31] out=u_csamul_rca32_and1_31
.subckt fa a=u_csamul_rca32_and1_31 b=u_csamul_rca32_fa2_30_xor1 cin=u_csamul_rca32_fa1_30_or0 fa_xor1=u_csamul_rca32_fa1_31_xor1 fa_or0=u_csamul_rca32_fa1_31_or0
.subckt and_gate a=a[2] b=b[31] out=u_csamul_rca32_and2_31
.subckt fa a=u_csamul_rca32_and2_31 b=u_csamul_rca32_fa3_30_xor1 cin=u_csamul_rca32_fa2_30_or0 fa_xor1=u_csamul_rca32_fa2_31_xor1 fa_or0=u_csamul_rca32_fa2_31_or0
.subckt and_gate a=a[3] b=b[31] out=u_csamul_rca32_and3_31
.subckt fa a=u_csamul_rca32_and3_31 b=u_csamul_rca32_fa4_30_xor1 cin=u_csamul_rca32_fa3_30_or0 fa_xor1=u_csamul_rca32_fa3_31_xor1 fa_or0=u_csamul_rca32_fa3_31_or0
.subckt and_gate a=a[4] b=b[31] out=u_csamul_rca32_and4_31
.subckt fa a=u_csamul_rca32_and4_31 b=u_csamul_rca32_fa5_30_xor1 cin=u_csamul_rca32_fa4_30_or0 fa_xor1=u_csamul_rca32_fa4_31_xor1 fa_or0=u_csamul_rca32_fa4_31_or0
.subckt and_gate a=a[5] b=b[31] out=u_csamul_rca32_and5_31
.subckt fa a=u_csamul_rca32_and5_31 b=u_csamul_rca32_fa6_30_xor1 cin=u_csamul_rca32_fa5_30_or0 fa_xor1=u_csamul_rca32_fa5_31_xor1 fa_or0=u_csamul_rca32_fa5_31_or0
.subckt and_gate a=a[6] b=b[31] out=u_csamul_rca32_and6_31
.subckt fa a=u_csamul_rca32_and6_31 b=u_csamul_rca32_fa7_30_xor1 cin=u_csamul_rca32_fa6_30_or0 fa_xor1=u_csamul_rca32_fa6_31_xor1 fa_or0=u_csamul_rca32_fa6_31_or0
.subckt and_gate a=a[7] b=b[31] out=u_csamul_rca32_and7_31
.subckt fa a=u_csamul_rca32_and7_31 b=u_csamul_rca32_fa8_30_xor1 cin=u_csamul_rca32_fa7_30_or0 fa_xor1=u_csamul_rca32_fa7_31_xor1 fa_or0=u_csamul_rca32_fa7_31_or0
.subckt and_gate a=a[8] b=b[31] out=u_csamul_rca32_and8_31
.subckt fa a=u_csamul_rca32_and8_31 b=u_csamul_rca32_fa9_30_xor1 cin=u_csamul_rca32_fa8_30_or0 fa_xor1=u_csamul_rca32_fa8_31_xor1 fa_or0=u_csamul_rca32_fa8_31_or0
.subckt and_gate a=a[9] b=b[31] out=u_csamul_rca32_and9_31
.subckt fa a=u_csamul_rca32_and9_31 b=u_csamul_rca32_fa10_30_xor1 cin=u_csamul_rca32_fa9_30_or0 fa_xor1=u_csamul_rca32_fa9_31_xor1 fa_or0=u_csamul_rca32_fa9_31_or0
.subckt and_gate a=a[10] b=b[31] out=u_csamul_rca32_and10_31
.subckt fa a=u_csamul_rca32_and10_31 b=u_csamul_rca32_fa11_30_xor1 cin=u_csamul_rca32_fa10_30_or0 fa_xor1=u_csamul_rca32_fa10_31_xor1 fa_or0=u_csamul_rca32_fa10_31_or0
.subckt and_gate a=a[11] b=b[31] out=u_csamul_rca32_and11_31
.subckt fa a=u_csamul_rca32_and11_31 b=u_csamul_rca32_fa12_30_xor1 cin=u_csamul_rca32_fa11_30_or0 fa_xor1=u_csamul_rca32_fa11_31_xor1 fa_or0=u_csamul_rca32_fa11_31_or0
.subckt and_gate a=a[12] b=b[31] out=u_csamul_rca32_and12_31
.subckt fa a=u_csamul_rca32_and12_31 b=u_csamul_rca32_fa13_30_xor1 cin=u_csamul_rca32_fa12_30_or0 fa_xor1=u_csamul_rca32_fa12_31_xor1 fa_or0=u_csamul_rca32_fa12_31_or0
.subckt and_gate a=a[13] b=b[31] out=u_csamul_rca32_and13_31
.subckt fa a=u_csamul_rca32_and13_31 b=u_csamul_rca32_fa14_30_xor1 cin=u_csamul_rca32_fa13_30_or0 fa_xor1=u_csamul_rca32_fa13_31_xor1 fa_or0=u_csamul_rca32_fa13_31_or0
.subckt and_gate a=a[14] b=b[31] out=u_csamul_rca32_and14_31
.subckt fa a=u_csamul_rca32_and14_31 b=u_csamul_rca32_fa15_30_xor1 cin=u_csamul_rca32_fa14_30_or0 fa_xor1=u_csamul_rca32_fa14_31_xor1 fa_or0=u_csamul_rca32_fa14_31_or0
.subckt and_gate a=a[15] b=b[31] out=u_csamul_rca32_and15_31
.subckt fa a=u_csamul_rca32_and15_31 b=u_csamul_rca32_fa16_30_xor1 cin=u_csamul_rca32_fa15_30_or0 fa_xor1=u_csamul_rca32_fa15_31_xor1 fa_or0=u_csamul_rca32_fa15_31_or0
.subckt and_gate a=a[16] b=b[31] out=u_csamul_rca32_and16_31
.subckt fa a=u_csamul_rca32_and16_31 b=u_csamul_rca32_fa17_30_xor1 cin=u_csamul_rca32_fa16_30_or0 fa_xor1=u_csamul_rca32_fa16_31_xor1 fa_or0=u_csamul_rca32_fa16_31_or0
.subckt and_gate a=a[17] b=b[31] out=u_csamul_rca32_and17_31
.subckt fa a=u_csamul_rca32_and17_31 b=u_csamul_rca32_fa18_30_xor1 cin=u_csamul_rca32_fa17_30_or0 fa_xor1=u_csamul_rca32_fa17_31_xor1 fa_or0=u_csamul_rca32_fa17_31_or0
.subckt and_gate a=a[18] b=b[31] out=u_csamul_rca32_and18_31
.subckt fa a=u_csamul_rca32_and18_31 b=u_csamul_rca32_fa19_30_xor1 cin=u_csamul_rca32_fa18_30_or0 fa_xor1=u_csamul_rca32_fa18_31_xor1 fa_or0=u_csamul_rca32_fa18_31_or0
.subckt and_gate a=a[19] b=b[31] out=u_csamul_rca32_and19_31
.subckt fa a=u_csamul_rca32_and19_31 b=u_csamul_rca32_fa20_30_xor1 cin=u_csamul_rca32_fa19_30_or0 fa_xor1=u_csamul_rca32_fa19_31_xor1 fa_or0=u_csamul_rca32_fa19_31_or0
.subckt and_gate a=a[20] b=b[31] out=u_csamul_rca32_and20_31
.subckt fa a=u_csamul_rca32_and20_31 b=u_csamul_rca32_fa21_30_xor1 cin=u_csamul_rca32_fa20_30_or0 fa_xor1=u_csamul_rca32_fa20_31_xor1 fa_or0=u_csamul_rca32_fa20_31_or0
.subckt and_gate a=a[21] b=b[31] out=u_csamul_rca32_and21_31
.subckt fa a=u_csamul_rca32_and21_31 b=u_csamul_rca32_fa22_30_xor1 cin=u_csamul_rca32_fa21_30_or0 fa_xor1=u_csamul_rca32_fa21_31_xor1 fa_or0=u_csamul_rca32_fa21_31_or0
.subckt and_gate a=a[22] b=b[31] out=u_csamul_rca32_and22_31
.subckt fa a=u_csamul_rca32_and22_31 b=u_csamul_rca32_fa23_30_xor1 cin=u_csamul_rca32_fa22_30_or0 fa_xor1=u_csamul_rca32_fa22_31_xor1 fa_or0=u_csamul_rca32_fa22_31_or0
.subckt and_gate a=a[23] b=b[31] out=u_csamul_rca32_and23_31
.subckt fa a=u_csamul_rca32_and23_31 b=u_csamul_rca32_fa24_30_xor1 cin=u_csamul_rca32_fa23_30_or0 fa_xor1=u_csamul_rca32_fa23_31_xor1 fa_or0=u_csamul_rca32_fa23_31_or0
.subckt and_gate a=a[24] b=b[31] out=u_csamul_rca32_and24_31
.subckt fa a=u_csamul_rca32_and24_31 b=u_csamul_rca32_fa25_30_xor1 cin=u_csamul_rca32_fa24_30_or0 fa_xor1=u_csamul_rca32_fa24_31_xor1 fa_or0=u_csamul_rca32_fa24_31_or0
.subckt and_gate a=a[25] b=b[31] out=u_csamul_rca32_and25_31
.subckt fa a=u_csamul_rca32_and25_31 b=u_csamul_rca32_fa26_30_xor1 cin=u_csamul_rca32_fa25_30_or0 fa_xor1=u_csamul_rca32_fa25_31_xor1 fa_or0=u_csamul_rca32_fa25_31_or0
.subckt and_gate a=a[26] b=b[31] out=u_csamul_rca32_and26_31
.subckt fa a=u_csamul_rca32_and26_31 b=u_csamul_rca32_fa27_30_xor1 cin=u_csamul_rca32_fa26_30_or0 fa_xor1=u_csamul_rca32_fa26_31_xor1 fa_or0=u_csamul_rca32_fa26_31_or0
.subckt and_gate a=a[27] b=b[31] out=u_csamul_rca32_and27_31
.subckt fa a=u_csamul_rca32_and27_31 b=u_csamul_rca32_fa28_30_xor1 cin=u_csamul_rca32_fa27_30_or0 fa_xor1=u_csamul_rca32_fa27_31_xor1 fa_or0=u_csamul_rca32_fa27_31_or0
.subckt and_gate a=a[28] b=b[31] out=u_csamul_rca32_and28_31
.subckt fa a=u_csamul_rca32_and28_31 b=u_csamul_rca32_fa29_30_xor1 cin=u_csamul_rca32_fa28_30_or0 fa_xor1=u_csamul_rca32_fa28_31_xor1 fa_or0=u_csamul_rca32_fa28_31_or0
.subckt and_gate a=a[29] b=b[31] out=u_csamul_rca32_and29_31
.subckt fa a=u_csamul_rca32_and29_31 b=u_csamul_rca32_fa30_30_xor1 cin=u_csamul_rca32_fa29_30_or0 fa_xor1=u_csamul_rca32_fa29_31_xor1 fa_or0=u_csamul_rca32_fa29_31_or0
.subckt and_gate a=a[30] b=b[31] out=u_csamul_rca32_and30_31
.subckt fa a=u_csamul_rca32_and30_31 b=u_csamul_rca32_and31_30 cin=u_csamul_rca32_fa30_30_or0 fa_xor1=u_csamul_rca32_fa30_31_xor1 fa_or0=u_csamul_rca32_fa30_31_or0
.subckt and_gate a=a[31] b=b[31] out=u_csamul_rca32_and31_31
.names u_csamul_rca32_fa1_31_xor1 u_csamul_rca32_u_rca32_a[0]
1 1
.names u_csamul_rca32_fa2_31_xor1 u_csamul_rca32_u_rca32_a[1]
1 1
.names u_csamul_rca32_fa3_31_xor1 u_csamul_rca32_u_rca32_a[2]
1 1
.names u_csamul_rca32_fa4_31_xor1 u_csamul_rca32_u_rca32_a[3]
1 1
.names u_csamul_rca32_fa5_31_xor1 u_csamul_rca32_u_rca32_a[4]
1 1
.names u_csamul_rca32_fa6_31_xor1 u_csamul_rca32_u_rca32_a[5]
1 1
.names u_csamul_rca32_fa7_31_xor1 u_csamul_rca32_u_rca32_a[6]
1 1
.names u_csamul_rca32_fa8_31_xor1 u_csamul_rca32_u_rca32_a[7]
1 1
.names u_csamul_rca32_fa9_31_xor1 u_csamul_rca32_u_rca32_a[8]
1 1
.names u_csamul_rca32_fa10_31_xor1 u_csamul_rca32_u_rca32_a[9]
1 1
.names u_csamul_rca32_fa11_31_xor1 u_csamul_rca32_u_rca32_a[10]
1 1
.names u_csamul_rca32_fa12_31_xor1 u_csamul_rca32_u_rca32_a[11]
1 1
.names u_csamul_rca32_fa13_31_xor1 u_csamul_rca32_u_rca32_a[12]
1 1
.names u_csamul_rca32_fa14_31_xor1 u_csamul_rca32_u_rca32_a[13]
1 1
.names u_csamul_rca32_fa15_31_xor1 u_csamul_rca32_u_rca32_a[14]
1 1
.names u_csamul_rca32_fa16_31_xor1 u_csamul_rca32_u_rca32_a[15]
1 1
.names u_csamul_rca32_fa17_31_xor1 u_csamul_rca32_u_rca32_a[16]
1 1
.names u_csamul_rca32_fa18_31_xor1 u_csamul_rca32_u_rca32_a[17]
1 1
.names u_csamul_rca32_fa19_31_xor1 u_csamul_rca32_u_rca32_a[18]
1 1
.names u_csamul_rca32_fa20_31_xor1 u_csamul_rca32_u_rca32_a[19]
1 1
.names u_csamul_rca32_fa21_31_xor1 u_csamul_rca32_u_rca32_a[20]
1 1
.names u_csamul_rca32_fa22_31_xor1 u_csamul_rca32_u_rca32_a[21]
1 1
.names u_csamul_rca32_fa23_31_xor1 u_csamul_rca32_u_rca32_a[22]
1 1
.names u_csamul_rca32_fa24_31_xor1 u_csamul_rca32_u_rca32_a[23]
1 1
.names u_csamul_rca32_fa25_31_xor1 u_csamul_rca32_u_rca32_a[24]
1 1
.names u_csamul_rca32_fa26_31_xor1 u_csamul_rca32_u_rca32_a[25]
1 1
.names u_csamul_rca32_fa27_31_xor1 u_csamul_rca32_u_rca32_a[26]
1 1
.names u_csamul_rca32_fa28_31_xor1 u_csamul_rca32_u_rca32_a[27]
1 1
.names u_csamul_rca32_fa29_31_xor1 u_csamul_rca32_u_rca32_a[28]
1 1
.names u_csamul_rca32_fa30_31_xor1 u_csamul_rca32_u_rca32_a[29]
1 1
.names u_csamul_rca32_and31_31 u_csamul_rca32_u_rca32_a[30]
1 1
.names gnd u_csamul_rca32_u_rca32_a[31]
1 1
.names u_csamul_rca32_fa0_31_or0 u_csamul_rca32_u_rca32_b[0]
1 1
.names u_csamul_rca32_fa1_31_or0 u_csamul_rca32_u_rca32_b[1]
1 1
.names u_csamul_rca32_fa2_31_or0 u_csamul_rca32_u_rca32_b[2]
1 1
.names u_csamul_rca32_fa3_31_or0 u_csamul_rca32_u_rca32_b[3]
1 1
.names u_csamul_rca32_fa4_31_or0 u_csamul_rca32_u_rca32_b[4]
1 1
.names u_csamul_rca32_fa5_31_or0 u_csamul_rca32_u_rca32_b[5]
1 1
.names u_csamul_rca32_fa6_31_or0 u_csamul_rca32_u_rca32_b[6]
1 1
.names u_csamul_rca32_fa7_31_or0 u_csamul_rca32_u_rca32_b[7]
1 1
.names u_csamul_rca32_fa8_31_or0 u_csamul_rca32_u_rca32_b[8]
1 1
.names u_csamul_rca32_fa9_31_or0 u_csamul_rca32_u_rca32_b[9]
1 1
.names u_csamul_rca32_fa10_31_or0 u_csamul_rca32_u_rca32_b[10]
1 1
.names u_csamul_rca32_fa11_31_or0 u_csamul_rca32_u_rca32_b[11]
1 1
.names u_csamul_rca32_fa12_31_or0 u_csamul_rca32_u_rca32_b[12]
1 1
.names u_csamul_rca32_fa13_31_or0 u_csamul_rca32_u_rca32_b[13]
1 1
.names u_csamul_rca32_fa14_31_or0 u_csamul_rca32_u_rca32_b[14]
1 1
.names u_csamul_rca32_fa15_31_or0 u_csamul_rca32_u_rca32_b[15]
1 1
.names u_csamul_rca32_fa16_31_or0 u_csamul_rca32_u_rca32_b[16]
1 1
.names u_csamul_rca32_fa17_31_or0 u_csamul_rca32_u_rca32_b[17]
1 1
.names u_csamul_rca32_fa18_31_or0 u_csamul_rca32_u_rca32_b[18]
1 1
.names u_csamul_rca32_fa19_31_or0 u_csamul_rca32_u_rca32_b[19]
1 1
.names u_csamul_rca32_fa20_31_or0 u_csamul_rca32_u_rca32_b[20]
1 1
.names u_csamul_rca32_fa21_31_or0 u_csamul_rca32_u_rca32_b[21]
1 1
.names u_csamul_rca32_fa22_31_or0 u_csamul_rca32_u_rca32_b[22]
1 1
.names u_csamul_rca32_fa23_31_or0 u_csamul_rca32_u_rca32_b[23]
1 1
.names u_csamul_rca32_fa24_31_or0 u_csamul_rca32_u_rca32_b[24]
1 1
.names u_csamul_rca32_fa25_31_or0 u_csamul_rca32_u_rca32_b[25]
1 1
.names u_csamul_rca32_fa26_31_or0 u_csamul_rca32_u_rca32_b[26]
1 1
.names u_csamul_rca32_fa27_31_or0 u_csamul_rca32_u_rca32_b[27]
1 1
.names u_csamul_rca32_fa28_31_or0 u_csamul_rca32_u_rca32_b[28]
1 1
.names u_csamul_rca32_fa29_31_or0 u_csamul_rca32_u_rca32_b[29]
1 1
.names u_csamul_rca32_fa30_31_or0 u_csamul_rca32_u_rca32_b[30]
1 1
.names gnd u_csamul_rca32_u_rca32_b[31]
1 1
.subckt u_rca32 a[0]=u_csamul_rca32_u_rca32_a[0] a[1]=u_csamul_rca32_u_rca32_a[1] a[2]=u_csamul_rca32_u_rca32_a[2] a[3]=u_csamul_rca32_u_rca32_a[3] a[4]=u_csamul_rca32_u_rca32_a[4] a[5]=u_csamul_rca32_u_rca32_a[5] a[6]=u_csamul_rca32_u_rca32_a[6] a[7]=u_csamul_rca32_u_rca32_a[7] a[8]=u_csamul_rca32_u_rca32_a[8] a[9]=u_csamul_rca32_u_rca32_a[9] a[10]=u_csamul_rca32_u_rca32_a[10] a[11]=u_csamul_rca32_u_rca32_a[11] a[12]=u_csamul_rca32_u_rca32_a[12] a[13]=u_csamul_rca32_u_rca32_a[13] a[14]=u_csamul_rca32_u_rca32_a[14] a[15]=u_csamul_rca32_u_rca32_a[15] a[16]=u_csamul_rca32_u_rca32_a[16] a[17]=u_csamul_rca32_u_rca32_a[17] a[18]=u_csamul_rca32_u_rca32_a[18] a[19]=u_csamul_rca32_u_rca32_a[19] a[20]=u_csamul_rca32_u_rca32_a[20] a[21]=u_csamul_rca32_u_rca32_a[21] a[22]=u_csamul_rca32_u_rca32_a[22] a[23]=u_csamul_rca32_u_rca32_a[23] a[24]=u_csamul_rca32_u_rca32_a[24] a[25]=u_csamul_rca32_u_rca32_a[25] a[26]=u_csamul_rca32_u_rca32_a[26] a[27]=u_csamul_rca32_u_rca32_a[27] a[28]=u_csamul_rca32_u_rca32_a[28] a[29]=u_csamul_rca32_u_rca32_a[29] a[30]=u_csamul_rca32_u_rca32_a[30] a[31]=u_csamul_rca32_u_rca32_a[31] b[0]=u_csamul_rca32_u_rca32_b[0] b[1]=u_csamul_rca32_u_rca32_b[1] b[2]=u_csamul_rca32_u_rca32_b[2] b[3]=u_csamul_rca32_u_rca32_b[3] b[4]=u_csamul_rca32_u_rca32_b[4] b[5]=u_csamul_rca32_u_rca32_b[5] b[6]=u_csamul_rca32_u_rca32_b[6] b[7]=u_csamul_rca32_u_rca32_b[7] b[8]=u_csamul_rca32_u_rca32_b[8] b[9]=u_csamul_rca32_u_rca32_b[9] b[10]=u_csamul_rca32_u_rca32_b[10] b[11]=u_csamul_rca32_u_rca32_b[11] b[12]=u_csamul_rca32_u_rca32_b[12] b[13]=u_csamul_rca32_u_rca32_b[13] b[14]=u_csamul_rca32_u_rca32_b[14] b[15]=u_csamul_rca32_u_rca32_b[15] b[16]=u_csamul_rca32_u_rca32_b[16] b[17]=u_csamul_rca32_u_rca32_b[17] b[18]=u_csamul_rca32_u_rca32_b[18] b[19]=u_csamul_rca32_u_rca32_b[19] b[20]=u_csamul_rca32_u_rca32_b[20] b[21]=u_csamul_rca32_u_rca32_b[21] b[22]=u_csamul_rca32_u_rca32_b[22] b[23]=u_csamul_rca32_u_rca32_b[23] b[24]=u_csamul_rca32_u_rca32_b[24] b[25]=u_csamul_rca32_u_rca32_b[25] b[26]=u_csamul_rca32_u_rca32_b[26] b[27]=u_csamul_rca32_u_rca32_b[27] b[28]=u_csamul_rca32_u_rca32_b[28] b[29]=u_csamul_rca32_u_rca32_b[29] b[30]=u_csamul_rca32_u_rca32_b[30] b[31]=u_csamul_rca32_u_rca32_b[31] u_rca32_out[0]=u_csamul_rca32_u_rca32_ha_xor0 u_rca32_out[1]=u_csamul_rca32_u_rca32_fa1_xor1 u_rca32_out[2]=u_csamul_rca32_u_rca32_fa2_xor1 u_rca32_out[3]=u_csamul_rca32_u_rca32_fa3_xor1 u_rca32_out[4]=u_csamul_rca32_u_rca32_fa4_xor1 u_rca32_out[5]=u_csamul_rca32_u_rca32_fa5_xor1 u_rca32_out[6]=u_csamul_rca32_u_rca32_fa6_xor1 u_rca32_out[7]=u_csamul_rca32_u_rca32_fa7_xor1 u_rca32_out[8]=u_csamul_rca32_u_rca32_fa8_xor1 u_rca32_out[9]=u_csamul_rca32_u_rca32_fa9_xor1 u_rca32_out[10]=u_csamul_rca32_u_rca32_fa10_xor1 u_rca32_out[11]=u_csamul_rca32_u_rca32_fa11_xor1 u_rca32_out[12]=u_csamul_rca32_u_rca32_fa12_xor1 u_rca32_out[13]=u_csamul_rca32_u_rca32_fa13_xor1 u_rca32_out[14]=u_csamul_rca32_u_rca32_fa14_xor1 u_rca32_out[15]=u_csamul_rca32_u_rca32_fa15_xor1 u_rca32_out[16]=u_csamul_rca32_u_rca32_fa16_xor1 u_rca32_out[17]=u_csamul_rca32_u_rca32_fa17_xor1 u_rca32_out[18]=u_csamul_rca32_u_rca32_fa18_xor1 u_rca32_out[19]=u_csamul_rca32_u_rca32_fa19_xor1 u_rca32_out[20]=u_csamul_rca32_u_rca32_fa20_xor1 u_rca32_out[21]=u_csamul_rca32_u_rca32_fa21_xor1 u_rca32_out[22]=u_csamul_rca32_u_rca32_fa22_xor1 u_rca32_out[23]=u_csamul_rca32_u_rca32_fa23_xor1 u_rca32_out[24]=u_csamul_rca32_u_rca32_fa24_xor1 u_rca32_out[25]=u_csamul_rca32_u_rca32_fa25_xor1 u_rca32_out[26]=u_csamul_rca32_u_rca32_fa26_xor1 u_rca32_out[27]=u_csamul_rca32_u_rca32_fa27_xor1 u_rca32_out[28]=u_csamul_rca32_u_rca32_fa28_xor1 u_rca32_out[29]=u_csamul_rca32_u_rca32_fa29_xor1 u_rca32_out[30]=u_csamul_rca32_u_rca32_fa30_xor1 u_rca32_out[31]=u_csamul_rca32_u_rca32_fa30_or0 u_rca32_out[32]=constant_value_0
.names u_csamul_rca32_and0_0 u_csamul_rca32_out[0]
1 1
.names u_csamul_rca32_ha0_1_xor0 u_csamul_rca32_out[1]
1 1
.names u_csamul_rca32_fa0_2_xor1 u_csamul_rca32_out[2]
1 1
.names u_csamul_rca32_fa0_3_xor1 u_csamul_rca32_out[3]
1 1
.names u_csamul_rca32_fa0_4_xor1 u_csamul_rca32_out[4]
1 1
.names u_csamul_rca32_fa0_5_xor1 u_csamul_rca32_out[5]
1 1
.names u_csamul_rca32_fa0_6_xor1 u_csamul_rca32_out[6]
1 1
.names u_csamul_rca32_fa0_7_xor1 u_csamul_rca32_out[7]
1 1
.names u_csamul_rca32_fa0_8_xor1 u_csamul_rca32_out[8]
1 1
.names u_csamul_rca32_fa0_9_xor1 u_csamul_rca32_out[9]
1 1
.names u_csamul_rca32_fa0_10_xor1 u_csamul_rca32_out[10]
1 1
.names u_csamul_rca32_fa0_11_xor1 u_csamul_rca32_out[11]
1 1
.names u_csamul_rca32_fa0_12_xor1 u_csamul_rca32_out[12]
1 1
.names u_csamul_rca32_fa0_13_xor1 u_csamul_rca32_out[13]
1 1
.names u_csamul_rca32_fa0_14_xor1 u_csamul_rca32_out[14]
1 1
.names u_csamul_rca32_fa0_15_xor1 u_csamul_rca32_out[15]
1 1
.names u_csamul_rca32_fa0_16_xor1 u_csamul_rca32_out[16]
1 1
.names u_csamul_rca32_fa0_17_xor1 u_csamul_rca32_out[17]
1 1
.names u_csamul_rca32_fa0_18_xor1 u_csamul_rca32_out[18]
1 1
.names u_csamul_rca32_fa0_19_xor1 u_csamul_rca32_out[19]
1 1
.names u_csamul_rca32_fa0_20_xor1 u_csamul_rca32_out[20]
1 1
.names u_csamul_rca32_fa0_21_xor1 u_csamul_rca32_out[21]
1 1
.names u_csamul_rca32_fa0_22_xor1 u_csamul_rca32_out[22]
1 1
.names u_csamul_rca32_fa0_23_xor1 u_csamul_rca32_out[23]
1 1
.names u_csamul_rca32_fa0_24_xor1 u_csamul_rca32_out[24]
1 1
.names u_csamul_rca32_fa0_25_xor1 u_csamul_rca32_out[25]
1 1
.names u_csamul_rca32_fa0_26_xor1 u_csamul_rca32_out[26]
1 1
.names u_csamul_rca32_fa0_27_xor1 u_csamul_rca32_out[27]
1 1
.names u_csamul_rca32_fa0_28_xor1 u_csamul_rca32_out[28]
1 1
.names u_csamul_rca32_fa0_29_xor1 u_csamul_rca32_out[29]
1 1
.names u_csamul_rca32_fa0_30_xor1 u_csamul_rca32_out[30]
1 1
.names u_csamul_rca32_fa0_31_xor1 u_csamul_rca32_out[31]
1 1
.names u_csamul_rca32_u_rca32_ha_xor0 u_csamul_rca32_out[32]
1 1
.names u_csamul_rca32_u_rca32_fa1_xor1 u_csamul_rca32_out[33]
1 1
.names u_csamul_rca32_u_rca32_fa2_xor1 u_csamul_rca32_out[34]
1 1
.names u_csamul_rca32_u_rca32_fa3_xor1 u_csamul_rca32_out[35]
1 1
.names u_csamul_rca32_u_rca32_fa4_xor1 u_csamul_rca32_out[36]
1 1
.names u_csamul_rca32_u_rca32_fa5_xor1 u_csamul_rca32_out[37]
1 1
.names u_csamul_rca32_u_rca32_fa6_xor1 u_csamul_rca32_out[38]
1 1
.names u_csamul_rca32_u_rca32_fa7_xor1 u_csamul_rca32_out[39]
1 1
.names u_csamul_rca32_u_rca32_fa8_xor1 u_csamul_rca32_out[40]
1 1
.names u_csamul_rca32_u_rca32_fa9_xor1 u_csamul_rca32_out[41]
1 1
.names u_csamul_rca32_u_rca32_fa10_xor1 u_csamul_rca32_out[42]
1 1
.names u_csamul_rca32_u_rca32_fa11_xor1 u_csamul_rca32_out[43]
1 1
.names u_csamul_rca32_u_rca32_fa12_xor1 u_csamul_rca32_out[44]
1 1
.names u_csamul_rca32_u_rca32_fa13_xor1 u_csamul_rca32_out[45]
1 1
.names u_csamul_rca32_u_rca32_fa14_xor1 u_csamul_rca32_out[46]
1 1
.names u_csamul_rca32_u_rca32_fa15_xor1 u_csamul_rca32_out[47]
1 1
.names u_csamul_rca32_u_rca32_fa16_xor1 u_csamul_rca32_out[48]
1 1
.names u_csamul_rca32_u_rca32_fa17_xor1 u_csamul_rca32_out[49]
1 1
.names u_csamul_rca32_u_rca32_fa18_xor1 u_csamul_rca32_out[50]
1 1
.names u_csamul_rca32_u_rca32_fa19_xor1 u_csamul_rca32_out[51]
1 1
.names u_csamul_rca32_u_rca32_fa20_xor1 u_csamul_rca32_out[52]
1 1
.names u_csamul_rca32_u_rca32_fa21_xor1 u_csamul_rca32_out[53]
1 1
.names u_csamul_rca32_u_rca32_fa22_xor1 u_csamul_rca32_out[54]
1 1
.names u_csamul_rca32_u_rca32_fa23_xor1 u_csamul_rca32_out[55]
1 1
.names u_csamul_rca32_u_rca32_fa24_xor1 u_csamul_rca32_out[56]
1 1
.names u_csamul_rca32_u_rca32_fa25_xor1 u_csamul_rca32_out[57]
1 1
.names u_csamul_rca32_u_rca32_fa26_xor1 u_csamul_rca32_out[58]
1 1
.names u_csamul_rca32_u_rca32_fa27_xor1 u_csamul_rca32_out[59]
1 1
.names u_csamul_rca32_u_rca32_fa28_xor1 u_csamul_rca32_out[60]
1 1
.names u_csamul_rca32_u_rca32_fa29_xor1 u_csamul_rca32_out[61]
1 1
.names u_csamul_rca32_u_rca32_fa30_xor1 u_csamul_rca32_out[62]
1 1
.names u_csamul_rca32_u_rca32_fa30_or0 u_csamul_rca32_out[63]
1 1
.end
.model u_rca32
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] a[31] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31]
.outputs u_rca32_out[0] u_rca32_out[1] u_rca32_out[2] u_rca32_out[3] u_rca32_out[4] u_rca32_out[5] u_rca32_out[6] u_rca32_out[7] u_rca32_out[8] u_rca32_out[9] u_rca32_out[10] u_rca32_out[11] u_rca32_out[12] u_rca32_out[13] u_rca32_out[14] u_rca32_out[15] u_rca32_out[16] u_rca32_out[17] u_rca32_out[18] u_rca32_out[19] u_rca32_out[20] u_rca32_out[21] u_rca32_out[22] u_rca32_out[23] u_rca32_out[24] u_rca32_out[25] u_rca32_out[26] u_rca32_out[27] u_rca32_out[28] u_rca32_out[29] u_rca32_out[30] u_rca32_out[31] u_rca32_out[32]
.names vdd
1
.names gnd
0
.subckt ha a=a[0] b=b[0] ha_xor0=u_rca32_ha_xor0 ha_and0=u_rca32_ha_and0
.subckt fa a=a[1] b=b[1] cin=u_rca32_ha_and0 fa_xor1=u_rca32_fa1_xor1 fa_or0=u_rca32_fa1_or0
.subckt fa a=a[2] b=b[2] cin=u_rca32_fa1_or0 fa_xor1=u_rca32_fa2_xor1 fa_or0=u_rca32_fa2_or0
.subckt fa a=a[3] b=b[3] cin=u_rca32_fa2_or0 fa_xor1=u_rca32_fa3_xor1 fa_or0=u_rca32_fa3_or0
.subckt fa a=a[4] b=b[4] cin=u_rca32_fa3_or0 fa_xor1=u_rca32_fa4_xor1 fa_or0=u_rca32_fa4_or0
.subckt fa a=a[5] b=b[5] cin=u_rca32_fa4_or0 fa_xor1=u_rca32_fa5_xor1 fa_or0=u_rca32_fa5_or0
.subckt fa a=a[6] b=b[6] cin=u_rca32_fa5_or0 fa_xor1=u_rca32_fa6_xor1 fa_or0=u_rca32_fa6_or0
.subckt fa a=a[7] b=b[7] cin=u_rca32_fa6_or0 fa_xor1=u_rca32_fa7_xor1 fa_or0=u_rca32_fa7_or0
.subckt fa a=a[8] b=b[8] cin=u_rca32_fa7_or0 fa_xor1=u_rca32_fa8_xor1 fa_or0=u_rca32_fa8_or0
.subckt fa a=a[9] b=b[9] cin=u_rca32_fa8_or0 fa_xor1=u_rca32_fa9_xor1 fa_or0=u_rca32_fa9_or0
.subckt fa a=a[10] b=b[10] cin=u_rca32_fa9_or0 fa_xor1=u_rca32_fa10_xor1 fa_or0=u_rca32_fa10_or0
.subckt fa a=a[11] b=b[11] cin=u_rca32_fa10_or0 fa_xor1=u_rca32_fa11_xor1 fa_or0=u_rca32_fa11_or0
.subckt fa a=a[12] b=b[12] cin=u_rca32_fa11_or0 fa_xor1=u_rca32_fa12_xor1 fa_or0=u_rca32_fa12_or0
.subckt fa a=a[13] b=b[13] cin=u_rca32_fa12_or0 fa_xor1=u_rca32_fa13_xor1 fa_or0=u_rca32_fa13_or0
.subckt fa a=a[14] b=b[14] cin=u_rca32_fa13_or0 fa_xor1=u_rca32_fa14_xor1 fa_or0=u_rca32_fa14_or0
.subckt fa a=a[15] b=b[15] cin=u_rca32_fa14_or0 fa_xor1=u_rca32_fa15_xor1 fa_or0=u_rca32_fa15_or0
.subckt fa a=a[16] b=b[16] cin=u_rca32_fa15_or0 fa_xor1=u_rca32_fa16_xor1 fa_or0=u_rca32_fa16_or0
.subckt fa a=a[17] b=b[17] cin=u_rca32_fa16_or0 fa_xor1=u_rca32_fa17_xor1 fa_or0=u_rca32_fa17_or0
.subckt fa a=a[18] b=b[18] cin=u_rca32_fa17_or0 fa_xor1=u_rca32_fa18_xor1 fa_or0=u_rca32_fa18_or0
.subckt fa a=a[19] b=b[19] cin=u_rca32_fa18_or0 fa_xor1=u_rca32_fa19_xor1 fa_or0=u_rca32_fa19_or0
.subckt fa a=a[20] b=b[20] cin=u_rca32_fa19_or0 fa_xor1=u_rca32_fa20_xor1 fa_or0=u_rca32_fa20_or0
.subckt fa a=a[21] b=b[21] cin=u_rca32_fa20_or0 fa_xor1=u_rca32_fa21_xor1 fa_or0=u_rca32_fa21_or0
.subckt fa a=a[22] b=b[22] cin=u_rca32_fa21_or0 fa_xor1=u_rca32_fa22_xor1 fa_or0=u_rca32_fa22_or0
.subckt fa a=a[23] b=b[23] cin=u_rca32_fa22_or0 fa_xor1=u_rca32_fa23_xor1 fa_or0=u_rca32_fa23_or0
.subckt fa a=a[24] b=b[24] cin=u_rca32_fa23_or0 fa_xor1=u_rca32_fa24_xor1 fa_or0=u_rca32_fa24_or0
.subckt fa a=a[25] b=b[25] cin=u_rca32_fa24_or0 fa_xor1=u_rca32_fa25_xor1 fa_or0=u_rca32_fa25_or0
.subckt fa a=a[26] b=b[26] cin=u_rca32_fa25_or0 fa_xor1=u_rca32_fa26_xor1 fa_or0=u_rca32_fa26_or0
.subckt fa a=a[27] b=b[27] cin=u_rca32_fa26_or0 fa_xor1=u_rca32_fa27_xor1 fa_or0=u_rca32_fa27_or0
.subckt fa a=a[28] b=b[28] cin=u_rca32_fa27_or0 fa_xor1=u_rca32_fa28_xor1 fa_or0=u_rca32_fa28_or0
.subckt fa a=a[29] b=b[29] cin=u_rca32_fa28_or0 fa_xor1=u_rca32_fa29_xor1 fa_or0=u_rca32_fa29_or0
.subckt fa a=a[30] b=b[30] cin=u_rca32_fa29_or0 fa_xor1=u_rca32_fa30_xor1 fa_or0=u_rca32_fa30_or0
.subckt fa a=a[31] b=b[31] cin=u_rca32_fa30_or0 fa_xor1=u_rca32_fa31_xor1 fa_or0=u_rca32_fa31_or0
.names u_rca32_ha_xor0 u_rca32_out[0]
1 1
.names u_rca32_fa1_xor1 u_rca32_out[1]
1 1
.names u_rca32_fa2_xor1 u_rca32_out[2]
1 1
.names u_rca32_fa3_xor1 u_rca32_out[3]
1 1
.names u_rca32_fa4_xor1 u_rca32_out[4]
1 1
.names u_rca32_fa5_xor1 u_rca32_out[5]
1 1
.names u_rca32_fa6_xor1 u_rca32_out[6]
1 1
.names u_rca32_fa7_xor1 u_rca32_out[7]
1 1
.names u_rca32_fa8_xor1 u_rca32_out[8]
1 1
.names u_rca32_fa9_xor1 u_rca32_out[9]
1 1
.names u_rca32_fa10_xor1 u_rca32_out[10]
1 1
.names u_rca32_fa11_xor1 u_rca32_out[11]
1 1
.names u_rca32_fa12_xor1 u_rca32_out[12]
1 1
.names u_rca32_fa13_xor1 u_rca32_out[13]
1 1
.names u_rca32_fa14_xor1 u_rca32_out[14]
1 1
.names u_rca32_fa15_xor1 u_rca32_out[15]
1 1
.names u_rca32_fa16_xor1 u_rca32_out[16]
1 1
.names u_rca32_fa17_xor1 u_rca32_out[17]
1 1
.names u_rca32_fa18_xor1 u_rca32_out[18]
1 1
.names u_rca32_fa19_xor1 u_rca32_out[19]
1 1
.names u_rca32_fa20_xor1 u_rca32_out[20]
1 1
.names u_rca32_fa21_xor1 u_rca32_out[21]
1 1
.names u_rca32_fa22_xor1 u_rca32_out[22]
1 1
.names u_rca32_fa23_xor1 u_rca32_out[23]
1 1
.names u_rca32_fa24_xor1 u_rca32_out[24]
1 1
.names u_rca32_fa25_xor1 u_rca32_out[25]
1 1
.names u_rca32_fa26_xor1 u_rca32_out[26]
1 1
.names u_rca32_fa27_xor1 u_rca32_out[27]
1 1
.names u_rca32_fa28_xor1 u_rca32_out[28]
1 1
.names u_rca32_fa29_xor1 u_rca32_out[29]
1 1
.names u_rca32_fa30_xor1 u_rca32_out[30]
1 1
.names u_rca32_fa31_xor1 u_rca32_out[31]
1 1
.names u_rca32_fa31_or0 u_rca32_out[32]
1 1
.end
.model fa
.inputs a b cin
.outputs fa_xor1 fa_or0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=fa_xor0
.subckt and_gate a=a b=b out=fa_and0
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
.end
.model ha
.inputs a b
.outputs ha_xor0 ha_and0
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=ha_xor0
.subckt and_gate a=a b=b out=ha_and0
.end
.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end
.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end
.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end
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