56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
561 lines
36 KiB
Plaintext
561 lines
36 KiB
Plaintext
.model s_dadda_rca12
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11]
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.outputs s_dadda_rca12_out[0] s_dadda_rca12_out[1] s_dadda_rca12_out[2] s_dadda_rca12_out[3] s_dadda_rca12_out[4] s_dadda_rca12_out[5] s_dadda_rca12_out[6] s_dadda_rca12_out[7] s_dadda_rca12_out[8] s_dadda_rca12_out[9] s_dadda_rca12_out[10] s_dadda_rca12_out[11] s_dadda_rca12_out[12] s_dadda_rca12_out[13] s_dadda_rca12_out[14] s_dadda_rca12_out[15] s_dadda_rca12_out[16] s_dadda_rca12_out[17] s_dadda_rca12_out[18] s_dadda_rca12_out[19] s_dadda_rca12_out[20] s_dadda_rca12_out[21] s_dadda_rca12_out[22] s_dadda_rca12_out[23]
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.names vdd
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1
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.names gnd
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0
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.subckt and_gate a=a[9] b=b[0] out=s_dadda_rca12_and_9_0
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.subckt and_gate a=a[8] b=b[1] out=s_dadda_rca12_and_8_1
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.subckt ha a=s_dadda_rca12_and_9_0 b=s_dadda_rca12_and_8_1 ha_xor0=s_dadda_rca12_ha0_xor0 ha_and0=s_dadda_rca12_ha0_and0
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.subckt and_gate a=a[10] b=b[0] out=s_dadda_rca12_and_10_0
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.subckt and_gate a=a[9] b=b[1] out=s_dadda_rca12_and_9_1
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.subckt fa a=s_dadda_rca12_ha0_and0 b=s_dadda_rca12_and_10_0 cin=s_dadda_rca12_and_9_1 fa_xor1=s_dadda_rca12_fa0_xor1 fa_or0=s_dadda_rca12_fa0_or0
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.subckt and_gate a=a[8] b=b[2] out=s_dadda_rca12_and_8_2
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.subckt and_gate a=a[7] b=b[3] out=s_dadda_rca12_and_7_3
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.subckt ha a=s_dadda_rca12_and_8_2 b=s_dadda_rca12_and_7_3 ha_xor0=s_dadda_rca12_ha1_xor0 ha_and0=s_dadda_rca12_ha1_and0
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.subckt nand_gate a=a[11] b=b[0] out=s_dadda_rca12_nand_11_0
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.subckt fa a=s_dadda_rca12_ha1_and0 b=s_dadda_rca12_fa0_or0 cin=s_dadda_rca12_nand_11_0 fa_xor1=s_dadda_rca12_fa1_xor1 fa_or0=s_dadda_rca12_fa1_or0
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.subckt and_gate a=a[10] b=b[1] out=s_dadda_rca12_and_10_1
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.subckt and_gate a=a[9] b=b[2] out=s_dadda_rca12_and_9_2
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.subckt and_gate a=a[8] b=b[3] out=s_dadda_rca12_and_8_3
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.subckt fa a=s_dadda_rca12_and_10_1 b=s_dadda_rca12_and_9_2 cin=s_dadda_rca12_and_8_3 fa_xor1=s_dadda_rca12_fa2_xor1 fa_or0=s_dadda_rca12_fa2_or0
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.subckt and_gate a=a[7] b=b[4] out=s_dadda_rca12_and_7_4
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.subckt and_gate a=a[6] b=b[5] out=s_dadda_rca12_and_6_5
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.subckt ha a=s_dadda_rca12_and_7_4 b=s_dadda_rca12_and_6_5 ha_xor0=s_dadda_rca12_ha2_xor0 ha_and0=s_dadda_rca12_ha2_and0
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.subckt fa a=s_dadda_rca12_ha2_and0 b=s_dadda_rca12_fa2_or0 cin=s_dadda_rca12_fa1_or0 fa_xor1=s_dadda_rca12_fa3_xor1 fa_or0=s_dadda_rca12_fa3_or0
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.subckt nand_gate a=a[11] b=b[1] out=s_dadda_rca12_nand_11_1
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.subckt and_gate a=a[10] b=b[2] out=s_dadda_rca12_and_10_2
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.subckt fa a=vdd b=s_dadda_rca12_nand_11_1 cin=s_dadda_rca12_and_10_2 fa_xor1=s_dadda_rca12_fa4_xor1 fa_or0=s_dadda_rca12_fa4_or0
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.subckt and_gate a=a[9] b=b[3] out=s_dadda_rca12_and_9_3
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.subckt and_gate a=a[8] b=b[4] out=s_dadda_rca12_and_8_4
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.subckt and_gate a=a[7] b=b[5] out=s_dadda_rca12_and_7_5
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.subckt fa a=s_dadda_rca12_and_9_3 b=s_dadda_rca12_and_8_4 cin=s_dadda_rca12_and_7_5 fa_xor1=s_dadda_rca12_fa5_xor1 fa_or0=s_dadda_rca12_fa5_or0
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.subckt fa a=s_dadda_rca12_fa5_or0 b=s_dadda_rca12_fa4_or0 cin=s_dadda_rca12_fa3_or0 fa_xor1=s_dadda_rca12_fa6_xor1 fa_or0=s_dadda_rca12_fa6_or0
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.subckt nand_gate a=a[11] b=b[2] out=s_dadda_rca12_nand_11_2
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.subckt and_gate a=a[10] b=b[3] out=s_dadda_rca12_and_10_3
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.subckt and_gate a=a[9] b=b[4] out=s_dadda_rca12_and_9_4
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.subckt fa a=s_dadda_rca12_nand_11_2 b=s_dadda_rca12_and_10_3 cin=s_dadda_rca12_and_9_4 fa_xor1=s_dadda_rca12_fa7_xor1 fa_or0=s_dadda_rca12_fa7_or0
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.subckt nand_gate a=a[11] b=b[3] out=s_dadda_rca12_nand_11_3
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.subckt fa a=s_dadda_rca12_fa7_or0 b=s_dadda_rca12_fa6_or0 cin=s_dadda_rca12_nand_11_3 fa_xor1=s_dadda_rca12_fa8_xor1 fa_or0=s_dadda_rca12_fa8_or0
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.subckt and_gate a=a[4] b=b[0] out=s_dadda_rca12_and_4_0
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.subckt and_gate a=a[3] b=b[1] out=s_dadda_rca12_and_3_1
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.subckt ha a=s_dadda_rca12_and_4_0 b=s_dadda_rca12_and_3_1 ha_xor0=s_dadda_rca12_ha3_xor0 ha_and0=s_dadda_rca12_ha3_and0
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.subckt and_gate a=a[5] b=b[0] out=s_dadda_rca12_and_5_0
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.subckt and_gate a=a[4] b=b[1] out=s_dadda_rca12_and_4_1
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.subckt fa a=s_dadda_rca12_ha3_and0 b=s_dadda_rca12_and_5_0 cin=s_dadda_rca12_and_4_1 fa_xor1=s_dadda_rca12_fa9_xor1 fa_or0=s_dadda_rca12_fa9_or0
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.subckt and_gate a=a[3] b=b[2] out=s_dadda_rca12_and_3_2
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.subckt and_gate a=a[2] b=b[3] out=s_dadda_rca12_and_2_3
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.subckt ha a=s_dadda_rca12_and_3_2 b=s_dadda_rca12_and_2_3 ha_xor0=s_dadda_rca12_ha4_xor0 ha_and0=s_dadda_rca12_ha4_and0
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.subckt and_gate a=a[6] b=b[0] out=s_dadda_rca12_and_6_0
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.subckt fa a=s_dadda_rca12_ha4_and0 b=s_dadda_rca12_fa9_or0 cin=s_dadda_rca12_and_6_0 fa_xor1=s_dadda_rca12_fa10_xor1 fa_or0=s_dadda_rca12_fa10_or0
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.subckt and_gate a=a[5] b=b[1] out=s_dadda_rca12_and_5_1
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.subckt and_gate a=a[4] b=b[2] out=s_dadda_rca12_and_4_2
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.subckt and_gate a=a[3] b=b[3] out=s_dadda_rca12_and_3_3
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.subckt fa a=s_dadda_rca12_and_5_1 b=s_dadda_rca12_and_4_2 cin=s_dadda_rca12_and_3_3 fa_xor1=s_dadda_rca12_fa11_xor1 fa_or0=s_dadda_rca12_fa11_or0
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.subckt and_gate a=a[2] b=b[4] out=s_dadda_rca12_and_2_4
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.subckt and_gate a=a[1] b=b[5] out=s_dadda_rca12_and_1_5
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.subckt ha a=s_dadda_rca12_and_2_4 b=s_dadda_rca12_and_1_5 ha_xor0=s_dadda_rca12_ha5_xor0 ha_and0=s_dadda_rca12_ha5_and0
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.subckt fa a=s_dadda_rca12_ha5_and0 b=s_dadda_rca12_fa11_or0 cin=s_dadda_rca12_fa10_or0 fa_xor1=s_dadda_rca12_fa12_xor1 fa_or0=s_dadda_rca12_fa12_or0
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.subckt and_gate a=a[7] b=b[0] out=s_dadda_rca12_and_7_0
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.subckt and_gate a=a[6] b=b[1] out=s_dadda_rca12_and_6_1
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.subckt and_gate a=a[5] b=b[2] out=s_dadda_rca12_and_5_2
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.subckt fa a=s_dadda_rca12_and_7_0 b=s_dadda_rca12_and_6_1 cin=s_dadda_rca12_and_5_2 fa_xor1=s_dadda_rca12_fa13_xor1 fa_or0=s_dadda_rca12_fa13_or0
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.subckt and_gate a=a[4] b=b[3] out=s_dadda_rca12_and_4_3
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.subckt and_gate a=a[3] b=b[4] out=s_dadda_rca12_and_3_4
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.subckt and_gate a=a[2] b=b[5] out=s_dadda_rca12_and_2_5
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.subckt fa a=s_dadda_rca12_and_4_3 b=s_dadda_rca12_and_3_4 cin=s_dadda_rca12_and_2_5 fa_xor1=s_dadda_rca12_fa14_xor1 fa_or0=s_dadda_rca12_fa14_or0
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.subckt and_gate a=a[1] b=b[6] out=s_dadda_rca12_and_1_6
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.subckt and_gate a=a[0] b=b[7] out=s_dadda_rca12_and_0_7
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.subckt ha a=s_dadda_rca12_and_1_6 b=s_dadda_rca12_and_0_7 ha_xor0=s_dadda_rca12_ha6_xor0 ha_and0=s_dadda_rca12_ha6_and0
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.subckt fa a=s_dadda_rca12_ha6_and0 b=s_dadda_rca12_fa14_or0 cin=s_dadda_rca12_fa13_or0 fa_xor1=s_dadda_rca12_fa15_xor1 fa_or0=s_dadda_rca12_fa15_or0
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.subckt and_gate a=a[8] b=b[0] out=s_dadda_rca12_and_8_0
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.subckt and_gate a=a[7] b=b[1] out=s_dadda_rca12_and_7_1
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.subckt fa a=s_dadda_rca12_fa12_or0 b=s_dadda_rca12_and_8_0 cin=s_dadda_rca12_and_7_1 fa_xor1=s_dadda_rca12_fa16_xor1 fa_or0=s_dadda_rca12_fa16_or0
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.subckt and_gate a=a[6] b=b[2] out=s_dadda_rca12_and_6_2
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.subckt and_gate a=a[5] b=b[3] out=s_dadda_rca12_and_5_3
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.subckt and_gate a=a[4] b=b[4] out=s_dadda_rca12_and_4_4
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.subckt fa a=s_dadda_rca12_and_6_2 b=s_dadda_rca12_and_5_3 cin=s_dadda_rca12_and_4_4 fa_xor1=s_dadda_rca12_fa17_xor1 fa_or0=s_dadda_rca12_fa17_or0
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.subckt and_gate a=a[3] b=b[5] out=s_dadda_rca12_and_3_5
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.subckt and_gate a=a[2] b=b[6] out=s_dadda_rca12_and_2_6
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.subckt and_gate a=a[1] b=b[7] out=s_dadda_rca12_and_1_7
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.subckt fa a=s_dadda_rca12_and_3_5 b=s_dadda_rca12_and_2_6 cin=s_dadda_rca12_and_1_7 fa_xor1=s_dadda_rca12_fa18_xor1 fa_or0=s_dadda_rca12_fa18_or0
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.subckt and_gate a=a[0] b=b[8] out=s_dadda_rca12_and_0_8
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.subckt ha a=s_dadda_rca12_and_0_8 b=s_dadda_rca12_fa15_xor1 ha_xor0=s_dadda_rca12_ha7_xor0 ha_and0=s_dadda_rca12_ha7_and0
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.subckt fa a=s_dadda_rca12_ha7_and0 b=s_dadda_rca12_fa18_or0 cin=s_dadda_rca12_fa17_or0 fa_xor1=s_dadda_rca12_fa19_xor1 fa_or0=s_dadda_rca12_fa19_or0
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.subckt and_gate a=a[7] b=b[2] out=s_dadda_rca12_and_7_2
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.subckt fa a=s_dadda_rca12_fa16_or0 b=s_dadda_rca12_fa15_or0 cin=s_dadda_rca12_and_7_2 fa_xor1=s_dadda_rca12_fa20_xor1 fa_or0=s_dadda_rca12_fa20_or0
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.subckt and_gate a=a[6] b=b[3] out=s_dadda_rca12_and_6_3
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.subckt and_gate a=a[5] b=b[4] out=s_dadda_rca12_and_5_4
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.subckt and_gate a=a[4] b=b[5] out=s_dadda_rca12_and_4_5
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.subckt fa a=s_dadda_rca12_and_6_3 b=s_dadda_rca12_and_5_4 cin=s_dadda_rca12_and_4_5 fa_xor1=s_dadda_rca12_fa21_xor1 fa_or0=s_dadda_rca12_fa21_or0
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.subckt and_gate a=a[3] b=b[6] out=s_dadda_rca12_and_3_6
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.subckt and_gate a=a[2] b=b[7] out=s_dadda_rca12_and_2_7
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.subckt and_gate a=a[1] b=b[8] out=s_dadda_rca12_and_1_8
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.subckt fa a=s_dadda_rca12_and_3_6 b=s_dadda_rca12_and_2_7 cin=s_dadda_rca12_and_1_8 fa_xor1=s_dadda_rca12_fa22_xor1 fa_or0=s_dadda_rca12_fa22_or0
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.subckt and_gate a=a[0] b=b[9] out=s_dadda_rca12_and_0_9
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.subckt fa a=s_dadda_rca12_and_0_9 b=s_dadda_rca12_ha0_xor0 cin=s_dadda_rca12_fa19_xor1 fa_xor1=s_dadda_rca12_fa23_xor1 fa_or0=s_dadda_rca12_fa23_or0
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.subckt fa a=s_dadda_rca12_fa23_or0 b=s_dadda_rca12_fa22_or0 cin=s_dadda_rca12_fa21_or0 fa_xor1=s_dadda_rca12_fa24_xor1 fa_or0=s_dadda_rca12_fa24_or0
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.subckt and_gate a=a[6] b=b[4] out=s_dadda_rca12_and_6_4
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.subckt fa a=s_dadda_rca12_fa20_or0 b=s_dadda_rca12_fa19_or0 cin=s_dadda_rca12_and_6_4 fa_xor1=s_dadda_rca12_fa25_xor1 fa_or0=s_dadda_rca12_fa25_or0
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.subckt and_gate a=a[5] b=b[5] out=s_dadda_rca12_and_5_5
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.subckt and_gate a=a[4] b=b[6] out=s_dadda_rca12_and_4_6
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.subckt and_gate a=a[3] b=b[7] out=s_dadda_rca12_and_3_7
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.subckt fa a=s_dadda_rca12_and_5_5 b=s_dadda_rca12_and_4_6 cin=s_dadda_rca12_and_3_7 fa_xor1=s_dadda_rca12_fa26_xor1 fa_or0=s_dadda_rca12_fa26_or0
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.subckt and_gate a=a[2] b=b[8] out=s_dadda_rca12_and_2_8
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.subckt and_gate a=a[1] b=b[9] out=s_dadda_rca12_and_1_9
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.subckt and_gate a=a[0] b=b[10] out=s_dadda_rca12_and_0_10
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.subckt fa a=s_dadda_rca12_and_2_8 b=s_dadda_rca12_and_1_9 cin=s_dadda_rca12_and_0_10 fa_xor1=s_dadda_rca12_fa27_xor1 fa_or0=s_dadda_rca12_fa27_or0
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.subckt fa a=s_dadda_rca12_fa0_xor1 b=s_dadda_rca12_ha1_xor0 cin=s_dadda_rca12_fa24_xor1 fa_xor1=s_dadda_rca12_fa28_xor1 fa_or0=s_dadda_rca12_fa28_or0
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.subckt fa a=s_dadda_rca12_fa28_or0 b=s_dadda_rca12_fa27_or0 cin=s_dadda_rca12_fa26_or0 fa_xor1=s_dadda_rca12_fa29_xor1 fa_or0=s_dadda_rca12_fa29_or0
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.subckt and_gate a=a[5] b=b[6] out=s_dadda_rca12_and_5_6
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.subckt fa a=s_dadda_rca12_fa25_or0 b=s_dadda_rca12_fa24_or0 cin=s_dadda_rca12_and_5_6 fa_xor1=s_dadda_rca12_fa30_xor1 fa_or0=s_dadda_rca12_fa30_or0
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.subckt and_gate a=a[4] b=b[7] out=s_dadda_rca12_and_4_7
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.subckt and_gate a=a[3] b=b[8] out=s_dadda_rca12_and_3_8
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.subckt and_gate a=a[2] b=b[9] out=s_dadda_rca12_and_2_9
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.subckt fa a=s_dadda_rca12_and_4_7 b=s_dadda_rca12_and_3_8 cin=s_dadda_rca12_and_2_9 fa_xor1=s_dadda_rca12_fa31_xor1 fa_or0=s_dadda_rca12_fa31_or0
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.subckt and_gate a=a[1] b=b[10] out=s_dadda_rca12_and_1_10
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.subckt nand_gate a=a[0] b=b[11] out=s_dadda_rca12_nand_0_11
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.subckt fa a=s_dadda_rca12_and_1_10 b=s_dadda_rca12_nand_0_11 cin=s_dadda_rca12_fa1_xor1 fa_xor1=s_dadda_rca12_fa32_xor1 fa_or0=s_dadda_rca12_fa32_or0
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.subckt fa a=s_dadda_rca12_fa2_xor1 b=s_dadda_rca12_ha2_xor0 cin=s_dadda_rca12_fa29_xor1 fa_xor1=s_dadda_rca12_fa33_xor1 fa_or0=s_dadda_rca12_fa33_or0
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.subckt fa a=s_dadda_rca12_fa33_or0 b=s_dadda_rca12_fa32_or0 cin=s_dadda_rca12_fa31_or0 fa_xor1=s_dadda_rca12_fa34_xor1 fa_or0=s_dadda_rca12_fa34_or0
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.subckt and_gate a=a[6] b=b[6] out=s_dadda_rca12_and_6_6
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.subckt fa a=s_dadda_rca12_fa30_or0 b=s_dadda_rca12_fa29_or0 cin=s_dadda_rca12_and_6_6 fa_xor1=s_dadda_rca12_fa35_xor1 fa_or0=s_dadda_rca12_fa35_or0
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.subckt and_gate a=a[5] b=b[7] out=s_dadda_rca12_and_5_7
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.subckt and_gate a=a[4] b=b[8] out=s_dadda_rca12_and_4_8
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.subckt and_gate a=a[3] b=b[9] out=s_dadda_rca12_and_3_9
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.subckt fa a=s_dadda_rca12_and_5_7 b=s_dadda_rca12_and_4_8 cin=s_dadda_rca12_and_3_9 fa_xor1=s_dadda_rca12_fa36_xor1 fa_or0=s_dadda_rca12_fa36_or0
|
|
.subckt and_gate a=a[2] b=b[10] out=s_dadda_rca12_and_2_10
|
|
.subckt nand_gate a=a[1] b=b[11] out=s_dadda_rca12_nand_1_11
|
|
.subckt fa a=s_dadda_rca12_and_2_10 b=s_dadda_rca12_nand_1_11 cin=s_dadda_rca12_fa3_xor1 fa_xor1=s_dadda_rca12_fa37_xor1 fa_or0=s_dadda_rca12_fa37_or0
|
|
.subckt fa a=s_dadda_rca12_fa4_xor1 b=s_dadda_rca12_fa5_xor1 cin=s_dadda_rca12_fa34_xor1 fa_xor1=s_dadda_rca12_fa38_xor1 fa_or0=s_dadda_rca12_fa38_or0
|
|
.subckt fa a=s_dadda_rca12_fa38_or0 b=s_dadda_rca12_fa37_or0 cin=s_dadda_rca12_fa36_or0 fa_xor1=s_dadda_rca12_fa39_xor1 fa_or0=s_dadda_rca12_fa39_or0
|
|
.subckt and_gate a=a[8] b=b[5] out=s_dadda_rca12_and_8_5
|
|
.subckt fa a=s_dadda_rca12_fa35_or0 b=s_dadda_rca12_fa34_or0 cin=s_dadda_rca12_and_8_5 fa_xor1=s_dadda_rca12_fa40_xor1 fa_or0=s_dadda_rca12_fa40_or0
|
|
.subckt and_gate a=a[7] b=b[6] out=s_dadda_rca12_and_7_6
|
|
.subckt and_gate a=a[6] b=b[7] out=s_dadda_rca12_and_6_7
|
|
.subckt and_gate a=a[5] b=b[8] out=s_dadda_rca12_and_5_8
|
|
.subckt fa a=s_dadda_rca12_and_7_6 b=s_dadda_rca12_and_6_7 cin=s_dadda_rca12_and_5_8 fa_xor1=s_dadda_rca12_fa41_xor1 fa_or0=s_dadda_rca12_fa41_or0
|
|
.subckt and_gate a=a[4] b=b[9] out=s_dadda_rca12_and_4_9
|
|
.subckt and_gate a=a[3] b=b[10] out=s_dadda_rca12_and_3_10
|
|
.subckt nand_gate a=a[2] b=b[11] out=s_dadda_rca12_nand_2_11
|
|
.subckt fa a=s_dadda_rca12_and_4_9 b=s_dadda_rca12_and_3_10 cin=s_dadda_rca12_nand_2_11 fa_xor1=s_dadda_rca12_fa42_xor1 fa_or0=s_dadda_rca12_fa42_or0
|
|
.subckt fa a=s_dadda_rca12_fa6_xor1 b=s_dadda_rca12_fa7_xor1 cin=s_dadda_rca12_fa39_xor1 fa_xor1=s_dadda_rca12_fa43_xor1 fa_or0=s_dadda_rca12_fa43_or0
|
|
.subckt fa a=s_dadda_rca12_fa43_or0 b=s_dadda_rca12_fa42_or0 cin=s_dadda_rca12_fa41_or0 fa_xor1=s_dadda_rca12_fa44_xor1 fa_or0=s_dadda_rca12_fa44_or0
|
|
.subckt and_gate a=a[10] b=b[4] out=s_dadda_rca12_and_10_4
|
|
.subckt fa a=s_dadda_rca12_fa40_or0 b=s_dadda_rca12_fa39_or0 cin=s_dadda_rca12_and_10_4 fa_xor1=s_dadda_rca12_fa45_xor1 fa_or0=s_dadda_rca12_fa45_or0
|
|
.subckt and_gate a=a[9] b=b[5] out=s_dadda_rca12_and_9_5
|
|
.subckt and_gate a=a[8] b=b[6] out=s_dadda_rca12_and_8_6
|
|
.subckt and_gate a=a[7] b=b[7] out=s_dadda_rca12_and_7_7
|
|
.subckt fa a=s_dadda_rca12_and_9_5 b=s_dadda_rca12_and_8_6 cin=s_dadda_rca12_and_7_7 fa_xor1=s_dadda_rca12_fa46_xor1 fa_or0=s_dadda_rca12_fa46_or0
|
|
.subckt and_gate a=a[6] b=b[8] out=s_dadda_rca12_and_6_8
|
|
.subckt and_gate a=a[5] b=b[9] out=s_dadda_rca12_and_5_9
|
|
.subckt and_gate a=a[4] b=b[10] out=s_dadda_rca12_and_4_10
|
|
.subckt fa a=s_dadda_rca12_and_6_8 b=s_dadda_rca12_and_5_9 cin=s_dadda_rca12_and_4_10 fa_xor1=s_dadda_rca12_fa47_xor1 fa_or0=s_dadda_rca12_fa47_or0
|
|
.subckt nand_gate a=a[3] b=b[11] out=s_dadda_rca12_nand_3_11
|
|
.subckt fa a=s_dadda_rca12_nand_3_11 b=s_dadda_rca12_fa8_xor1 cin=s_dadda_rca12_fa44_xor1 fa_xor1=s_dadda_rca12_fa48_xor1 fa_or0=s_dadda_rca12_fa48_or0
|
|
.subckt fa a=s_dadda_rca12_fa48_or0 b=s_dadda_rca12_fa47_or0 cin=s_dadda_rca12_fa46_or0 fa_xor1=s_dadda_rca12_fa49_xor1 fa_or0=s_dadda_rca12_fa49_or0
|
|
.subckt fa a=s_dadda_rca12_fa45_or0 b=s_dadda_rca12_fa44_or0 cin=s_dadda_rca12_fa8_or0 fa_xor1=s_dadda_rca12_fa50_xor1 fa_or0=s_dadda_rca12_fa50_or0
|
|
.subckt nand_gate a=a[11] b=b[4] out=s_dadda_rca12_nand_11_4
|
|
.subckt and_gate a=a[10] b=b[5] out=s_dadda_rca12_and_10_5
|
|
.subckt and_gate a=a[9] b=b[6] out=s_dadda_rca12_and_9_6
|
|
.subckt fa a=s_dadda_rca12_nand_11_4 b=s_dadda_rca12_and_10_5 cin=s_dadda_rca12_and_9_6 fa_xor1=s_dadda_rca12_fa51_xor1 fa_or0=s_dadda_rca12_fa51_or0
|
|
.subckt and_gate a=a[8] b=b[7] out=s_dadda_rca12_and_8_7
|
|
.subckt and_gate a=a[7] b=b[8] out=s_dadda_rca12_and_7_8
|
|
.subckt and_gate a=a[6] b=b[9] out=s_dadda_rca12_and_6_9
|
|
.subckt fa a=s_dadda_rca12_and_8_7 b=s_dadda_rca12_and_7_8 cin=s_dadda_rca12_and_6_9 fa_xor1=s_dadda_rca12_fa52_xor1 fa_or0=s_dadda_rca12_fa52_or0
|
|
.subckt and_gate a=a[5] b=b[10] out=s_dadda_rca12_and_5_10
|
|
.subckt nand_gate a=a[4] b=b[11] out=s_dadda_rca12_nand_4_11
|
|
.subckt fa a=s_dadda_rca12_and_5_10 b=s_dadda_rca12_nand_4_11 cin=s_dadda_rca12_fa49_xor1 fa_xor1=s_dadda_rca12_fa53_xor1 fa_or0=s_dadda_rca12_fa53_or0
|
|
.subckt fa a=s_dadda_rca12_fa53_or0 b=s_dadda_rca12_fa52_or0 cin=s_dadda_rca12_fa51_or0 fa_xor1=s_dadda_rca12_fa54_xor1 fa_or0=s_dadda_rca12_fa54_or0
|
|
.subckt nand_gate a=a[11] b=b[5] out=s_dadda_rca12_nand_11_5
|
|
.subckt fa a=s_dadda_rca12_fa50_or0 b=s_dadda_rca12_fa49_or0 cin=s_dadda_rca12_nand_11_5 fa_xor1=s_dadda_rca12_fa55_xor1 fa_or0=s_dadda_rca12_fa55_or0
|
|
.subckt and_gate a=a[10] b=b[6] out=s_dadda_rca12_and_10_6
|
|
.subckt and_gate a=a[9] b=b[7] out=s_dadda_rca12_and_9_7
|
|
.subckt and_gate a=a[8] b=b[8] out=s_dadda_rca12_and_8_8
|
|
.subckt fa a=s_dadda_rca12_and_10_6 b=s_dadda_rca12_and_9_7 cin=s_dadda_rca12_and_8_8 fa_xor1=s_dadda_rca12_fa56_xor1 fa_or0=s_dadda_rca12_fa56_or0
|
|
.subckt and_gate a=a[7] b=b[9] out=s_dadda_rca12_and_7_9
|
|
.subckt and_gate a=a[6] b=b[10] out=s_dadda_rca12_and_6_10
|
|
.subckt nand_gate a=a[5] b=b[11] out=s_dadda_rca12_nand_5_11
|
|
.subckt fa a=s_dadda_rca12_and_7_9 b=s_dadda_rca12_and_6_10 cin=s_dadda_rca12_nand_5_11 fa_xor1=s_dadda_rca12_fa57_xor1 fa_or0=s_dadda_rca12_fa57_or0
|
|
.subckt fa a=s_dadda_rca12_fa57_or0 b=s_dadda_rca12_fa56_or0 cin=s_dadda_rca12_fa55_or0 fa_xor1=s_dadda_rca12_fa58_xor1 fa_or0=s_dadda_rca12_fa58_or0
|
|
.subckt nand_gate a=a[11] b=b[6] out=s_dadda_rca12_nand_11_6
|
|
.subckt and_gate a=a[10] b=b[7] out=s_dadda_rca12_and_10_7
|
|
.subckt fa a=s_dadda_rca12_fa54_or0 b=s_dadda_rca12_nand_11_6 cin=s_dadda_rca12_and_10_7 fa_xor1=s_dadda_rca12_fa59_xor1 fa_or0=s_dadda_rca12_fa59_or0
|
|
.subckt and_gate a=a[9] b=b[8] out=s_dadda_rca12_and_9_8
|
|
.subckt and_gate a=a[8] b=b[9] out=s_dadda_rca12_and_8_9
|
|
.subckt and_gate a=a[7] b=b[10] out=s_dadda_rca12_and_7_10
|
|
.subckt fa a=s_dadda_rca12_and_9_8 b=s_dadda_rca12_and_8_9 cin=s_dadda_rca12_and_7_10 fa_xor1=s_dadda_rca12_fa60_xor1 fa_or0=s_dadda_rca12_fa60_or0
|
|
.subckt fa a=s_dadda_rca12_fa60_or0 b=s_dadda_rca12_fa59_or0 cin=s_dadda_rca12_fa58_or0 fa_xor1=s_dadda_rca12_fa61_xor1 fa_or0=s_dadda_rca12_fa61_or0
|
|
.subckt nand_gate a=a[11] b=b[7] out=s_dadda_rca12_nand_11_7
|
|
.subckt and_gate a=a[10] b=b[8] out=s_dadda_rca12_and_10_8
|
|
.subckt and_gate a=a[9] b=b[9] out=s_dadda_rca12_and_9_9
|
|
.subckt fa a=s_dadda_rca12_nand_11_7 b=s_dadda_rca12_and_10_8 cin=s_dadda_rca12_and_9_9 fa_xor1=s_dadda_rca12_fa62_xor1 fa_or0=s_dadda_rca12_fa62_or0
|
|
.subckt nand_gate a=a[11] b=b[8] out=s_dadda_rca12_nand_11_8
|
|
.subckt fa a=s_dadda_rca12_fa62_or0 b=s_dadda_rca12_fa61_or0 cin=s_dadda_rca12_nand_11_8 fa_xor1=s_dadda_rca12_fa63_xor1 fa_or0=s_dadda_rca12_fa63_or0
|
|
.subckt and_gate a=a[3] b=b[0] out=s_dadda_rca12_and_3_0
|
|
.subckt and_gate a=a[2] b=b[1] out=s_dadda_rca12_and_2_1
|
|
.subckt ha a=s_dadda_rca12_and_3_0 b=s_dadda_rca12_and_2_1 ha_xor0=s_dadda_rca12_ha8_xor0 ha_and0=s_dadda_rca12_ha8_and0
|
|
.subckt and_gate a=a[2] b=b[2] out=s_dadda_rca12_and_2_2
|
|
.subckt and_gate a=a[1] b=b[3] out=s_dadda_rca12_and_1_3
|
|
.subckt fa a=s_dadda_rca12_ha8_and0 b=s_dadda_rca12_and_2_2 cin=s_dadda_rca12_and_1_3 fa_xor1=s_dadda_rca12_fa64_xor1 fa_or0=s_dadda_rca12_fa64_or0
|
|
.subckt and_gate a=a[1] b=b[4] out=s_dadda_rca12_and_1_4
|
|
.subckt and_gate a=a[0] b=b[5] out=s_dadda_rca12_and_0_5
|
|
.subckt fa a=s_dadda_rca12_fa64_or0 b=s_dadda_rca12_and_1_4 cin=s_dadda_rca12_and_0_5 fa_xor1=s_dadda_rca12_fa65_xor1 fa_or0=s_dadda_rca12_fa65_or0
|
|
.subckt and_gate a=a[0] b=b[6] out=s_dadda_rca12_and_0_6
|
|
.subckt fa a=s_dadda_rca12_fa65_or0 b=s_dadda_rca12_and_0_6 cin=s_dadda_rca12_fa10_xor1 fa_xor1=s_dadda_rca12_fa66_xor1 fa_or0=s_dadda_rca12_fa66_or0
|
|
.subckt fa a=s_dadda_rca12_fa66_or0 b=s_dadda_rca12_fa12_xor1 cin=s_dadda_rca12_fa13_xor1 fa_xor1=s_dadda_rca12_fa67_xor1 fa_or0=s_dadda_rca12_fa67_or0
|
|
.subckt fa a=s_dadda_rca12_fa67_or0 b=s_dadda_rca12_fa16_xor1 cin=s_dadda_rca12_fa17_xor1 fa_xor1=s_dadda_rca12_fa68_xor1 fa_or0=s_dadda_rca12_fa68_or0
|
|
.subckt fa a=s_dadda_rca12_fa68_or0 b=s_dadda_rca12_fa20_xor1 cin=s_dadda_rca12_fa21_xor1 fa_xor1=s_dadda_rca12_fa69_xor1 fa_or0=s_dadda_rca12_fa69_or0
|
|
.subckt fa a=s_dadda_rca12_fa69_or0 b=s_dadda_rca12_fa25_xor1 cin=s_dadda_rca12_fa26_xor1 fa_xor1=s_dadda_rca12_fa70_xor1 fa_or0=s_dadda_rca12_fa70_or0
|
|
.subckt fa a=s_dadda_rca12_fa70_or0 b=s_dadda_rca12_fa30_xor1 cin=s_dadda_rca12_fa31_xor1 fa_xor1=s_dadda_rca12_fa71_xor1 fa_or0=s_dadda_rca12_fa71_or0
|
|
.subckt fa a=s_dadda_rca12_fa71_or0 b=s_dadda_rca12_fa35_xor1 cin=s_dadda_rca12_fa36_xor1 fa_xor1=s_dadda_rca12_fa72_xor1 fa_or0=s_dadda_rca12_fa72_or0
|
|
.subckt fa a=s_dadda_rca12_fa72_or0 b=s_dadda_rca12_fa40_xor1 cin=s_dadda_rca12_fa41_xor1 fa_xor1=s_dadda_rca12_fa73_xor1 fa_or0=s_dadda_rca12_fa73_or0
|
|
.subckt fa a=s_dadda_rca12_fa73_or0 b=s_dadda_rca12_fa45_xor1 cin=s_dadda_rca12_fa46_xor1 fa_xor1=s_dadda_rca12_fa74_xor1 fa_or0=s_dadda_rca12_fa74_or0
|
|
.subckt fa a=s_dadda_rca12_fa74_or0 b=s_dadda_rca12_fa50_xor1 cin=s_dadda_rca12_fa51_xor1 fa_xor1=s_dadda_rca12_fa75_xor1 fa_or0=s_dadda_rca12_fa75_or0
|
|
.subckt fa a=s_dadda_rca12_fa75_or0 b=s_dadda_rca12_fa54_xor1 cin=s_dadda_rca12_fa55_xor1 fa_xor1=s_dadda_rca12_fa76_xor1 fa_or0=s_dadda_rca12_fa76_or0
|
|
.subckt nand_gate a=a[6] b=b[11] out=s_dadda_rca12_nand_6_11
|
|
.subckt fa a=s_dadda_rca12_fa76_or0 b=s_dadda_rca12_nand_6_11 cin=s_dadda_rca12_fa58_xor1 fa_xor1=s_dadda_rca12_fa77_xor1 fa_or0=s_dadda_rca12_fa77_or0
|
|
.subckt and_gate a=a[8] b=b[10] out=s_dadda_rca12_and_8_10
|
|
.subckt nand_gate a=a[7] b=b[11] out=s_dadda_rca12_nand_7_11
|
|
.subckt fa a=s_dadda_rca12_fa77_or0 b=s_dadda_rca12_and_8_10 cin=s_dadda_rca12_nand_7_11 fa_xor1=s_dadda_rca12_fa78_xor1 fa_or0=s_dadda_rca12_fa78_or0
|
|
.subckt and_gate a=a[10] b=b[9] out=s_dadda_rca12_and_10_9
|
|
.subckt and_gate a=a[9] b=b[10] out=s_dadda_rca12_and_9_10
|
|
.subckt fa a=s_dadda_rca12_fa78_or0 b=s_dadda_rca12_and_10_9 cin=s_dadda_rca12_and_9_10 fa_xor1=s_dadda_rca12_fa79_xor1 fa_or0=s_dadda_rca12_fa79_or0
|
|
.subckt nand_gate a=a[11] b=b[9] out=s_dadda_rca12_nand_11_9
|
|
.subckt fa a=s_dadda_rca12_fa79_or0 b=s_dadda_rca12_fa63_or0 cin=s_dadda_rca12_nand_11_9 fa_xor1=s_dadda_rca12_fa80_xor1 fa_or0=s_dadda_rca12_fa80_or0
|
|
.subckt and_gate a=a[2] b=b[0] out=s_dadda_rca12_and_2_0
|
|
.subckt and_gate a=a[1] b=b[1] out=s_dadda_rca12_and_1_1
|
|
.subckt ha a=s_dadda_rca12_and_2_0 b=s_dadda_rca12_and_1_1 ha_xor0=s_dadda_rca12_ha9_xor0 ha_and0=s_dadda_rca12_ha9_and0
|
|
.subckt and_gate a=a[1] b=b[2] out=s_dadda_rca12_and_1_2
|
|
.subckt and_gate a=a[0] b=b[3] out=s_dadda_rca12_and_0_3
|
|
.subckt fa a=s_dadda_rca12_ha9_and0 b=s_dadda_rca12_and_1_2 cin=s_dadda_rca12_and_0_3 fa_xor1=s_dadda_rca12_fa81_xor1 fa_or0=s_dadda_rca12_fa81_or0
|
|
.subckt and_gate a=a[0] b=b[4] out=s_dadda_rca12_and_0_4
|
|
.subckt fa a=s_dadda_rca12_fa81_or0 b=s_dadda_rca12_and_0_4 cin=s_dadda_rca12_ha3_xor0 fa_xor1=s_dadda_rca12_fa82_xor1 fa_or0=s_dadda_rca12_fa82_or0
|
|
.subckt fa a=s_dadda_rca12_fa82_or0 b=s_dadda_rca12_fa9_xor1 cin=s_dadda_rca12_ha4_xor0 fa_xor1=s_dadda_rca12_fa83_xor1 fa_or0=s_dadda_rca12_fa83_or0
|
|
.subckt fa a=s_dadda_rca12_fa83_or0 b=s_dadda_rca12_fa11_xor1 cin=s_dadda_rca12_ha5_xor0 fa_xor1=s_dadda_rca12_fa84_xor1 fa_or0=s_dadda_rca12_fa84_or0
|
|
.subckt fa a=s_dadda_rca12_fa84_or0 b=s_dadda_rca12_fa14_xor1 cin=s_dadda_rca12_ha6_xor0 fa_xor1=s_dadda_rca12_fa85_xor1 fa_or0=s_dadda_rca12_fa85_or0
|
|
.subckt fa a=s_dadda_rca12_fa85_or0 b=s_dadda_rca12_fa18_xor1 cin=s_dadda_rca12_ha7_xor0 fa_xor1=s_dadda_rca12_fa86_xor1 fa_or0=s_dadda_rca12_fa86_or0
|
|
.subckt fa a=s_dadda_rca12_fa86_or0 b=s_dadda_rca12_fa22_xor1 cin=s_dadda_rca12_fa23_xor1 fa_xor1=s_dadda_rca12_fa87_xor1 fa_or0=s_dadda_rca12_fa87_or0
|
|
.subckt fa a=s_dadda_rca12_fa87_or0 b=s_dadda_rca12_fa27_xor1 cin=s_dadda_rca12_fa28_xor1 fa_xor1=s_dadda_rca12_fa88_xor1 fa_or0=s_dadda_rca12_fa88_or0
|
|
.subckt fa a=s_dadda_rca12_fa88_or0 b=s_dadda_rca12_fa32_xor1 cin=s_dadda_rca12_fa33_xor1 fa_xor1=s_dadda_rca12_fa89_xor1 fa_or0=s_dadda_rca12_fa89_or0
|
|
.subckt fa a=s_dadda_rca12_fa89_or0 b=s_dadda_rca12_fa37_xor1 cin=s_dadda_rca12_fa38_xor1 fa_xor1=s_dadda_rca12_fa90_xor1 fa_or0=s_dadda_rca12_fa90_or0
|
|
.subckt fa a=s_dadda_rca12_fa90_or0 b=s_dadda_rca12_fa42_xor1 cin=s_dadda_rca12_fa43_xor1 fa_xor1=s_dadda_rca12_fa91_xor1 fa_or0=s_dadda_rca12_fa91_or0
|
|
.subckt fa a=s_dadda_rca12_fa91_or0 b=s_dadda_rca12_fa47_xor1 cin=s_dadda_rca12_fa48_xor1 fa_xor1=s_dadda_rca12_fa92_xor1 fa_or0=s_dadda_rca12_fa92_or0
|
|
.subckt fa a=s_dadda_rca12_fa92_or0 b=s_dadda_rca12_fa52_xor1 cin=s_dadda_rca12_fa53_xor1 fa_xor1=s_dadda_rca12_fa93_xor1 fa_or0=s_dadda_rca12_fa93_or0
|
|
.subckt fa a=s_dadda_rca12_fa93_or0 b=s_dadda_rca12_fa56_xor1 cin=s_dadda_rca12_fa57_xor1 fa_xor1=s_dadda_rca12_fa94_xor1 fa_or0=s_dadda_rca12_fa94_or0
|
|
.subckt fa a=s_dadda_rca12_fa94_or0 b=s_dadda_rca12_fa59_xor1 cin=s_dadda_rca12_fa60_xor1 fa_xor1=s_dadda_rca12_fa95_xor1 fa_or0=s_dadda_rca12_fa95_or0
|
|
.subckt fa a=s_dadda_rca12_fa95_or0 b=s_dadda_rca12_fa61_xor1 cin=s_dadda_rca12_fa62_xor1 fa_xor1=s_dadda_rca12_fa96_xor1 fa_or0=s_dadda_rca12_fa96_or0
|
|
.subckt nand_gate a=a[8] b=b[11] out=s_dadda_rca12_nand_8_11
|
|
.subckt fa a=s_dadda_rca12_fa96_or0 b=s_dadda_rca12_nand_8_11 cin=s_dadda_rca12_fa63_xor1 fa_xor1=s_dadda_rca12_fa97_xor1 fa_or0=s_dadda_rca12_fa97_or0
|
|
.subckt and_gate a=a[10] b=b[10] out=s_dadda_rca12_and_10_10
|
|
.subckt nand_gate a=a[9] b=b[11] out=s_dadda_rca12_nand_9_11
|
|
.subckt fa a=s_dadda_rca12_fa97_or0 b=s_dadda_rca12_and_10_10 cin=s_dadda_rca12_nand_9_11 fa_xor1=s_dadda_rca12_fa98_xor1 fa_or0=s_dadda_rca12_fa98_or0
|
|
.subckt nand_gate a=a[11] b=b[10] out=s_dadda_rca12_nand_11_10
|
|
.subckt fa a=s_dadda_rca12_fa98_or0 b=s_dadda_rca12_fa80_or0 cin=s_dadda_rca12_nand_11_10 fa_xor1=s_dadda_rca12_fa99_xor1 fa_or0=s_dadda_rca12_fa99_or0
|
|
.subckt and_gate a=a[0] b=b[0] out=s_dadda_rca12_and_0_0
|
|
.subckt and_gate a=a[1] b=b[0] out=s_dadda_rca12_and_1_0
|
|
.subckt and_gate a=a[0] b=b[2] out=s_dadda_rca12_and_0_2
|
|
.subckt nand_gate a=a[10] b=b[11] out=s_dadda_rca12_nand_10_11
|
|
.subckt and_gate a=a[0] b=b[1] out=s_dadda_rca12_and_0_1
|
|
.subckt and_gate a=a[11] b=b[11] out=s_dadda_rca12_and_11_11
|
|
.names s_dadda_rca12_and_1_0 s_dadda_rca12_u_rca22_a[0]
|
|
1 1
|
|
.names s_dadda_rca12_and_0_2 s_dadda_rca12_u_rca22_a[1]
|
|
1 1
|
|
.names s_dadda_rca12_ha8_xor0 s_dadda_rca12_u_rca22_a[2]
|
|
1 1
|
|
.names s_dadda_rca12_fa64_xor1 s_dadda_rca12_u_rca22_a[3]
|
|
1 1
|
|
.names s_dadda_rca12_fa65_xor1 s_dadda_rca12_u_rca22_a[4]
|
|
1 1
|
|
.names s_dadda_rca12_fa66_xor1 s_dadda_rca12_u_rca22_a[5]
|
|
1 1
|
|
.names s_dadda_rca12_fa67_xor1 s_dadda_rca12_u_rca22_a[6]
|
|
1 1
|
|
.names s_dadda_rca12_fa68_xor1 s_dadda_rca12_u_rca22_a[7]
|
|
1 1
|
|
.names s_dadda_rca12_fa69_xor1 s_dadda_rca12_u_rca22_a[8]
|
|
1 1
|
|
.names s_dadda_rca12_fa70_xor1 s_dadda_rca12_u_rca22_a[9]
|
|
1 1
|
|
.names s_dadda_rca12_fa71_xor1 s_dadda_rca12_u_rca22_a[10]
|
|
1 1
|
|
.names s_dadda_rca12_fa72_xor1 s_dadda_rca12_u_rca22_a[11]
|
|
1 1
|
|
.names s_dadda_rca12_fa73_xor1 s_dadda_rca12_u_rca22_a[12]
|
|
1 1
|
|
.names s_dadda_rca12_fa74_xor1 s_dadda_rca12_u_rca22_a[13]
|
|
1 1
|
|
.names s_dadda_rca12_fa75_xor1 s_dadda_rca12_u_rca22_a[14]
|
|
1 1
|
|
.names s_dadda_rca12_fa76_xor1 s_dadda_rca12_u_rca22_a[15]
|
|
1 1
|
|
.names s_dadda_rca12_fa77_xor1 s_dadda_rca12_u_rca22_a[16]
|
|
1 1
|
|
.names s_dadda_rca12_fa78_xor1 s_dadda_rca12_u_rca22_a[17]
|
|
1 1
|
|
.names s_dadda_rca12_fa79_xor1 s_dadda_rca12_u_rca22_a[18]
|
|
1 1
|
|
.names s_dadda_rca12_fa80_xor1 s_dadda_rca12_u_rca22_a[19]
|
|
1 1
|
|
.names s_dadda_rca12_nand_10_11 s_dadda_rca12_u_rca22_a[20]
|
|
1 1
|
|
.names s_dadda_rca12_fa99_or0 s_dadda_rca12_u_rca22_a[21]
|
|
1 1
|
|
.names s_dadda_rca12_and_0_1 s_dadda_rca12_u_rca22_b[0]
|
|
1 1
|
|
.names s_dadda_rca12_ha9_xor0 s_dadda_rca12_u_rca22_b[1]
|
|
1 1
|
|
.names s_dadda_rca12_fa81_xor1 s_dadda_rca12_u_rca22_b[2]
|
|
1 1
|
|
.names s_dadda_rca12_fa82_xor1 s_dadda_rca12_u_rca22_b[3]
|
|
1 1
|
|
.names s_dadda_rca12_fa83_xor1 s_dadda_rca12_u_rca22_b[4]
|
|
1 1
|
|
.names s_dadda_rca12_fa84_xor1 s_dadda_rca12_u_rca22_b[5]
|
|
1 1
|
|
.names s_dadda_rca12_fa85_xor1 s_dadda_rca12_u_rca22_b[6]
|
|
1 1
|
|
.names s_dadda_rca12_fa86_xor1 s_dadda_rca12_u_rca22_b[7]
|
|
1 1
|
|
.names s_dadda_rca12_fa87_xor1 s_dadda_rca12_u_rca22_b[8]
|
|
1 1
|
|
.names s_dadda_rca12_fa88_xor1 s_dadda_rca12_u_rca22_b[9]
|
|
1 1
|
|
.names s_dadda_rca12_fa89_xor1 s_dadda_rca12_u_rca22_b[10]
|
|
1 1
|
|
.names s_dadda_rca12_fa90_xor1 s_dadda_rca12_u_rca22_b[11]
|
|
1 1
|
|
.names s_dadda_rca12_fa91_xor1 s_dadda_rca12_u_rca22_b[12]
|
|
1 1
|
|
.names s_dadda_rca12_fa92_xor1 s_dadda_rca12_u_rca22_b[13]
|
|
1 1
|
|
.names s_dadda_rca12_fa93_xor1 s_dadda_rca12_u_rca22_b[14]
|
|
1 1
|
|
.names s_dadda_rca12_fa94_xor1 s_dadda_rca12_u_rca22_b[15]
|
|
1 1
|
|
.names s_dadda_rca12_fa95_xor1 s_dadda_rca12_u_rca22_b[16]
|
|
1 1
|
|
.names s_dadda_rca12_fa96_xor1 s_dadda_rca12_u_rca22_b[17]
|
|
1 1
|
|
.names s_dadda_rca12_fa97_xor1 s_dadda_rca12_u_rca22_b[18]
|
|
1 1
|
|
.names s_dadda_rca12_fa98_xor1 s_dadda_rca12_u_rca22_b[19]
|
|
1 1
|
|
.names s_dadda_rca12_fa99_xor1 s_dadda_rca12_u_rca22_b[20]
|
|
1 1
|
|
.names s_dadda_rca12_and_11_11 s_dadda_rca12_u_rca22_b[21]
|
|
1 1
|
|
.subckt u_rca22 a[0]=s_dadda_rca12_u_rca22_a[0] a[1]=s_dadda_rca12_u_rca22_a[1] a[2]=s_dadda_rca12_u_rca22_a[2] a[3]=s_dadda_rca12_u_rca22_a[3] a[4]=s_dadda_rca12_u_rca22_a[4] a[5]=s_dadda_rca12_u_rca22_a[5] a[6]=s_dadda_rca12_u_rca22_a[6] a[7]=s_dadda_rca12_u_rca22_a[7] a[8]=s_dadda_rca12_u_rca22_a[8] a[9]=s_dadda_rca12_u_rca22_a[9] a[10]=s_dadda_rca12_u_rca22_a[10] a[11]=s_dadda_rca12_u_rca22_a[11] a[12]=s_dadda_rca12_u_rca22_a[12] a[13]=s_dadda_rca12_u_rca22_a[13] a[14]=s_dadda_rca12_u_rca22_a[14] a[15]=s_dadda_rca12_u_rca22_a[15] a[16]=s_dadda_rca12_u_rca22_a[16] a[17]=s_dadda_rca12_u_rca22_a[17] a[18]=s_dadda_rca12_u_rca22_a[18] a[19]=s_dadda_rca12_u_rca22_a[19] a[20]=s_dadda_rca12_u_rca22_a[20] a[21]=s_dadda_rca12_u_rca22_a[21] b[0]=s_dadda_rca12_u_rca22_b[0] b[1]=s_dadda_rca12_u_rca22_b[1] b[2]=s_dadda_rca12_u_rca22_b[2] b[3]=s_dadda_rca12_u_rca22_b[3] b[4]=s_dadda_rca12_u_rca22_b[4] b[5]=s_dadda_rca12_u_rca22_b[5] b[6]=s_dadda_rca12_u_rca22_b[6] b[7]=s_dadda_rca12_u_rca22_b[7] b[8]=s_dadda_rca12_u_rca22_b[8] b[9]=s_dadda_rca12_u_rca22_b[9] b[10]=s_dadda_rca12_u_rca22_b[10] b[11]=s_dadda_rca12_u_rca22_b[11] b[12]=s_dadda_rca12_u_rca22_b[12] b[13]=s_dadda_rca12_u_rca22_b[13] b[14]=s_dadda_rca12_u_rca22_b[14] b[15]=s_dadda_rca12_u_rca22_b[15] b[16]=s_dadda_rca12_u_rca22_b[16] b[17]=s_dadda_rca12_u_rca22_b[17] b[18]=s_dadda_rca12_u_rca22_b[18] b[19]=s_dadda_rca12_u_rca22_b[19] b[20]=s_dadda_rca12_u_rca22_b[20] b[21]=s_dadda_rca12_u_rca22_b[21] u_rca22_out[0]=s_dadda_rca12_u_rca22_ha_xor0 u_rca22_out[1]=s_dadda_rca12_u_rca22_fa1_xor1 u_rca22_out[2]=s_dadda_rca12_u_rca22_fa2_xor1 u_rca22_out[3]=s_dadda_rca12_u_rca22_fa3_xor1 u_rca22_out[4]=s_dadda_rca12_u_rca22_fa4_xor1 u_rca22_out[5]=s_dadda_rca12_u_rca22_fa5_xor1 u_rca22_out[6]=s_dadda_rca12_u_rca22_fa6_xor1 u_rca22_out[7]=s_dadda_rca12_u_rca22_fa7_xor1 u_rca22_out[8]=s_dadda_rca12_u_rca22_fa8_xor1 u_rca22_out[9]=s_dadda_rca12_u_rca22_fa9_xor1 u_rca22_out[10]=s_dadda_rca12_u_rca22_fa10_xor1 u_rca22_out[11]=s_dadda_rca12_u_rca22_fa11_xor1 u_rca22_out[12]=s_dadda_rca12_u_rca22_fa12_xor1 u_rca22_out[13]=s_dadda_rca12_u_rca22_fa13_xor1 u_rca22_out[14]=s_dadda_rca12_u_rca22_fa14_xor1 u_rca22_out[15]=s_dadda_rca12_u_rca22_fa15_xor1 u_rca22_out[16]=s_dadda_rca12_u_rca22_fa16_xor1 u_rca22_out[17]=s_dadda_rca12_u_rca22_fa17_xor1 u_rca22_out[18]=s_dadda_rca12_u_rca22_fa18_xor1 u_rca22_out[19]=s_dadda_rca12_u_rca22_fa19_xor1 u_rca22_out[20]=s_dadda_rca12_u_rca22_fa20_xor1 u_rca22_out[21]=s_dadda_rca12_u_rca22_fa21_xor1 u_rca22_out[22]=s_dadda_rca12_u_rca22_fa21_or0
|
|
.subckt not_gate a=s_dadda_rca12_u_rca22_fa21_or0 out=s_dadda_rca12_xor0
|
|
.names s_dadda_rca12_and_0_0 s_dadda_rca12_out[0]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_ha_xor0 s_dadda_rca12_out[1]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa1_xor1 s_dadda_rca12_out[2]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa2_xor1 s_dadda_rca12_out[3]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa3_xor1 s_dadda_rca12_out[4]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa4_xor1 s_dadda_rca12_out[5]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa5_xor1 s_dadda_rca12_out[6]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa6_xor1 s_dadda_rca12_out[7]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa7_xor1 s_dadda_rca12_out[8]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa8_xor1 s_dadda_rca12_out[9]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa9_xor1 s_dadda_rca12_out[10]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa10_xor1 s_dadda_rca12_out[11]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa11_xor1 s_dadda_rca12_out[12]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa12_xor1 s_dadda_rca12_out[13]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa13_xor1 s_dadda_rca12_out[14]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa14_xor1 s_dadda_rca12_out[15]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa15_xor1 s_dadda_rca12_out[16]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa16_xor1 s_dadda_rca12_out[17]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa17_xor1 s_dadda_rca12_out[18]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa18_xor1 s_dadda_rca12_out[19]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa19_xor1 s_dadda_rca12_out[20]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa20_xor1 s_dadda_rca12_out[21]
|
|
1 1
|
|
.names s_dadda_rca12_u_rca22_fa21_xor1 s_dadda_rca12_out[22]
|
|
1 1
|
|
.names s_dadda_rca12_xor0 s_dadda_rca12_out[23]
|
|
1 1
|
|
.end
|
|
|
|
.model u_rca22
|
|
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21]
|
|
.outputs u_rca22_out[0] u_rca22_out[1] u_rca22_out[2] u_rca22_out[3] u_rca22_out[4] u_rca22_out[5] u_rca22_out[6] u_rca22_out[7] u_rca22_out[8] u_rca22_out[9] u_rca22_out[10] u_rca22_out[11] u_rca22_out[12] u_rca22_out[13] u_rca22_out[14] u_rca22_out[15] u_rca22_out[16] u_rca22_out[17] u_rca22_out[18] u_rca22_out[19] u_rca22_out[20] u_rca22_out[21] u_rca22_out[22]
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt ha a=a[0] b=b[0] ha_xor0=u_rca22_ha_xor0 ha_and0=u_rca22_ha_and0
|
|
.subckt fa a=a[1] b=b[1] cin=u_rca22_ha_and0 fa_xor1=u_rca22_fa1_xor1 fa_or0=u_rca22_fa1_or0
|
|
.subckt fa a=a[2] b=b[2] cin=u_rca22_fa1_or0 fa_xor1=u_rca22_fa2_xor1 fa_or0=u_rca22_fa2_or0
|
|
.subckt fa a=a[3] b=b[3] cin=u_rca22_fa2_or0 fa_xor1=u_rca22_fa3_xor1 fa_or0=u_rca22_fa3_or0
|
|
.subckt fa a=a[4] b=b[4] cin=u_rca22_fa3_or0 fa_xor1=u_rca22_fa4_xor1 fa_or0=u_rca22_fa4_or0
|
|
.subckt fa a=a[5] b=b[5] cin=u_rca22_fa4_or0 fa_xor1=u_rca22_fa5_xor1 fa_or0=u_rca22_fa5_or0
|
|
.subckt fa a=a[6] b=b[6] cin=u_rca22_fa5_or0 fa_xor1=u_rca22_fa6_xor1 fa_or0=u_rca22_fa6_or0
|
|
.subckt fa a=a[7] b=b[7] cin=u_rca22_fa6_or0 fa_xor1=u_rca22_fa7_xor1 fa_or0=u_rca22_fa7_or0
|
|
.subckt fa a=a[8] b=b[8] cin=u_rca22_fa7_or0 fa_xor1=u_rca22_fa8_xor1 fa_or0=u_rca22_fa8_or0
|
|
.subckt fa a=a[9] b=b[9] cin=u_rca22_fa8_or0 fa_xor1=u_rca22_fa9_xor1 fa_or0=u_rca22_fa9_or0
|
|
.subckt fa a=a[10] b=b[10] cin=u_rca22_fa9_or0 fa_xor1=u_rca22_fa10_xor1 fa_or0=u_rca22_fa10_or0
|
|
.subckt fa a=a[11] b=b[11] cin=u_rca22_fa10_or0 fa_xor1=u_rca22_fa11_xor1 fa_or0=u_rca22_fa11_or0
|
|
.subckt fa a=a[12] b=b[12] cin=u_rca22_fa11_or0 fa_xor1=u_rca22_fa12_xor1 fa_or0=u_rca22_fa12_or0
|
|
.subckt fa a=a[13] b=b[13] cin=u_rca22_fa12_or0 fa_xor1=u_rca22_fa13_xor1 fa_or0=u_rca22_fa13_or0
|
|
.subckt fa a=a[14] b=b[14] cin=u_rca22_fa13_or0 fa_xor1=u_rca22_fa14_xor1 fa_or0=u_rca22_fa14_or0
|
|
.subckt fa a=a[15] b=b[15] cin=u_rca22_fa14_or0 fa_xor1=u_rca22_fa15_xor1 fa_or0=u_rca22_fa15_or0
|
|
.subckt fa a=a[16] b=b[16] cin=u_rca22_fa15_or0 fa_xor1=u_rca22_fa16_xor1 fa_or0=u_rca22_fa16_or0
|
|
.subckt fa a=a[17] b=b[17] cin=u_rca22_fa16_or0 fa_xor1=u_rca22_fa17_xor1 fa_or0=u_rca22_fa17_or0
|
|
.subckt fa a=a[18] b=b[18] cin=u_rca22_fa17_or0 fa_xor1=u_rca22_fa18_xor1 fa_or0=u_rca22_fa18_or0
|
|
.subckt fa a=a[19] b=b[19] cin=u_rca22_fa18_or0 fa_xor1=u_rca22_fa19_xor1 fa_or0=u_rca22_fa19_or0
|
|
.subckt fa a=a[20] b=b[20] cin=u_rca22_fa19_or0 fa_xor1=u_rca22_fa20_xor1 fa_or0=u_rca22_fa20_or0
|
|
.subckt fa a=a[21] b=b[21] cin=u_rca22_fa20_or0 fa_xor1=u_rca22_fa21_xor1 fa_or0=u_rca22_fa21_or0
|
|
.names u_rca22_ha_xor0 u_rca22_out[0]
|
|
1 1
|
|
.names u_rca22_fa1_xor1 u_rca22_out[1]
|
|
1 1
|
|
.names u_rca22_fa2_xor1 u_rca22_out[2]
|
|
1 1
|
|
.names u_rca22_fa3_xor1 u_rca22_out[3]
|
|
1 1
|
|
.names u_rca22_fa4_xor1 u_rca22_out[4]
|
|
1 1
|
|
.names u_rca22_fa5_xor1 u_rca22_out[5]
|
|
1 1
|
|
.names u_rca22_fa6_xor1 u_rca22_out[6]
|
|
1 1
|
|
.names u_rca22_fa7_xor1 u_rca22_out[7]
|
|
1 1
|
|
.names u_rca22_fa8_xor1 u_rca22_out[8]
|
|
1 1
|
|
.names u_rca22_fa9_xor1 u_rca22_out[9]
|
|
1 1
|
|
.names u_rca22_fa10_xor1 u_rca22_out[10]
|
|
1 1
|
|
.names u_rca22_fa11_xor1 u_rca22_out[11]
|
|
1 1
|
|
.names u_rca22_fa12_xor1 u_rca22_out[12]
|
|
1 1
|
|
.names u_rca22_fa13_xor1 u_rca22_out[13]
|
|
1 1
|
|
.names u_rca22_fa14_xor1 u_rca22_out[14]
|
|
1 1
|
|
.names u_rca22_fa15_xor1 u_rca22_out[15]
|
|
1 1
|
|
.names u_rca22_fa16_xor1 u_rca22_out[16]
|
|
1 1
|
|
.names u_rca22_fa17_xor1 u_rca22_out[17]
|
|
1 1
|
|
.names u_rca22_fa18_xor1 u_rca22_out[18]
|
|
1 1
|
|
.names u_rca22_fa19_xor1 u_rca22_out[19]
|
|
1 1
|
|
.names u_rca22_fa20_xor1 u_rca22_out[20]
|
|
1 1
|
|
.names u_rca22_fa21_xor1 u_rca22_out[21]
|
|
1 1
|
|
.names u_rca22_fa21_or0 u_rca22_out[22]
|
|
1 1
|
|
.end
|
|
|
|
.model fa
|
|
.inputs a b cin
|
|
.outputs fa_xor1 fa_or0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=fa_xor0
|
|
.subckt and_gate a=a b=b out=fa_and0
|
|
.subckt xor_gate a=fa_xor0 b=cin out=fa_xor1
|
|
.subckt and_gate a=fa_xor0 b=cin out=fa_and1
|
|
.subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0
|
|
.end
|
|
|
|
.model ha
|
|
.inputs a b
|
|
.outputs ha_xor0 ha_and0
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.subckt xor_gate a=a b=b out=ha_xor0
|
|
.subckt and_gate a=a b=b out=ha_and0
|
|
.end
|
|
|
|
.model not_gate
|
|
.inputs a
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a out
|
|
0 1
|
|
.end
|
|
|
|
.model nand_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
0- 1
|
|
-0 1
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
1- 1
|
|
-1 1
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
01 1
|
|
10 1
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs a b
|
|
.outputs out
|
|
.names vdd
|
|
1
|
|
.names gnd
|
|
0
|
|
.names a b out
|
|
11 1
|
|
.end
|