dissertation_thesis/ariths-gen-mig
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honzastor 2021-03-22 00:31:59 +01:00
parent 792d0c5db1
commit 8df8e72810
1 changed files with 0 additions and 1 deletions
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arithmetic_circuits_generator.py
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@ -29,7 +29,6 @@ if __name__ == "__main__":
#arrmul.get_v_code_flat(open("arrmul_test.v", "w")) #arrmul.get_v_code_flat(open("arrmul_test.v", "w"))
#arrmul.get_blif_code_flat(open("arrmul_test.blif", "w")) #arrmul.get_blif_code_flat(open("arrmul_test.blif", "w"))
w1 = wire(name="a") w1 = wire(name="a")
w2 = wire(name="b") w2 = wire(name="b")
w3 = wire(name="cin") w3 = wire(name="cin")