dissertation_thesis/ariths-gen-mig
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Imprt missing full adder
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This commit is contained in:
Lukáš Plevač 2025-01-15 19:23:47 +01:00
parent d0501238f8
commit 395750eac5
1 changed files with 302 additions and 302 deletions
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ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
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@ -1,4 +1,4 @@
from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit
from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit, FullAdder
from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
from ariths_gen.one_bit_circuits import Maji
from ariths_gen.wire_components import Wire, Bus