Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.
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@ -66,7 +66,7 @@ class FullAdder(ThreeInputOneBitCircuit):
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"wireys": self.get_sum_wire().prefix,
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"wireys": self.get_sum_wire().prefix,
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"wireyc": self.get_carry_wire().prefix,
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"wireyc": self.get_carry_wire().prefix,
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}
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}
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) + "\n"
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) + ";\n"
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def get_self_init_v_hier(self):
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def get_self_init_v_hier(self):
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@ -85,7 +85,7 @@ class FullAdder(ThreeInputOneBitCircuit):
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"wirec": self.c.name,
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"wirec": self.c.name,
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"wireys": unique_out_wires[0],
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"wireys": unique_out_wires[0],
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"wireyc": unique_out_wires[1],
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"wireyc": unique_out_wires[1],
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}) + "\n"
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}) + ";\n"
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class FullAdderPG(ThreeInputOneBitCircuit):
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class FullAdderPG(ThreeInputOneBitCircuit):
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"""Class representing modified three input one bit full adder with propagate/generate logic.
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"""Class representing modified three input one bit full adder with propagate/generate logic.
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@ -50,10 +50,10 @@ class HalfAdder(TwoInputOneBitCircuit):
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"unit": self.prefix,
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"unit": self.prefix,
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"wirea": self.a.prefix,
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"wirea": self.a.prefix,
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"wireb": self.b.prefix,
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"wireb": self.b.prefix,
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"wires": self.get_sum_wire().prefix,
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"wireys": self.get_sum_wire().prefix,
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"wirec": self.get_carry_wire().prefix,
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"wireyc": self.get_carry_wire().prefix,
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}
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}
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) + "\n"
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) + ";\n"
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def get_self_init_v_hier(self):
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def get_self_init_v_hier(self):
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@ -71,7 +71,7 @@ class HalfAdder(TwoInputOneBitCircuit):
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"wireb": self.b.name,
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"wireb": self.b.name,
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"wireys": unique_out_wires[0],
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"wireys": unique_out_wires[0],
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"wireyc": unique_out_wires[1],
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"wireyc": unique_out_wires[1],
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}) + "\n"
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}) + ";\n"
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class PGLogicBlock(TwoInputOneBitCircuit):
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class PGLogicBlock(TwoInputOneBitCircuit):
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"""Class representing two input one bit propagate/generate logic block.
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"""Class representing two input one bit propagate/generate logic block.
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62
generate_axmuls.py
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62
generate_axmuls.py
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@ -0,0 +1,62 @@
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.multi_bit_circuits.approximate_multipliers import (
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UnsignedTruncatedMultiplier,
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UnsignedBrokenArrayMultiplier
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)
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from ariths_gen.pdk import *
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import os
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if __name__ == "__main__":
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# Use HA and FA technology from pdk45 library
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set_pdk45_library()
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# 8-bit unsigned BAMs
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paths = ["BrokenArrayMultiplier/C/flat", "BrokenArrayMultiplier/C/hier", "BrokenArrayMultiplier/Verilog/flat", "BrokenArrayMultiplier/Verilog/hier"]
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for path in paths:
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if not os.path.exists(path):
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os.makedirs(path)
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i = 0
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for h in range(0, 8):
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# v <= (8-1) + (8-2)
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for v in range(h, 13):
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i += 1
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N=8
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a = Bus(prefix="a", N=N)
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b = Bus(prefix="b", N=N)
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u_bam = UnsignedBrokenArrayMultiplier(a, b, name=f"f_u_bam{N}_h{h}_v{v}", horizontal_cut=h, vertical_cut=v)
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u_bam.get_c_code_flat(file_object=open(f"BrokenArrayMultiplier/C/flat/f_u_bam{N}_h{h}_v{v}.c", "w"))
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u_bam.get_v_code_flat(file_object=open(f"BrokenArrayMultiplier/Verilog/flat/f_u_bam{N}_h{h}_v{v}.v", "w"))
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u_bam = UnsignedBrokenArrayMultiplier(a, b, name=f"h_u_bam{N}_h{h}_v{v}", horizontal_cut=h, vertical_cut=v)
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u_bam.get_c_code_hier(file_object=open(f"BrokenArrayMultiplier/C/hier/h_u_bam{N}_h{h}_v{v}.c", "w"))
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u_bam.get_v_code_hier(file_object=open(f"BrokenArrayMultiplier/Verilog/hier/h_u_bam{N}_h{h}_v{v}.v", "w"))
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# 8-bit unsigned TMs
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paths = ["TruncatedMultiplier/C/flat", "TruncatedMultiplier/C/hier", "TruncatedMultiplier/Verilog/flat", "TruncatedMultiplier/Verilog/hier"]
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for path in paths:
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if not os.path.exists(path):
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os.makedirs(path)
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for i in range(0, 8):
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N=8
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a = Bus(prefix="a", N=N)
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b = Bus(prefix="b", N=N)
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u_tm = UnsignedTruncatedMultiplier(a, b, name=f"f_u_tm{N}_k{i}", truncation_cut=i)
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u_tm.get_c_code_flat(file_object=open(f"TruncatedMultiplier/C/flat/f_u_tm{N}_k{i}.c", "w"))
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u_tm.get_v_code_flat(file_object=open(f"TruncatedMultiplier/Verilog/flat/f_u_tm{N}_k{i}.v", "w"))
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u_tm = UnsignedTruncatedMultiplier(a, b, name=f"h_u_tm{N}_k{i}", truncation_cut=i)
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u_tm.get_c_code_hier(file_object=open(f"TruncatedMultiplier/C/hier/h_u_tm{N}_k{i}.c", "w"))
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u_tm.get_v_code_hier(file_object=open(f"TruncatedMultiplier/Verilog/hier/h_u_tm{N}_k{i}.v", "w"))
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