From 3c6db0bbb59d2ec77ebf53c75dfe7c1711814b76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Luk=C3=A1=C5=A1=20Pleva=C4=8D?= Date: Sun, 28 Jan 2024 11:50:51 +0100 Subject: [PATCH] Added pseudo parallel --- SDC-Sim | 1 + codes/caUnaryAdd.asm | 34 ++++++++++++++++++++++ codes/sep.asm | 63 +++++++++++++++++++++++++++++++++++++++++ src/SIMDDNA/register.py | 5 ++++ 4 files changed, 103 insertions(+) create mode 120000 SDC-Sim create mode 100644 codes/caUnaryAdd.asm create mode 100644 codes/sep.asm diff --git a/SDC-Sim b/SDC-Sim new file mode 120000 index 0000000..a8c92b0 --- /dev/null +++ b/SDC-Sim @@ -0,0 +1 @@ +src/main.py \ No newline at end of file diff --git a/codes/caUnaryAdd.asm b/codes/caUnaryAdd.asm new file mode 100644 index 0000000..c1bf3b6 --- /dev/null +++ b/codes/caUnaryAdd.asm @@ -0,0 +1,34 @@ +# +# Shift left register in DNA|SIMD +# @autor Lukáš Plevač +# @date 12.06.2023 +# + +define: + 0 [AB][CD][EF] + 1 [ABC][DEF] + 2 {A}[BCDE]{F} + +data: + 00022120 + +instructions: + {F*A*G*} # mark 02 and 22 + {F*A*B*G*} # mark 20 nothing to do here and open binding for 21 + {F*A*B*C*G*} # mark 21 + {B*C*D*E*} # replace old zero with 2 + {FAG} + {A*B*C*D*G*} # unvrap 2 when 02 + {ABCDG} + + {A*B*C*} {D*E*F*} # set 1 + + + + #{DEF} + + #{FABG} # unmark 20 + + #{B*C*D*E*} # write 2 + + #{FABCG} \ No newline at end of file diff --git a/codes/sep.asm b/codes/sep.asm new file mode 100644 index 0000000..eb83cab --- /dev/null +++ b/codes/sep.asm @@ -0,0 +1,63 @@ +# +# Shift left register in DNA|SIMD +# @autor Lukáš Plevač +# @date 11.28.2023 +# + +define: + # BIT NOT selector + 0 [ABC][DE]{NSL} + 1 [ABCD]{ENSL} + +data: + # Implicit zero + 00110[ABC][DE][NSL] + 10101[ABC][DE][NSL] + +instructions: # O(33) + {E*N*S*L*A*} # unvrap DE from zero and bind here on tother site onvrap first base + {D*E*N*S*L*G*} # replace unvraper if on left site is 0 + {ENSLA} # remove all existing unvrapers free when left 1 + {E*N*S*L*A*B*} # unvrap 0 when is on right is 0 on free space and fully binde here if is 1 right + {ENSLAB} # unvrap unwraper if is 1 on right + {E*N*S*L*I*} # bind not selector for 11 on free space (only free when 1 right and 1 left) (prevent E binding to) + {N*S*L*A*B*C*F*} # REMOVE {E*N*S*L*A*B*} + {DENSLG} # REMOVE {D*E*N*S*L*G*} + {NSLABCF} # REMOVE {N*S*L*A*B*C*F*} + {A*B*C*} # write zero fisrt part back + + {E*N*S*L*J*} # try fit in free space between cells (when 1 on right thare is no free base when 0 there is one free base) + {D*E*N*S*L*G*} # replace {E*N*S*L*J*} when 0 on rigth + {DENSLG} # REMOVE {D*E*N*S*L*G*} (now free only when have 0 on rigth) + {D*E*N*S*L*A*B*} # unvrap 0 when is on left is 0 on free space and fully binde here if is 0 right + {DENSLAB} # unvrap {D*E*N*S*L*A*B*} when 1 on rigth + + {E*N*S*L*Y*} # pad NOT selector to prevent bind not selector here (01) + {B*C*D*G*} {DENSLAB} # unvrap {D*E*N*S*L*A*B*} using {B*C*D*G*} and remove + + {ENSLI} # remove temp not selector for 11 + {N*S*L*U*} # bind not selector for 00 + + {ENSLY} {ENSLJ} # remove PAD {E*N*S*L*Y*} and PAD {E*N*S*L*J*} + + # here is problem with 000 + # {BCDG} remove unvraper {B*C*D*G*} not needed becasuse is replaced by 0 + + {A*B*C*} {D*E*} # write 0 + + # selected not subprogram + + {G*D*E*N*} # mark NOT 0 and NOT 1 + {ABCD} # remove unwraped 1 + {GDEN} # remove mark + {C*D*E*N*} # mark write 0 + {CDEN} # remowe mark write 0 (is only posible when is unvraped for second part of zero) + {A*B*C*D*} # write 1 + {ABCD} # remove not writed 1 (is unwraped by mark write 0) + {N*S*L*G*} # unwrap write 0 mark + {CDEN} # remove write 0 mark + {NSLG} # remove unwraper + {A*B*C*} {D*E*} # write 0 + {NSLU} # remove all not selectors + + diff --git a/src/SIMDDNA/register.py b/src/SIMDDNA/register.py index ae62865..9df198f 100644 --- a/src/SIMDDNA/register.py +++ b/src/SIMDDNA/register.py @@ -6,6 +6,8 @@ from . import molecule from . import ascii +from joblib import Parallel, delayed + class Register: ## # Init register @@ -27,6 +29,9 @@ class Register: # def instruction(self, IMols): # @todo: while chainging + Parallel(n_jobs=4)(delayed(self.insDo)(IMols) for _ in range(4)) + + def insDo(self, IMols): for _ in range(20): for mol in IMols: # try bind mol to all possible bindings