commit c6a162fe595b7af842507607bc3a3105a8db2cca Author: Lukáš Plevač Date: Sun Dec 3 19:31:49 2023 +0100 first commit diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..f7e41b0 --- /dev/null +++ b/Makefile @@ -0,0 +1,7 @@ +build: + cd synth && \ + /tools/Xilinx/Vivado/2023.2/bin/vivado -mode batch -source filter.tcl + +test: + cd ver && \ + vsim -c -do filter.tcl diff --git a/comp/block_memory.vhd b/comp/block_memory.vhd new file mode 100644 index 0000000..4615264 --- /dev/null +++ b/comp/block_memory.vhd @@ -0,0 +1,99 @@ +-- block_memory.vhd: General storage memory build from BlockRAMs or M20Ks with one read and one write port +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_unsigned.all; +use work.functions_package.clog2; + + + +entity block_memory is + generic( + -- Size of the memory. + -- ITEMS individual records addressed from 0 to ITEMS-1, each ITEM_WIDTH bits wide. + ITEM_WIDTH : natural := 32; + ITEMS : natural := 1024; + -- Enables output data register on read port for better frequency. + -- Latency of reading data from the memory is 1 clock cycle when false, and 2 clock cycles when true. + OUTPUT_REGISTER : boolean := true + ); + port ( + -- Main clock signal and its synchronous reset. + CLK : in std_logic; + RESET : in std_logic; + -- Read interface ---------------------------------------------------------- + READ_ADDRESS : in std_logic_vector(clog2(ITEMS)-1 downto 0); -- item address to read + READ_VALID : in std_logic; -- read is valid + READ_DATA : out std_logic_vector(ITEM_WIDTH-1 downto 0); -- read data (note: read latency!) + READ_DATA_VALID : out std_logic; -- delayed read valid flag + -- Write interface --------------------------------------------------------- + WRITE_DATA : in std_logic_vector(ITEM_WIDTH-1 downto 0); -- data to write + WRITE_ADDRESS : in std_logic_vector(clog2(ITEMS)-1 downto 0); -- item address to write + WRITE_VALID : in std_logic -- perform write operation + ); +end entity; + + + +architecture behavioral of block_memory is + + type memory_type is array(0 to ITEMS-1) of std_logic_vector(ITEM_WIDTH-1 downto 0); + signal memory : memory_type; + signal memory_data : std_logic_vector(ITEM_WIDTH-1 downto 0); + signal memory_data_valid : std_logic; + +begin + + -- Unsupported configurations checks ----------------------------------------- + assert ITEMS > 1 report "FAILURE: Block Memory must have at least two items!" severity failure; + assert ITEM_WIDTH > 0 report "FAILURE: Block Memory item must be at least 1 bit wide!" severity failure; + + -- Runtime error checks ------------------------------------------------------ + assert conv_integer(READ_ADDRESS) < ITEMS or RESET/= '0' report "ERROR: Block Memory read out of bounds!" severity error; + assert conv_integer(WRITE_ADDRESS) < ITEMS or RESET/= '0' report "ERROR: Block Memory write out of bounds!" severity error; + + -- Memory core implementation ------------------------------------------------ + storage_core: process(CLK) + begin + if rising_edge(CLK) then + -- Write port + if WRITE_VALID = '1' then + memory(conv_integer(WRITE_ADDRESS)) <= WRITE_DATA; + end if; + -- Read port + memory_data <= memory(conv_integer(READ_ADDRESS)); + if RESET = '1' then + memory_data_valid <= '0'; + else + memory_data_valid <= READ_VALID; + end if; + end if; + end process; + + -- Optional output register on read port ------------------------------------- + registered_read: if OUTPUT_REGISTER generate + read_register: process(CLK) + begin + if rising_edge(CLK) then + READ_DATA <= memory_data; + if RESET = '1' then + READ_DATA_VALID <= '0'; + else + READ_DATA_VALID <= memory_data_valid; + end if; + end if; + end process; + end generate; + direct_read: if not OUTPUT_REGISTER generate + READ_DATA <= memory_data; + READ_DATA_VALID <= memory_data_valid; + end generate; + +end architecture; \ No newline at end of file diff --git a/comp/functions.vhd b/comp/functions.vhd new file mode 100644 index 0000000..aecc3d1 --- /dev/null +++ b/comp/functions.vhd @@ -0,0 +1,46 @@ +-- functions.vhd: Useful functions not present in the vanilla VHDL libraries +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + + +package functions_package is + + -- Ceil 2-logarithm of a given number N, i.e. returns smallest value X for which 2^X >= N holds. + function clog2(n : natural) return natural; + + -- Ceil division of a given number N by K, i.e. returns smallest value X for which X*K >= N holds. + function cdiv(n : natural; k : natural) return natural; + +end functions_package; + + + +package body functions_package is + + function clog2(n : natural) return natural is + variable x, m : natural; + begin + x := 0; + m := 1; + while m < n loop + x := x + 1; + m := m * 2; + end loop; + return x; + end function; + + function cdiv(n : natural; k : natural) return natural is + begin + return (n-1) / k + 1; + end function; + +end functions_package; \ No newline at end of file diff --git a/comp/jenkins_final.vhd b/comp/jenkins_final.vhd new file mode 100644 index 0000000..bf5ff3f --- /dev/null +++ b/comp/jenkins_final.vhd @@ -0,0 +1,128 @@ +-- jenkins_final.vhd: Part of Jenkins hashing function based on https://burtleburtle.net/bob/c/lookup3.c +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_unsigned.all; + + + +entity jenkins_final is + generic( + -- Width of hashed key in 32-bit words. + LENGTH : natural := 1 + ); + port ( + -- Main clock signal and its synchronous reset. + CLK : in std_logic; + RESET : in std_logic; + -- Input interface --------------------------------------------------------- + INPUT_A : in std_logic_vector(32-1 downto 0); + INPUT_B : in std_logic_vector(32-1 downto 0); + INPUT_C : in std_logic_vector(32-1 downto 0); + INPUT_KEY : in std_logic_vector(LENGTH*32-1 downto 0); + INPUT_VALID : in std_logic; + -- Output interface -------------------------------------------------------- + OUTPUT_A : out std_logic_vector(32-1 downto 0); + OUTPUT_B : out std_logic_vector(32-1 downto 0); + OUTPUT_C : out std_logic_vector(32-1 downto 0); + OUTPUT_KEY : out std_logic_vector(LENGTH*32-1 downto 0); + OUTPUT_VALID : out std_logic + ); +end entity; + + + +architecture behavioral of jenkins_final is + + constant STAGES : integer := 7; + + function rot(x : std_logic_vector(32-1 downto 0); k : natural) return std_logic_vector is + begin + return x(32-k-1 downto 0) & x(32-1 downto 32-k); + end function; + + type computation_stage is record + a : std_logic_vector(32-1 downto 0); + b : std_logic_vector(32-1 downto 0); + c : std_logic_vector(32-1 downto 0); + key : std_logic_vector(LENGTH*32-1 downto 0); + valid : std_logic; + end record; + type computation_stage_array is array(natural range <>) of computation_stage; + + signal s : computation_stage_array(0 to STAGES); + +begin + + -- Input connections + s(0).a <= INPUT_A; + s(0).b <= INPUT_B; + s(0).c <= INPUT_C; + s(0).key <= INPUT_KEY; + s(0).valid <= INPUT_VALID; + + -- Stage 1: c ^= b; c -= rot(b,14); + s(1).a <= s(0).a; + s(1).b <= s(0).b; + s(1).c <= (s(0).c xor s(0).b) - rot(s(0).b, 14); + s(1).key <= s(0).key; + s(1).valid <= s(0).valid; + + -- Stage 2: a ^= c; a -= rot(c,11); + s(2).a <= (s(1).a xor s(1).c) - rot(s(1).c, 11); + s(2).b <= s(1).b; + s(2).c <= s(1).c; + s(2).key <= s(1).key; + s(2).valid <= s(1).valid; + + + -- Stage 3: b ^= a; b -= rot(a,25); + s(3).a <= s(2).a; + s(3).b <= (s(2).b xor s(2).a) - rot(s(2).a, 25); + s(3).c <= s(2).c; + s(3).key <= s(2).key; + s(3).valid <= s(2).valid; + + -- Stage 4: c ^= b; c -= rot(b,16); + s(4).a <= s(3).a; + s(4).b <= s(3).b; + s(4).c <= (s(3).c xor s(3).b) - rot(s(3).b, 16); + s(4).key <= s(3).key; + s(4).valid <= s(3).valid; + + -- Stage 5: a ^= c; a -= rot(c,4); + s(5).a <= (s(4).a xor s(4).c) - rot(s(4).c, 4); + s(5).b <= s(4).b; + s(5).c <= s(4).c; + s(5).key <= s(4).key; + s(5).valid <= s(4).valid; + + -- Stage 6: b ^= a; b -= rot(a,14); + s(6).a <= s(5).a; + s(6).b <= (s(5).b xor s(5).a) - rot(s(5).a, 14); + s(6).c <= s(5).c; + s(6).key <= s(5).key; + s(6).valid <= s(5).valid; + + -- Stage 7: c ^= b; c -= rot(b,24); + s(7).a <= s(6).a; + s(7).b <= s(6).b; + s(7).c <= (s(6).c xor s(6).b) - rot(s(6).b, 24); + s(7).key <= s(6).key; + s(7).valid <= s(6).valid; + + -- Output connections + OUTPUT_A <= s(STAGES).a; + OUTPUT_B <= s(STAGES).b; + OUTPUT_C <= s(STAGES).c; + OUTPUT_KEY <= s(STAGES).key; + OUTPUT_VALID <= s(STAGES).valid; + +end architecture; \ No newline at end of file diff --git a/comp/jenkins_hash.vhd b/comp/jenkins_hash.vhd new file mode 100644 index 0000000..ba3d3c8 --- /dev/null +++ b/comp/jenkins_hash.vhd @@ -0,0 +1,149 @@ +-- jenkins_hash.vhd: Jenkins hashing function VHDL implementation based on https://burtleburtle.net/bob/c/lookup3.c +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + + +entity jenkins_hash is + generic( + -- Width of hashed key in 32-bit words. + LENGTH : natural := 1; + -- Initialization seed value. + INITVAL : std_logic_vector(32-1 downto 0) := X"DEADBABE" + ); + port ( + -- Main clock signal and its synchronous reset. + CLK : in std_logic; + RESET : in std_logic; + -- Input interface --------------------------------------------------------- + INPUT_KEY : in std_logic_vector(LENGTH*32-1 downto 0); -- value to be hashed + INPUT_VALID : in std_logic; -- key valid + -- Output interface -------------------------------------------------------- + OUTPUT_HASH : out std_logic_vector(32-1 downto 0); -- computed hash value + OUTPUT_KEY : out std_logic_vector(LENGTH*32-1 downto 0); -- delayed input key + OUTPUT_VALID : out std_logic -- delayed input valid + ); +end entity; + + + +architecture behavioral of jenkins_hash is + + constant MIX_STAGES : integer := (LENGTH-1) / 3; + constant FINAL_LENGTH : integer := LENGTH - MIX_STAGES*3; + constant INITIAL_VALUE : std_logic_vector(32-1 downto 0) := X"deadbeef" + conv_std_logic_vector(LENGTH*4, 32) + INITVAL; + + type computation_stage is record + a : std_logic_vector(32-1 downto 0); + b : std_logic_vector(32-1 downto 0); + c : std_logic_vector(32-1 downto 0); + key : std_logic_vector(LENGTH*32-1 downto 0); + valid : std_logic; + end record; + type computation_stage_array is array(natural range <>) of computation_stage; + + signal mix_stage : computation_stage_array(0 to MIX_STAGES); + signal mix_to_final : computation_stage; + + signal final_adders : computation_stage; + signal final_key_part : std_logic_vector(FINAL_LENGTH*32-1 downto 0); + +begin + + -- Unsupported configurations checks ----------------------------------------- + assert LENGTH > 0 report "FAILURE: Jenkins Hash key must be at least one word wide!" severity failure; + + -- Set up the internal state ------------------------------------------------- + mix_stage(0).a <= INITIAL_VALUE; + mix_stage(0).b <= INITIAL_VALUE; + mix_stage(0).c <= INITIAL_VALUE; + mix_stage(0).key <= INPUT_KEY; + mix_stage(0).valid <= INPUT_VALID; + + -- Handle most of the key ---------------------------------------------------- + mix_pipeline: for s in 0 to MIX_STAGES-1 generate + signal local_key_part : std_logic_vector(3*32-1 downto 0); + signal adders : computation_stage; + begin + -- initial adding with key words + local_key_part <= mix_stage(s).key(3*32*(s+1)-1 downto 3*32*s); + adders.a <= mix_stage(s).a + local_key_part(32-1 downto 0); + adders.b <= mix_stage(s).b + local_key_part(64-1 downto 32); + adders.c <= mix_stage(s).c + local_key_part(96-1 downto 64); + adders.key <= mix_stage(s).key; + adders.valid <= mix_stage(s).valid; + -- mixing operation itself + mix: entity work.jenkins_mix + generic map ( + LENGTH => LENGTH + ) port map ( + CLK => CLK, + RESET => RESET, + INPUT_A => adders.a, + INPUT_B => adders.b, + INPUT_C => adders.c, + INPUT_KEY => adders.key, + INPUT_VALID => adders.valid, + OUTPUT_A => mix_stage(s+1).a, -- output dirrectly to the next stage + OUTPUT_B => mix_stage(s+1).b, + OUTPUT_C => mix_stage(s+1).c, + OUTPUT_KEY => mix_stage(s+1).key, + OUTPUT_VALID => mix_stage(s+1).valid + ); + end generate; + mix_to_final <= mix_stage(MIX_STAGES); -- output from the last mix stage is input for final + + + -- Handle the last 3 words --------------------------------------------------- + -- initial adding with key words for given length + final_key_part <= mix_to_final.key(LENGTH*32-1 downto LENGTH*32-FINAL_LENGTH*32); + final_length3: if FINAL_LENGTH = 3 generate + final_adders.c <= mix_to_final.c + final_key_part(96-1 downto 64); + final_adders.b <= mix_to_final.b + final_key_part(64-1 downto 32); + final_adders.a <= mix_to_final.a + final_key_part(32-1 downto 0); + end generate; + final_length2: if FINAL_LENGTH = 2 generate + final_adders.c <= mix_to_final.c; + final_adders.b <= mix_to_final.b + final_key_part(64-1 downto 32); + final_adders.a <= mix_to_final.a + final_key_part(32-1 downto 0); + end generate; + final_length1: if FINAL_LENGTH = 1 generate + final_adders.c <= mix_to_final.c; + final_adders.b <= mix_to_final.b; + final_adders.a <= mix_to_final.a + final_key_part(32-1 downto 0); + end generate; + final_length0: if FINAL_LENGTH = 0 generate + assert false report "FAILURE: Jenkins Hash impossible generate state reached in final stage!" severity failure; + end generate; + final_adders.key <= mix_to_final.key; + final_adders.valid <= mix_to_final.valid; + -- final operation itself + final: entity work.jenkins_final + generic map ( + LENGTH => LENGTH + ) port map ( + CLK => CLK, + RESET => RESET, + INPUT_A => final_adders.a, + INPUT_B => final_adders.b, + INPUT_C => final_adders.c, + INPUT_KEY => final_adders.key, + INPUT_VALID => final_adders.valid, + OUTPUT_A => open, -- output dirrectly into hash output + OUTPUT_B => open, + OUTPUT_C => OUTPUT_HASH, -- C is returned as hash + OUTPUT_KEY => OUTPUT_KEY, + OUTPUT_VALID => OUTPUT_VALID + ); + +end architecture; \ No newline at end of file diff --git a/comp/jenkins_mix.vhd b/comp/jenkins_mix.vhd new file mode 100644 index 0000000..da272af --- /dev/null +++ b/comp/jenkins_mix.vhd @@ -0,0 +1,120 @@ +-- jenkins_mix.vhd: Part of Jenkins hashing function based on https://burtleburtle.net/bob/c/lookup3.c +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_unsigned.all; + + + +entity jenkins_mix is + generic( + -- Width of hashed key in 32-bit words. + LENGTH : natural := 1 + ); + port ( + -- Main clock signal and its synchronous reset. + CLK : in std_logic; + RESET : in std_logic; + -- Input interface --------------------------------------------------------- + INPUT_A : in std_logic_vector(32-1 downto 0); + INPUT_B : in std_logic_vector(32-1 downto 0); + INPUT_C : in std_logic_vector(32-1 downto 0); + INPUT_KEY : in std_logic_vector(LENGTH*32-1 downto 0); + INPUT_VALID : in std_logic; + -- Output interface -------------------------------------------------------- + OUTPUT_A : out std_logic_vector(32-1 downto 0); + OUTPUT_B : out std_logic_vector(32-1 downto 0); + OUTPUT_C : out std_logic_vector(32-1 downto 0); + OUTPUT_KEY : out std_logic_vector(LENGTH*32-1 downto 0); + OUTPUT_VALID : out std_logic + ); +end entity; + + + +architecture behavioral of jenkins_mix is + + constant STAGES : integer := 6; + + function rot(x : std_logic_vector(32-1 downto 0); k : natural) return std_logic_vector is + begin + return x(32-k-1 downto 0) & x(32-1 downto 32-k); + end function; + + type computation_stage is record + a : std_logic_vector(32-1 downto 0); + b : std_logic_vector(32-1 downto 0); + c : std_logic_vector(32-1 downto 0); + key : std_logic_vector(LENGTH*32-1 downto 0); + valid : std_logic; + end record; + type computation_stage_array is array(natural range <>) of computation_stage; + + signal s : computation_stage_array(0 to STAGES); + +begin + + -- Input connections + s(0).a <= INPUT_A; + s(0).b <= INPUT_B; + s(0).c <= INPUT_C; + s(0).key <= INPUT_KEY; + s(0).valid <= INPUT_VALID; + + -- Stage 1: a -= c; a ^= rot(c, 4); c += b; + s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4); + s(1).b <= s(0).b; + s(1).c <= s(0).c + s(0).b; + s(1).key <= s(0).key; + s(1).valid <= s(0).valid; + + -- Stage 2: b -= a; b ^= rot(a, 6); a += c; + s(2).a <= s(1).a + s(1).c; + s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6); + s(2).c <= s(1).c; + s(2).key <= s(1).key; + s(2).valid <= s(1).valid; + + -- Stage 3: c -= b; c ^= rot(b, 8); b += a; + s(3).a <= s(2).a; + s(3).b <= s(2).b + s(2).a; + s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8); + s(3).key <= s(2).key; + s(3).valid <= s(2).valid; + + -- Stage 4: a -= c; a ^= rot(c,16); c += b; + s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16); + s(4).b <= s(3).b; + s(4).c <= s(3).c + s(3).b; + s(4).key <= s(3).key; + s(4).valid <= s(3).valid; + + -- Stage 5: b -= a; b ^= rot(a,19); a += c; + s(5).a <= s(4).a + s(4).c; + s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19); + s(5).c <= s(4).c; + s(5).key <= s(4).key; + s(5).valid <= s(4).valid; + + -- Stage 6: c -= b; c ^= rot(b, 4); b += a; + s(6).a <= s(5).a; + s(6).b <= s(5).b + s(5).a; + s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4); + s(6).key <= s(5).key; + s(6).valid <= s(5).valid; + + -- Output connections + OUTPUT_A <= s(STAGES).a; + OUTPUT_B <= s(STAGES).b; + OUTPUT_C <= s(STAGES).c; + OUTPUT_KEY <= s(STAGES).key; + OUTPUT_VALID <= s(STAGES).valid; + +end architecture; \ No newline at end of file diff --git a/filter.vhd b/filter.vhd new file mode 100644 index 0000000..3922bd9 --- /dev/null +++ b/filter.vhd @@ -0,0 +1,204 @@ +-- filter.vhd: Exact match filter for IP addresses using multiple parallel hash tables (architecture) +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_arith.all; +use work.functions_package.all; + + + +architecture structural of filter is + + constant RULE_WIDTH : natural := KEY_WIDTH + DATA_WIDTH + 1; -- each rule record consists of key, data, and empty flag + subtype RULE_KEY is natural range KEY_WIDTH+DATA_WIDTH downto DATA_WIDTH+1; + subtype RULE_DATA is natural range DATA_WIDTH downto 1; + constant RULE_EMPTY : natural := 0; + constant KEY_WORDS : natural := cdiv(KEY_WIDTH, 32); -- hash component operates with 32-bit words + + type uint32_array is array (natural range<>) of std_logic_vector(32-1 downto 0); + type rule_array is array (natural range <>) of std_logic_vector(RULE_WIDTH-1 downto 0); + + signal in_key : std_logic_vector(KEY_WORDS*32-1 downto 0) := (others => '0'); + signal in_valid : std_logic; + + signal out_key : std_logic_vector(KEY_WIDTH-1 downto 0); + signal out_key_found : std_logic; + signal out_data : std_logic_vector(DATA_WIDTH-1 downto 0); + signal out_valid : std_logic; + + signal cfg_record : std_logic_vector(RULE_WIDTH-1 downto 0); + signal cfg_table : std_logic_vector(clog2(TABLES)-1 downto 0); + signal cfg_item : std_logic_vector(clog2(TABLE_SIZE)-1 downto 0); + signal cfg_write : std_logic; + + signal hash_values : uint32_array(0 to TABLES-1); + signal hash_key : std_logic_vector(KEY_WIDTH-1 downto 0); + signal hash_valid : std_logic_vector(TABLES-1 downto 0); + + signal memory_rule : rule_array(0 to TABLES-1); + signal memory_key, memory_key_reg : std_logic_vector(KEY_WIDTH-1 downto 0); + signal memory_valid : std_logic_vector(TABLES-1 downto 0); + + signal match_flags : std_logic_vector(TABLES-1 downto 0); + +begin + + -- Unsupported configurations checks ----------------------------------------- + assert KEY_WIDTH > 0 report "FAILURE: Filter key must be at least one bit wide!" severity failure; + assert DATA_WIDTH > 0 report "FAILURE: Filter data must be at least one bit wide!" severity failure; + assert TABLES >= 2 report "FAILURE: Filter must have at least two tables to support effective hashing scheme!" severity failure; + assert TABLE_SIZE > 1 report "FAILURE: Filter table must have multiple items!" severity failure; + assert 2**clog2(TABLE_SIZE) = TABLE_SIZE report "FAILURE: Filter table must have size that is a power of 2!" severity failure; + + + -- Registering of entity interfaces ------------------------------------------ + -- Input interface + registered_input: if INPUT_REGISTER generate + input_register: process(CLK) + begin + if rising_edge(CLK) then + in_key(KEY_WIDTH-1 downto 0) <= INPUT_KEY; + if RESET = '1' then + in_valid <= '0'; + else + in_valid <= INPUT_VALID; + end if; + end if; + end process; + end generate; + dirrect_input: if not INPUT_REGISTER generate + in_key(KEY_WIDTH-1 downto 0) <= INPUT_KEY; + in_valid <= INPUT_VALID; + end generate; + -- Output interface + registered_output: if OUTPUT_REGISTER generate + output_register: process(CLK) + begin + if rising_edge(CLK) then + OUTPUT_KEY <= out_key; + OUTPUT_KEY_FOUND <= out_key_found; + OUTPUT_DATA <= out_data; + if RESET = '1' then + OUTPUT_VALID <= '0'; + else + OUTPUT_VALID <= out_valid; + end if; + end if; + end process; + end generate; + dirrect_output: if not OUTPUT_REGISTER generate + OUTPUT_KEY_FOUND <= out_key_found; + OUTPUT_DATA <= out_data; + OUTPUT_VALID <= out_valid; + end generate; + -- Configuration interface + registered_config: if CONFIG_REGISTER generate + config_register: process(CLK) + begin + if rising_edge(CLK) then + cfg_record(RULE_KEY) <= CONFIG_KEY; + cfg_record(RULE_DATA) <= CONFIG_DATA; + cfg_record(RULE_EMPTY) <= CONFIG_EMPTY; + cfg_table <= CONFIG_ADDRESS_TABLE; + cfg_item <= CONFIG_ADDRESS_ITEM; + if RESET = '1' then + cfg_write <= '0'; + else + cfg_write <= CONFIG_WRITE; + end if; + end if; + end process; + end generate; + dirrect_config: if not CONFIG_REGISTER generate + cfg_record(RULE_KEY) <= CONFIG_KEY; + cfg_record(RULE_DATA) <= CONFIG_DATA; + cfg_record(RULE_EMPTY) <= CONFIG_EMPTY; + cfg_table <= CONFIG_ADDRESS_TABLE; + cfg_item <= CONFIG_ADDRESS_ITEM; + cfg_write <= CONFIG_WRITE; + end generate; + + + -- Hashing stage ------------------------------------------------------------- + hash_generate: for t in 0 to TABLES-1 generate + signal local_key : std_logic_vector(KEY_WORDS*32-1 downto 0); + signal local_valid : std_logic; + begin + hash: entity work.jenkins_hash + generic map ( + LENGTH => KEY_WORDS, + INITVAL => conv_std_logic_vector(t+1,32) + ) port map ( + CLK => CLK, + RESET => RESET, + INPUT_KEY => in_key, + INPUT_VALID => in_valid, + OUTPUT_HASH => hash_values(t), + OUTPUT_KEY => local_key, + OUTPUT_VALID => hash_valid(t) + ); + key_valid_connection: if t = 0 generate -- key is pipelined inside the hash for table #0 + hash_key <= local_key(KEY_WIDTH-1 downto 0); + end generate; + end generate; + + + -- Storage stage ------------------------------------------------------------- + storage_generate: for t in 0 to TABLES-1 generate + signal table_select : std_logic; + signal write_here : std_logic; + begin + storage: entity work.block_memory + generic map ( + ITEM_WIDTH => RULE_WIDTH, + ITEMS => TABLE_SIZE, + OUTPUT_REGISTER => false + ) port map ( + CLK => CLK, + RESET => RESET, + READ_ADDRESS => hash_values(t)(clog2(TABLE_SIZE)-1 downto 0), -- lowest hash bits are used as address + READ_VALID => hash_valid(t), + READ_DATA => memory_rule(t), + READ_DATA_VALID => memory_valid(t), + WRITE_DATA => cfg_record, + WRITE_ADDRESS => cfg_item, + WRITE_VALID => write_here + ); + table_select <= '1' when cfg_table = conv_std_logic_vector(t,clog2(TABLES)) else '0'; -- table write enable selection + write_here <= cfg_write and table_select; + end generate; + key_memory_register: process(CLK) -- key pipeline to match memory latency + begin + if rising_edge(CLK) then + memory_key <= hash_key; -- memory is configured to have one cycle read latecy + -- memory_key_reg <= hash_key; + -- memory_key <= memory_key_reg; + end if; + end process; + + + -- Match decoding stage ------------------------------------------------------ + compare_and_select: process(memory_key, memory_rule) + begin + out_key_found <= '0'; + out_data <= (others => 'X'); + for t in 0 to TABLES-1 loop + if memory_key = memory_rule(t)(RULE_KEY) then -- main key compares + if memory_rule(t)(RULE_EMPTY) = '0' then -- do not forget to ignore empty rules + out_key_found <= '1'; + out_data <= memory_rule(t)(RULE_DATA); + end if; + end if; + end loop; + end process; + out_valid <= memory_valid(0); -- select pipelined valid flag from table #0 + out_key <= memory_key; + +end architecture; \ No newline at end of file diff --git a/filter_ent.vhd b/filter_ent.vhd new file mode 100644 index 0000000..ae1253a --- /dev/null +++ b/filter_ent.vhd @@ -0,0 +1,52 @@ +-- filter_ent.vhd: Exact match filter for IP addresses using multiple parallel hash tables (entity) +-- Copyright (C) 2019 FIT BUT +-- Author(s): Lukas Kekely +-- +-- SPDX-License-Identifier: BSD-3-Clause + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_arith.all; +use work.functions_package.all; + + + +entity filter is + generic( + -- Width of hashed key (IP address) in bits. + KEY_WIDTH : natural := 128; + -- Width of data value associated with each key in bits. + DATA_WIDTH : natural := 16; + -- Number of parallel hash tables or hash functions used. + TABLES : natural := 4; + -- Number of items in each hash table. Must be a power of 2. + TABLE_SIZE : natural := 2048; + -- Enables registers on selected interfaces for better frequency. + INPUT_REGISTER : boolean := true; + OUTPUT_REGISTER : boolean := true; + CONFIG_REGISTER : boolean := true + ); + port ( + -- Main clock signal and its synchronous reset. + CLK : in std_logic; + RESET : in std_logic; + -- Input interface --------------------------------------------------------- + INPUT_KEY : in std_logic_vector(KEY_WIDTH-1 downto 0); -- searched key + INPUT_VALID : in std_logic; -- key valid flag + -- Output interface -------------------------------------------------------- + OUTPUT_KEY : out std_logic_vector(KEY_WIDTH-1 downto 0); -- delayed searched key + OUTPUT_KEY_FOUND : out std_logic; -- key was found successfully + OUTPUT_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data associated with the found key + OUTPUT_VALID : out std_logic; -- delayed input valid + -- Configuration interface (insertion of rules) ---------------------------- + CONFIG_KEY : in std_logic_vector(KEY_WIDTH-1 downto 0); -- key value of a rule + CONFIG_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data value of a rule + CONFIG_EMPTY : in std_logic; -- rule is empty flag (data+key are ignored and rule cannot be matched) + CONFIG_ADDRESS_TABLE : in std_logic_vector(clog2(TABLES)-1 downto 0); -- address where to write the rule - table selection + CONFIG_ADDRESS_ITEM : in std_logic_vector(clog2(TABLE_SIZE)-1 downto 0); -- address where to write the rule - item selection in the table + CONFIG_WRITE : in std_logic -- write enable flag + ); +end entity; diff --git a/synth/filter.tcl b/synth/filter.tcl new file mode 100644 index 0000000..aa738cf --- /dev/null +++ b/synth/filter.tcl @@ -0,0 +1,39 @@ +# filter.tcl: Verification execution script for ModelSim +# Copyright (C) 2019 FIT BUT +# Author(s): Lukas Kekely +# +# SPDX-License-Identifier: BSD-3-Clause + + + +# Create Vivado Project +#create_project -part xc7vx330tffg1157-1 -force filter_vivado +create_project -part xc7k160tffv676-1 -force filter_vivado +set_param project.enableVHDL2008 1 +set_property target_language VHDL [current_project] +set_property enable_vhdl_2008 1 [current_project] + +# Add source files +add_files -norecurse \ + ../comp/functions.vhd \ + ../comp/block_memory.vhd \ + ../comp/jenkins_mix.vhd \ + ../comp/jenkins_final.vhd \ + ../comp/jenkins_hash.vhd \ + ../filter_ent.vhd \ + ../filter.vhd +set_property file_type {VHDL 2008} [get_files] +set_property top filter [current_fileset] + +# Add contraints file +add_files -fileset constrs_1 filter.xdc + +# Run synthesis +set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value "-mode out_of_context" -objects [get_runs synth_1] +launch_runs synth_1 +wait_on_run synth_1 +open_run synth_1 + +# Generate reports +report_timing_summary -delay_type min_max -report_unconstrained -max_paths 64 -input_pins -name timing_1 -file filter_synthesis_timing.log +report_utilization -file filter_synthesis_utilization.log diff --git a/synth/filter.xdc b/synth/filter.xdc new file mode 100644 index 0000000..d4e920c --- /dev/null +++ b/synth/filter.xdc @@ -0,0 +1,14 @@ +# filter.tcl: Verification execution script for ModelSim +# Copyright (C) 2019 FIT BUT +# Author(s): Lukas Kekely +# +# SPDX-License-Identifier: BSD-3-Clause + + + +# Configure clock frequencies +create_clock -period 4 [get_ports CLK] + +# Configure delays for synthesis +set_input_delay -clock [get_clocks CLK] 1 [all_inputs] +set_output_delay -clock [get_clocks CLK] 1 [all_outputs] \ No newline at end of file diff --git a/synth/filter_synthesis_timing.log b/synth/filter_synthesis_timing.log new file mode 100644 index 0000000..34ca125 --- /dev/null +++ b/synth/filter_synthesis_timing.log @@ -0,0 +1,18065 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:34:48 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_timing_summary -delay_type min_max -report_unconstrained -max_paths 64 -input_pins -name timing_1 -file filter_synthesis_timing.log +| Design : filter +| Device : 7k160t-ffv676 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (0) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (0) +------------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + -14.185 -5464.168 413 2121 0.190 0.000 0 2121 1.505 0.000 0 635 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +CLK {0.000 2.000} 4.000 250.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +CLK -14.185 -5464.168 413 2121 0.190 0.000 0 2121 1.505 0.000 0 635 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: CLK + To Clock: CLK + +Setup : 413 Failing Endpoints, Worst Slack -14.185ns, Total Violation -5464.168ns +Hold : 0 Failing Endpoints, Worst Slack 0.190ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.505ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB18E1 r storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB18E1 r storage_generate[2].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.578 4.025 storage_generate[2].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB18E1 r storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB18E1 r storage_generate[2].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[11]) + -0.581 4.022 storage_generate[2].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB36E1 r storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.463ns (logic 9.952ns (56.990%) route 7.511ns (43.010%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 17.551 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, unplaced) 0.584 18.135 storage_generate[2].storage/O76[10] + RAMB18E1 r storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB18E1 r storage_generate[2].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.135 + ------------------------------------------------------------------- + slack -14.110 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB36E1 r storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[1].storage/O76[9] + RAMB18E1 r storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB18E1 r storage_generate[1].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.578 4.025 storage_generate[1].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB36E1 r storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB36E1 r storage_generate[3].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[3].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.094ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.447ns (logic 9.936ns (56.951%) route 7.511ns (43.049%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[3].hash/Q[4] + r hash_generate[3].hash/plusOp_inferred__0/i__carry/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[3].hash/plusOp_inferred__0/i__carry/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[3].hash/plusOp_inferred__0/i__carry_n_0 + r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[3].hash/plusOp_inferred__0/i__carry__0/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556_0[1] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_861__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_587_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_556/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_904__0_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_628_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_586/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_654/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_967_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_665_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_629/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[16] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_413__2_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[17] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_945_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_661_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_705/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[21] + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[3].hash/final/mix_stage[1][b][25] + r hash_generate[3].hash/final/memory_reg_0_i_846/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[3].hash/final/memory_reg_0_i_846/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[3].hash/final/L8_out[25] + r hash_generate[3].hash/final/memory_reg_0_i_576/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[3].hash/final/memory_reg_0_i_576/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[3].hash/final/memory_reg_0_i_576_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_558/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[3].hash/final/memory_reg_0_i_558/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[3].hash/final/memory_reg_0_i_780__1[6] + r hash_generate[3].hash/final/memory_reg_0_i_321__2/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[3].hash/final/memory_reg_0_i_321__2/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[3].hash/final/memory_reg_0_i_321__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[3].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[3].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[3].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[3].hash/final/minusOp10_out_1[13] + r hash_generate[3].hash/final/memory_reg_0_i_238__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[3].hash/final/memory_reg_0_i_238__2/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[3].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[3].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[3].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[3].hash/final/minusOp8_out[17] + r hash_generate[3].hash/final/memory_reg_0_i_93__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[3].hash/final/memory_reg_0_i_93__2/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[3].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[3].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[3].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[3].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[3].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[3].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[3].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[3].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[3].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[3].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[3].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[3].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[3].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[3].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[3].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[3].hash/final/memory_reg_0_i_350__2[5] + r hash_generate[3].hash/final/memory_reg_0_i_190__2/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[3].hash/final/memory_reg_0_i_190__2/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[3].hash/final/memory_reg_0_i_190__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[3].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[3].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[3].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[3].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[3].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[3].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[3].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[3].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[3].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[3].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[3].hash/final/memory_reg_0_i_85__2/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[3].hash/final/memory_reg_0_i_85__2/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[3].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[3].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[3].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[3].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[3].hash/final/memory_reg_0_i_16__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[3].hash/final/memory_reg_0_i_16__2/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[3].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[3].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[3].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.535 r hash_generate[3].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.119 storage_generate[3].storage/O76[9] + RAMB18E1 r storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[3].storage/CLK + RAMB18E1 r storage_generate[3].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.578 4.025 storage_generate[3].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.119 + ------------------------------------------------------------------- + slack -14.094 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB36E1 r storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[2].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.048ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.401ns (logic 10.087ns (57.969%) route 7.314ns (42.031%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.318 r hash_generate[2].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, unplaced) 0.000 16.318 hash_generate[2].hash/final/memory_reg_0_i_29_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_26/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.538 r hash_generate[2].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, unplaced) 0.258 16.796 hash_generate[2].hash/final/memory_reg_0_i_26_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_24__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 16.951 r hash_generate[2].hash/final/memory_reg_0_i_24__1/O + net (fo=1, unplaced) 0.000 16.951 hash_generate[2].hash/final/memory_reg_0_i_24__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_4/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.261 r hash_generate[2].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, unplaced) 0.008 17.269 hash_generate[2].hash/final/memory_reg_0_i_4_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.489 r hash_generate[2].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, unplaced) 0.584 18.073 storage_generate[2].storage/O76[5] + RAMB18E1 r storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB18E1 r storage_generate[2].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + -0.578 4.025 storage_generate[2].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.073 + ------------------------------------------------------------------- + slack -14.048 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB36E1 r storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36E1 r storage_generate[1].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[1].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.369ns (logic 9.858ns (56.758%) route 7.511ns (43.242%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[4]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[1].hash/mix_pipeline[0].mix/Q[4] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_891_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_795_n_6 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_893__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/S[2] + CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 3.000 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, unplaced) 0.000 3.000 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.220 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, unplaced) 0.288 3.508 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.663 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, unplaced) 0.000 3.663 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.973 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CO[3] + net (fo=1, unplaced) 0.000 3.973 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.193 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.471 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.626 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_675/O + net (fo=10, unplaced) 0.383 5.009 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_2 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.062 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025/O + net (fo=1, unplaced) 0.000 5.062 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1025_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.372 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/CO[3] + net (fo=1, unplaced) 0.000 5.372 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.592 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_643/O[1] + net (fo=8, unplaced) 0.278 5.870 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.025 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0/O + net (fo=1, unplaced) 0.000 6.025 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_414__0_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.365 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.732 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[17] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.884 f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.248 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.301 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003/O + net (fo=1, unplaced) 0.348 7.649 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1003_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.883 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, unplaced) 0.000 7.883 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.103 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, unplaced) 0.476 8.579 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.734 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.734 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.044 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.044 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.264 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.744 hash_generate[1].hash/final/O75[25] + r hash_generate[1].hash/final/memory_reg_0_i_876/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.899 r hash_generate[1].hash/final/memory_reg_0_i_876/O + net (fo=1, unplaced) 0.363 10.262 hash_generate[1].hash/final/L8_out[25] + r hash_generate[1].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.569 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.569 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.714 r hash_generate[1].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.081 hash_generate[1].hash/final/memory_reg_0_i_810__0[6] + r hash_generate[1].hash/final/memory_reg_0_i_321__0/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.233 r hash_generate[1].hash/final/memory_reg_0_i_321__0/O + net (fo=1, unplaced) 0.000 11.233 hash_generate[1].hash/final/memory_reg_0_i_321__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.543 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.543 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.763 r hash_generate[1].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.243 hash_generate[1].hash/final/minusOp10_out_0[13] + r hash_generate[1].hash/final/memory_reg_0_i_238__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.398 r hash_generate[1].hash/final/memory_reg_0_i_238__0/O + net (fo=1, unplaced) 0.000 12.398 hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.708 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.708 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 12.928 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.196 hash_generate[1].hash/final/minusOp8_out[17] + r hash_generate[1].hash/final/memory_reg_0_i_93__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.351 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, unplaced) 0.000 13.351 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.661 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.669 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.729 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.729 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.789 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.789 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.849 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.849 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.909 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 13.909 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.969 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 13.969 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.029 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.029 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.249 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.507 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + r hash_generate[1].hash/final/memory_reg_0_i_190__0/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.662 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, unplaced) 0.000 14.662 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 14.972 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 14.980 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.040 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.040 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.100 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.100 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.160 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.160 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.349 r hash_generate[1].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.707 hash_generate[1].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[1].hash/final/memory_reg_0_i_85__0/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.849 r hash_generate[1].hash/final/memory_reg_0_i_85__0/O + net (fo=1, unplaced) 0.000 15.849 hash_generate[1].hash/final/memory_reg_0_i_85__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.159 r hash_generate[1].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.167 hash_generate[1].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.387 r hash_generate[1].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.850 hash_generate[1].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[1].hash/final/memory_reg_0_i_16__0/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.005 r hash_generate[1].hash/final/memory_reg_0_i_16__0/O + net (fo=1, unplaced) 0.000 17.005 hash_generate[1].hash/final/memory_reg_0_i_16__0_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.315 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.315 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + r hash_generate[1].hash/final/memory_reg_0_i_2/CI + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.457 r hash_generate[1].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.041 storage_generate[1].storage/O76[8] + RAMB18E1 r storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB18E1 r storage_generate[1].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[11]) + -0.581 4.022 storage_generate[1].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.041 + ------------------------------------------------------------------- + slack -14.019 + +Slack (VIOLATED) : -14.019ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.382ns (logic 9.871ns (56.790%) route 7.511ns (43.210%)) + Logic Levels: 50 (CARRY4=35 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/S[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/I0 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/I1 + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/I0 + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/I3 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/I4 + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/S[1] + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/I4 + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/I4 + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/DI[3] + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/I0 + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + r hash_generate[2].hash/final/memory_reg_0_i_874/I0 + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + r hash_generate[2].hash/final/memory_reg_0_i_580/DI[1] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_562/CI + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + r hash_generate[2].hash/final/memory_reg_0_i_321__1/I2 + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_256/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_259/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + r hash_generate[2].hash/final/memory_reg_0_i_238__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_110/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_102/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + r hash_generate[2].hash/final/memory_reg_0_i_93__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_33/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_30/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_27/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_283/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_282/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_264/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_262/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_260/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + r hash_generate[2].hash/final/memory_reg_0_i_190__1/I2 + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_104/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_103/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_95/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_109/CI + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_101/CI + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + r hash_generate[2].hash/final/memory_reg_0_i_85__1/I2 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_32/S[1] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_29/CI + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + r hash_generate[2].hash/final/memory_reg_0_i_16__1/I1 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + r hash_generate[2].hash/final/memory_reg_0_i_3/S[1] + CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 17.470 r hash_generate[2].hash/final/memory_reg_0_i_3/O[3] + net (fo=9, unplaced) 0.584 18.054 storage_generate[2].storage/O76[7] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[11]) + -0.568 4.035 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.035 + arrival time -18.054 + ------------------------------------------------------------------- + slack -14.019 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[5]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[5]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[5]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[5] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[9]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[5]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_1/ADDRARDADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[5]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[5]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[5] + RAMB36E1 r storage_generate[0].storage/memory_reg_1/ADDRARDADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[9]) + 0.145 0.443 storage_generate[0].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[5]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_2/ADDRARDADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[5]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[5]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[5] + RAMB36E1 r storage_generate[0].storage/memory_reg_2/ADDRARDADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_2/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[9]) + 0.145 0.443 storage_generate[0].storage/memory_reg_2 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[5]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_3/ADDRARDADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[5]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[5]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[5] + RAMB36E1 r storage_generate[0].storage/memory_reg_3/ADDRARDADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_3/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[9]) + 0.145 0.443 storage_generate[0].storage/memory_reg_3 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[5]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_4/ADDRARDADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[5]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[5]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[5] + RAMB36E1 r storage_generate[0].storage/memory_reg_4/ADDRARDADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_4/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[9]) + 0.145 0.443 storage_generate[0].storage/memory_reg_4 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_5/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_5/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: CLK +Waveform(ns): { 0.000 2.000 } +Period(ns): 4.000 +Sources: { CLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[2].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[3].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_0/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_2/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_3/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_4/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_5/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_6/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_7/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[0].storage/memory_reg_8/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_0/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_2/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_3/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_4/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_5/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_6/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_7/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[1].storage/memory_reg_8/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_0/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_2/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_3/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_4/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_5/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_6/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_7/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[2].storage/memory_reg_8/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 4.000 1.817 storage_generate[3].storage/memory_reg_0/CLKBWRCLK +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[104]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[104]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[105]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[105]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[106]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[106]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[107]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[107]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[108]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[108]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[109]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[109]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[10]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[10]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[110]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[110]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[111]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[111]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[112]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[112]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[113]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[113]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[114]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[114]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[115]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[115]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[116]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[116]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[117]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[117]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[118]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[118]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[119]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[119]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[11]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[11]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[120]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[120]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[121]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[121]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[122]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[122]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[123]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[123]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[124]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[124]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[125]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[125]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[126]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[126]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[127]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[127]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[12]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[12]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[104]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[104]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[105]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[105]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[106]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[106]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[107]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[107]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[108]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[108]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[109]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[109]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[10]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[10]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[110]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[110]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[111]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[111]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[112]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[112]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[113]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[113]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[114]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[114]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[115]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[115]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[116]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[116]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[117]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[117]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[118]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[118]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[119]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[119]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[11]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[11]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[120]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[120]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[121]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[121]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[122]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[122]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[123]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[123]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[124]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[124]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[125]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[125]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[126]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[126]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[127]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[127]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[12]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[12]/C + + + diff --git a/synth/filter_synthesis_utilization.log b/synth/filter_synthesis_utilization.log new file mode 100644 index 0000000..7fd4738 --- /dev/null +++ b/synth/filter_synthesis_utilization.log @@ -0,0 +1,186 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:34:48 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_utilization -file filter_synthesis_utilization.log +| Design : filter +| Device : xc7k160tffv676-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 3498 | 0 | 0 | 101400 | 3.45 | +| LUT as Logic | 3498 | 0 | 0 | 101400 | 3.45 | +| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | +| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 | +| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 563 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 34 | 0 | 0 | 325 | 10.46 | +| RAMB36/FIFO* | 32 | 0 | 0 | 325 | 9.85 | +| RAMB36E1 only | 32 | | | | | +| RAMB18 | 4 | 0 | 0 | 650 | 0.62 | +| RAMB18E1 only | 4 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 0 | 0 | 0 | 400 | 0.00 | +| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 384 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 0 | 32 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT5 | 995 | LUT | +| LUT6 | 950 | LUT | +| LUT3 | 900 | LUT | +| LUT2 | 874 | LUT | +| CARRY4 | 681 | CarryLogic | +| FDRE | 563 | Flop & Latch | +| LUT4 | 260 | LUT | +| LUT1 | 228 | LUT | +| RAMB36E1 | 32 | Block Memory | +| RAMB18E1 | 4 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/synth/filter_vivado.cache/wt/project.wpc b/synth/filter_vivado.cache/wt/project.wpc new file mode 100644 index 0000000..e3a38cb --- /dev/null +++ b/synth/filter_vivado.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +6d6f64655f636f756e7465727c42617463684d6f6465:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/synth/filter_vivado.cache/wt/synthesis.wdf b/synth/filter_vivado.cache/wt/synthesis.wdf new file mode 100644 index 0000000..6cc8ac4 --- /dev/null +++ b/synth/filter_vivado.cache/wt/synthesis.wdf @@ -0,0 +1,51 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b313630746666763637362d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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+ + +
+
+ + + + + + + +
+ + diff --git a/synth/filter_vivado.hw/filter_vivado.lpr b/synth/filter_vivado.hw/filter_vivado.lpr new file mode 100644 index 0000000..aa1fd32 --- /dev/null +++ b/synth/filter_vivado.hw/filter_vivado.lpr @@ -0,0 +1,7 @@ + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_1.xml b/synth/filter_vivado.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..e8978b9 --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_2.xml b/synth/filter_vivado.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..e8978b9 --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_3.xml b/synth/filter_vivado.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..5aaf564 --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.Vivado_Implementation.queue.rst b/synth/filter_vivado.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/.init_design.begin.rst b/synth/filter_vivado.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..bfc0a2a --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.init_design.end.rst b/synth/filter_vivado.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst b/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..bfc0a2a --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.opt_design.end.rst b/synth/filter_vivado.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst b/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst new file mode 100644 index 0000000..bfc0a2a --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.phys_opt_design.end.rst b/synth/filter_vivado.runs/impl_1/.phys_opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/.place_design.begin.rst b/synth/filter_vivado.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..bfc0a2a --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.place_design.end.rst b/synth/filter_vivado.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/.route_design.begin.rst b/synth/filter_vivado.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..bfc0a2a --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.route_design.end.rst b/synth/filter_vivado.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/.vivado.begin.rst b/synth/filter_vivado.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..f4c6d0f --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.vivado.end.rst b/synth/filter_vivado.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/impl_1/ISEWrap.js b/synth/filter_vivado.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/synth/filter_vivado.runs/impl_1/ISEWrap.sh b/synth/filter_vivado.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/synth/filter_vivado.runs/impl_1/clockInfo.txt b/synth/filter_vivado.runs/impl_1/clockInfo.txt new file mode 100644 index 0000000..f348b00 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/clockInfo.txt @@ -0,0 +1,10 @@ +------------------------------------- +| Tool Version : Vivado v.2023.2 +| Date : Sun Dec 3 18:52:50 2023 +| Host : veronika-swiftsf11433 +| Design : design_1 +| Device : xc7k160t-ffv676-1-- +------------------------------------- + +For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US + diff --git a/synth/filter_vivado.runs/impl_1/filter.tcl b/synth/filter_vivado.runs/impl_1/filter.tcl new file mode 100644 index 0000000..697b993 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter.tcl @@ -0,0 +1,304 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +namespace eval ::optrace { + variable script "/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.tcl" + variable category "vivado_impl" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } elseif { [info exist ::env(HOST)] } { + set host $::env(HOST) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +OPTRACE "impl_1" END { } +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +OPTRACE "impl_1" START { ROLLUP_1 } +OPTRACE "Phase: Init Design" START { ROLLUP_AUTO } +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 1 + set_param checkpoint.writeSynthRtdsInDcp 1 + set_param synth.incrementalSynthesisCache /tmp/.Xil_veronikaplevacova/Vivado-18297-veronika-swiftsf11433/incrSyn + set_param runs.launchOptions { -jobs 2 } +OPTRACE "create in-memory project" START { } + create_project -in_memory -part xc7k160tffv676-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 +OPTRACE "create in-memory project" END { } +OPTRACE "set parameters" START { } + set_property webtalk.parent_dir /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.cache/wt [current_project] + set_property parent.project_path /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr [current_project] + set_property ip_output_repo /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] +OPTRACE "set parameters" END { } +OPTRACE "add files" START { } + add_files -quiet /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp +OPTRACE "read constraints: implementation" START { } + read_xdc /home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc +OPTRACE "read constraints: implementation" END { } +OPTRACE "read constraints: implementation_pre" START { } +OPTRACE "read constraints: implementation_pre" END { } +OPTRACE "add files" END { } +OPTRACE "link_design" START { } + link_design -top filter -part xc7k160tffv676-1 -mode out_of_context +OPTRACE "link_design" END { } +OPTRACE "gray box cells" START { } +OPTRACE "gray box cells" END { } +OPTRACE "init_design_reports" START { REPORT } +OPTRACE "init_design_reports" END { } +OPTRACE "init_design_write_hwdef" START { } +OPTRACE "init_design_write_hwdef" END { } + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Init Design" END { } +OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO } +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb +OPTRACE "read constraints: opt_design" START { } +OPTRACE "read constraints: opt_design" END { } +OPTRACE "opt_design" START { } + opt_design +OPTRACE "opt_design" END { } +OPTRACE "read constraints: opt_design_post" START { } +OPTRACE "read constraints: opt_design_post" END { } +OPTRACE "opt_design reports" START { REPORT } + create_report "impl_1_opt_report_drc_0" "report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx" +OPTRACE "opt_design reports" END { } +OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force filter_opt.dcp +OPTRACE "Opt Design: write_checkpoint" END { } + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Opt Design" END { } +OPTRACE "Phase: Place Design" START { ROLLUP_AUTO } +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb +OPTRACE "read constraints: place_design" START { } +OPTRACE "read constraints: place_design" END { } + if { [llength [get_debug_cores -quiet] ] > 0 } { +OPTRACE "implement_debug_core" START { } + implement_debug_core +OPTRACE "implement_debug_core" END { } + } +OPTRACE "place_design" START { } + place_design +OPTRACE "place_design" END { } +OPTRACE "read constraints: place_design_post" START { } +OPTRACE "read constraints: place_design_post" END { } +OPTRACE "place_design reports" START { REPORT } + create_report "impl_1_place_report_io_0" "report_io -file filter_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file filter_control_sets_placed.rpt" +OPTRACE "place_design reports" END { } +OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force filter_placed.dcp +OPTRACE "Place Design: write_checkpoint" END { } + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Place Design" END { } +OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO } +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb +OPTRACE "read constraints: phys_opt_design" START { } +OPTRACE "read constraints: phys_opt_design" END { } +OPTRACE "phys_opt_design" START { } + phys_opt_design +OPTRACE "phys_opt_design" END { } +OPTRACE "read constraints: phys_opt_design_post" START { } +OPTRACE "read constraints: phys_opt_design_post" END { } +OPTRACE "phys_opt_design report" START { REPORT } +OPTRACE "phys_opt_design report" END { } +OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force filter_physopt.dcp +OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { } + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Physical Opt Design" END { } +OPTRACE "Phase: Route Design" START { ROLLUP_AUTO } +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb +OPTRACE "read constraints: route_design" START { } +OPTRACE "read constraints: route_design" END { } +OPTRACE "route_design" START { } + route_design +OPTRACE "route_design" END { } +OPTRACE "read constraints: route_design_post" START { } +OPTRACE "read constraints: route_design_post" END { } +OPTRACE "route_design reports" START { REPORT } + create_report "impl_1_route_report_drc_0" "report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file filter_route_status.rpt -pb filter_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file filter_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file filter_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx" +OPTRACE "route_design reports" END { } +OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force filter_routed.dcp +OPTRACE "Route Design: write_checkpoint" END { } +OPTRACE "route_design misc" START { } + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { +OPTRACE "route_design write_checkpoint" START { CHECKPOINT } +OPTRACE "route_design write_checkpoint" END { } + write_checkpoint -force filter_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +OPTRACE "route_design misc" END { } +OPTRACE "Phase: Route Design" END { } +OPTRACE "impl_1" END { } diff --git a/synth/filter_vivado.runs/impl_1/filter.vdi b/synth/filter_vivado.runs/impl_1/filter.vdi new file mode 100644 index 0000000..5a1e705 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter.vdi @@ -0,0 +1,1321 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 18:51:36 2023 +# Process ID: 19329 +# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1 +# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace +# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi +# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +source filter.tcl -notrace +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.508 ; gain = 0.023 ; free physical = 106 ; free virtual = 6598 +Command: link_design -top filter -part xc7k160tffv676-1 -mode out_of_context +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.383 ; gain = 0.000 ; free physical = 131 ; free virtual = 6415 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1767.770 ; gain = 0.000 ; free physical = 122 ; free virtual = 6282 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1773.742 ; gain = 465.234 ; free physical = 114 ; free virtual = 6277 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1824.535 ; gain = 50.793 ; free physical = 205 ; free virtual = 6272 + +Starting Cache Timing Information Task +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 10236edc4 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2345.418 ; gain = 520.883 ; free physical = 117 ; free virtual = 5807 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 146 ; free virtual = 5487 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 +Phase 1 Initialization | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 138 ; free virtual = 5486 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 +Phase 2 Timer Update And Timing Data Collection | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 + +Phase 3 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 10c3daf90 + +Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 134 ; free virtual = 5484 +Retarget | Checksum: 10c3daf90 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 9bde81ac + +Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 132 ; free virtual = 5484 +Constant propagation | Checksum: 9bde81ac +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 5 Sweep +Phase 5 Sweep | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 115 ; free virtual = 5482 +Sweep | Checksum: f9b192b3 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 +BUFG optimization | Checksum: f9b192b3 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 +Shift Register Optimization | Checksum: f9b192b3 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 8 Post Processing Netlist +Phase 8 Post Processing Netlist | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 +Post Processing Netlist | Checksum: f9b192b3 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Phase 9 Finalization + +Phase 9.1 Finalizing Design Cores and Updating Shapes +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 112 ; free virtual = 5479 + +Phase 9.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 111 ; free virtual = 5479 +Phase 9.2 Verifying Netlist Connectivity | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 +Phase 9 Finalization | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 109 ; free virtual = 5479 +INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 105 ; free virtual = 5477 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 36 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports +Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 72 +Ending PowerOpt Patch Enables Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 192 ; free virtual = 5341 +Ending Power Optimization Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 137.883 ; free physical = 172 ; free virtual = 5341 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 172 ; free virtual = 5341 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 +Ending Netlist Obfuscation Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 +INFO: [Common 17-83] Releasing license: Implementation +30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2817.184 ; gain = 1043.441 ; free physical = 171 ; free virtual = 5343 +INFO: [runtcl-4] Executing : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx +Command: report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt. +report_drc completed successfully +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5315 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_opt.dcp' has been generated. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3583ee0c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3d558abc + +Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 132 ; free virtual = 5293 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 8cce5483 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 8cce5483 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 +Phase 1 Placer Initialization | Checksum: 8cce5483 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 47fa083f + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1275ad596 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5286 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 1275ad596 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1457cd503 + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 169 ; free virtual = 5289 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 10 LUTNM shape to break, 4 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 10, total 10, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 12 nets or LUTs. Breaked 10 LUTs, combined 2 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. +INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 10 | 2 | 12 | 0 | 1 | 00:00:00 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 10 | 2 | 12 | 0 | 9 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 19c5c57a6 + +Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 +Phase 2.4 Global Placement Core | Checksum: 1b40ef446 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 +Phase 2 Global Placement | Checksum: 1b40ef446 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 11f4d2582 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5283 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12b805f00 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:21 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 137 ; free virtual = 5282 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 157230410 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 128b350f2 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 + +Phase 3.5 Fast Optimization +Phase 3.5 Fast Optimization | Checksum: 1632181f8 + +Time (s): cpu = 00:00:58 ; elapsed = 00:00:24 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 130 ; free virtual = 5276 + +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: f844008a + +Time (s): cpu = 00:01:00 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5275 + +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 14d2456fe + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 + +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 17ad421e0 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 + +Phase 3.9 Fast Optimization +Phase 3.9 Fast Optimization | Checksum: 17f4b35b0 + +Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 +Phase 3 Detail Placement | Checksum: 17f4b35b0 + +Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 1caaa20ca + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.908 | TNS=-6490.125 | +Phase 1 Physical Synthesis Initialization | Checksum: 179e6ab06 + +Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 153 ; free virtual = 5299 +INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 179e6ab06 + +Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1caaa20ca + +Time (s): cpu = 00:01:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=-16.162. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 186ecb07f + +Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 + +Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 +Phase 4.1 Post Commit Optimization | Checksum: 186ecb07f + +Time (s): cpu = 00:01:54 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5295 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 186ecb07f + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 4x4| 8x8| +|___________|___________________|___________________| +| South| 2x2| 4x4| +|___________|___________________|___________________| +| East| 4x4| 8x8| +|___________|___________________|___________________| +| West| 4x4| 4x4| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 186ecb07f + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Phase 4.3 Placer Reporting | Checksum: 186ecb07f + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2313e4908 + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Ending Placer Task | Checksum: 1402e79b2 + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +75 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:01:57 ; elapsed = 00:01:13 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +INFO: [runtcl-4] Executing : report_io -file filter_io_placed.rpt +report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 123 ; free virtual = 5306 +INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file filter_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 129 ; free virtual = 5308 +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 133 ; free virtual = 5307 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 191 ; free virtual = 5293 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_placed.dcp' has been generated. +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' + +Starting Initial Update Timing Task +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 +INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 2.64s | WALL: 1.05s +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | +Phase 1 Physical Synthesis Initialization | Checksum: 1c58d1c6b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5268 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | + +Phase 2 DSP Register Optimization +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Phase 2 DSP Register Optimization | Checksum: 1c58d1c6b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5269 + +Phase 3 Critical Path Optimization +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net in_key[8]. Re-placed instance registered_input.in_key_reg[8] +INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.142 | TNS=-6267.728 | +INFO: [Physopt 32-81] Processed net in_key[72]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.119 | TNS=-6265.451 | +INFO: [Physopt 32-702] Processed net in_key[72]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_24_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_59_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_98_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_190_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_350[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_93_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_96_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_127_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp10_out_0[9]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_286_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_479_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp12_out[25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_577_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_571_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_429_0[29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_434_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_535_0[24]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_725_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1100__0_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.103 | TNS=-6263.768 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net in_key[0]. Re-placed instance registered_input.in_key_reg[0] +INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.102 | TNS=-6259.511 | +INFO: [Physopt 32-81] Processed net in_key[8]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.099 | TNS=-6259.214 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.072 | TNS=-6256.541 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_433_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_721_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][a][23]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.060 | TNS=-6253.472 | +INFO: [Physopt 32-81] Processed net in_key[2]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[2]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.059 | TNS=-6252.086 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.046 | TNS=-6250.701 | +INFO: [Physopt 32-81] Processed net in_key[64]. Replicated 5 times. +INFO: [Physopt 32-735] Processed net in_key[64]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | +INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] +INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | +INFO: [Physopt 32-81] Processed net in_key[68]. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[68]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.007 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[1]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[1]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.043 | TNS=-6248.027 | +INFO: [Physopt 32-663] Processed net in_key[5]. Re-placed instance registered_input.in_key_reg[5] +INFO: [Physopt 32-735] Processed net in_key[5]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.041 | TNS=-6247.730 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_431_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/minusOp4_out[27]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[25]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6247.631 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Re-placed instance hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1101 +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6245.453 | +INFO: [Physopt 32-663] Processed net in_key[74]. Re-placed instance registered_input.in_key_reg[74] +INFO: [Physopt 32-735] Processed net in_key[74]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.057 | +INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] +INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.255 | +INFO: [Physopt 32-81] Processed net in_key[69]. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[69]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.036 | TNS=-6244.364 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net in_key[66]. Re-placed instance registered_input.in_key_reg[66] +INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.030 | TNS=-6243.770 | +INFO: [Physopt 32-702] Processed net in_key[66]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1066_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.029 | TNS=-6243.275 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net in_key[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_350__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp10_out_0[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_322__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_808__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 22 pins. +INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1151__1_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6243.176 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_724_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Re-placed instance hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_732 +INFO: [Physopt 32-735] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6241.592 | +INFO: [Physopt 32-702] Processed net in_key[65]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1155__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Re-placed instance hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1 +INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +INFO: [Physopt 32-663] Processed net in_key[10]. Re-placed instance registered_input.in_key_reg[10] +INFO: [Physopt 32-735] Processed net in_key[10]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +INFO: [Physopt 32-702] Processed net in_key[71]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[30]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_430_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_670_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[19]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_962_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[15]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_889__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_797__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/O76[9]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 137 ; free virtual = 5271 +Phase 3 Critical Path Optimization | Checksum: 17af5ebfb + +Time (s): cpu = 00:00:41 ; elapsed = 00:00:21 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 131 ; free virtual = 5271 + +Phase 4 Critical Path Optimization +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[71]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[71]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.023 | TNS=-6240.602 | +INFO: [Physopt 32-81] Processed net in_key[66]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.021 | TNS=-6240.404 | +INFO: [Physopt 32-81] Processed net in_key[64]_repN. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[64]_repN. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6240.008 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[9]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6239.810 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[0]. Replicated 5 times. +INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.018 | TNS=-6239.316 | +INFO: [Physopt 32-663] Processed net in_key[72]. Re-placed instance registered_input.in_key_reg[72] +INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.017 | TNS=-6238.820 | +INFO: [Physopt 32-702] Processed net in_key[2]_repN. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_3_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_258_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_259_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_256_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_580_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_579_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_575_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_677_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Critical path length was reduced through logic transformation on cell hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_comp. +INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[16]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.015 | TNS=-6237.929 | +INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.732 | +INFO: [Physopt 32-663] Processed net in_key[78]. Re-placed instance registered_input.in_key_reg[78] +INFO: [Physopt 32-735] Processed net in_key[78]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.533 | +INFO: [Physopt 32-663] Processed net in_key[13]. Re-placed instance registered_input.in_key_reg[13] +INFO: [Physopt 32-735] Processed net in_key[13]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_722_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[24]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_385__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_912_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_858__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_768__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/plusOp_inferred__0/i__carry__1_n_7. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/O76[9]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 +Phase 4 Critical Path Optimization | Checksum: 17af5ebfb + +Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 +INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-16.012 | TNS=-6236.939 | + +Summary of Physical Synthesis Optimizations +============================================ + + +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Critical Path | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 2 | 00:00:31 | +| Total | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 3 | 00:00:31 | +------------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 +Ending Physical Synthesis Task | Checksum: 27673438e + +Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +INFO: [Common 17-83] Releasing license: Implementation +415 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:01:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 109 ; free virtual = 5273 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: a88baaee ConstDB: 0 ShapeSum: d8eec616 RouteDB: 0 +WARNING: [Route 35-197] Clock port "CLK" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. +WARNING: [Route 35-198] Port "CONFIG_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[94]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[94]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[116]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[116]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[114]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[114]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[102]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[102]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[98]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[98]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[96]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[96]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[86]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[86]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[84]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[84]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[70]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[70]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[103]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[103]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[57]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[57]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[66]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[66]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[64]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[64]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[90]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[90]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[89]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[89]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[76]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[76]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[50]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[50]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[88]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[88]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[44]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[44]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[48]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[48]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[72]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[72]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[54]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[54]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[46]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[46]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[82]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[82]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[77]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[77]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[52]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[52]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[69]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[69]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[47]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[47]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_WRITE" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_WRITE". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "RESET" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "RESET". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[78]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[78]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[75]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[75]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[74]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[74]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[68]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[68]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[126]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[126]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[53]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[53]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[73]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[73]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_EMPTY" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_EMPTY". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[97]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[97]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[55]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[55]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +INFO: [Common 17-14] Message 'Route 35-198' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. +Post Restoration Checksum: NetGraph: f5668f66 | NumContArr: ae2b9928 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 328e41dc8 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:35 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 97 ; free virtual = 5070 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 328e41dc8 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 117 ; free virtual = 5073 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 328e41dc8 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 119 ; free virtual = 5075 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 242e0954c + +Time (s): cpu = 00:00:58 ; elapsed = 00:00:38 . Memory (MB): peak = 2979.195 ; gain = 142.992 ; free physical = 163 ; free virtual = 5036 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-15.599| TNS=-6066.110| WHS=0.033 | THS=0.000 | + + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 5168 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 5168 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 1d6088a45 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 1d6088a45 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 + +Phase 3.2 Initial Net Routing +Phase 3.2 Initial Net Routing | Checksum: 2130f4a2f + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 +Phase 3 Initial Routing | Checksum: 2130f4a2f + +Time (s): cpu = 00:01:33 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 4441 + Number of Nodes with overlaps = 1719 + Number of Nodes with overlaps = 1028 + Number of Nodes with overlaps = 514 + Number of Nodes with overlaps = 269 + Number of Nodes with overlaps = 127 + Number of Nodes with overlaps = 70 + Number of Nodes with overlaps = 32 + Number of Nodes with overlaps = 19 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.774| TNS=-6851.693| WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 225940652 + +Time (s): cpu = 00:04:22 ; elapsed = 00:02:04 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 215 ; free virtual = 5156 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 231 + Number of Nodes with overlaps = 180 + Number of Nodes with overlaps = 152 + Number of Nodes with overlaps = 92 + Number of Nodes with overlaps = 84 + Number of Nodes with overlaps = 60 + Number of Nodes with overlaps = 44 + Number of Nodes with overlaps = 35 + Number of Nodes with overlaps = 37 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 20 + Number of Nodes with overlaps = 13 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.494| TNS=-6783.227| WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 2cd491a74 + +Time (s): cpu = 00:05:31 ; elapsed = 00:02:59 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 325 ; free virtual = 5054 + +Phase 4.3 Global Iteration 2 + Number of Nodes with overlaps = 141 + Number of Nodes with overlaps = 144 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 105 + Number of Nodes with overlaps = 121 + Number of Nodes with overlaps = 78 + Number of Nodes with overlaps = 57 + Number of Nodes with overlaps = 48 + Number of Nodes with overlaps = 27 + Number of Nodes with overlaps = 17 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 10 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | + +Phase 4.3 Global Iteration 2 | Checksum: 18900c83b + +Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 +Phase 4 Rip-up And Reroute | Checksum: 18900c83b + +Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp + +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 18900c83b + +Time (s): cpu = 00:06:36 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 183 ; free virtual = 5022 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | + + Number of Nodes with overlaps = 0 +Phase 5.1 Delay CleanUp | Checksum: 1a7ad13b4 + +Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 1a7ad13b4 + +Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 +Phase 5 Delay and Skew Optimization | Checksum: 1a7ad13b4 + +Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 +Phase 6 Post Hold Fix | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 1.77316 % + Global Horizontal Routing Utilization = 2.02251 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +--GLOBAL Congestion: +Utilization threshold used for congestion level computation: 0.85 +Congestion Report +North Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 80.1802%, No Congested Regions. +East Dir 2x2 Area, Max Cong = 91.5441%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): + INT_L_X32Y168 -> INT_R_X33Y169 +West Dir 1x1 Area, Max Cong = 94.1176%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): + INT_L_X28Y189 -> INT_L_X28Y189 + INT_L_X26Y188 -> INT_L_X26Y188 + INT_R_X27Y188 -> INT_R_X27Y188 + INT_L_X28Y187 -> INT_L_X28Y187 + INT_L_X14Y172 -> INT_L_X14Y172 + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 1 +Effective congestion level: 2 Aspect Ratio: 0.5 Sparse Ratio: 0.5 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 + +Phase 7 Route finalize | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 133 ; free virtual = 5020 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 128 ; free virtual = 5019 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 26293a506 + +Time (s): cpu = 00:06:50 ; elapsed = 00:03:50 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 243 ; free virtual = 5043 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | + +WARNING: [Route 35-328] Router estimated timing not met. +Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. +Phase 10 Post Router Timing | Checksum: 26293a506 + +Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 224 ; free virtual = 5039 +INFO: [Route 35-16] Router Completed Successfully + +Phase 11 Post-Route Event Processing +Phase 11 Post-Route Event Processing | Checksum: 123c431d6 + +Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 +Ending Routing Task | Checksum: 123c431d6 + +Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +435 Infos, 109 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:06:55 ; elapsed = 00:03:53 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 137 ; free virtual = 5047 +INFO: [runtcl-4] Executing : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx +Command: report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx +Command: report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +INFO: [DRC 23-133] Running Methodology with 4 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx +Command: report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +445 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file filter_route_status.rpt -pb filter_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. +INFO: [runtcl-4] Executing : report_incremental_reuse -file filter_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file filter_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 154 ; free virtual = 4924 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 198 ; free virtual = 4894 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 199 ; free virtual = 4893 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_routed.dcp' has been generated. +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:58:43 2023... diff --git a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.pb b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.pb new file mode 100644 index 0000000..3390588 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt new file mode 100644 index 0000000..6c51a8f --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt @@ -0,0 +1,16 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:58:41 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx +| Design : filter +| Device : 7k160t-ffv676 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx new file mode 100644 index 0000000..dbdfc84 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt new file mode 100644 index 0000000..57d06e7 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt @@ -0,0 +1,99 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:58:41 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_clock_utilization -file filter_clock_utilization_routed.rpt +| Design : filter +| Device : 7k160t-ffv676 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 120 | 0 | 0 | 0 | +| BUFIO | 0 | 32 | 0 | 0 | 0 | +| BUFMR | 0 | 16 | 0 | 0 | 0 | +| BUFR | 0 | 32 | 0 | 0 | 0 | +| MMCM | 0 | 8 | 0 | 0 | 0 | +| PLL | 0 | 8 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | +| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt b/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt new file mode 100644 index 0000000..e88ee81 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt @@ -0,0 +1,80 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:54:00 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_control_sets -verbose -file filter_control_sets_placed.rpt +| Design : filter +| Device : xc7k160t +--------------------------------------------------------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 2 | +| Minimum number of control sets | 2 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 5 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 2 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 1 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 1 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 559 | 206 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 4 | 2 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+--------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | ++--------------+---------------+------------------+------------------+----------------+--------------+ +| CLK | | RESET | 2 | 4 | 2.00 | +| CLK | | | 206 | 559 | 2.71 | ++--------------+---------------+------------------+------------------+----------------+--------------+ + + diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_opted.pb b/synth/filter_vivado.runs/impl_1/filter_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_drc_opted.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt b/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt new file mode 100644 index 0000000..907b2c3 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:52:45 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx +| Design : filter +| Device : xc7k160tffv676-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpx b/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpx new file mode 100644 index 0000000..635a2fe Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_routed.pb b/synth/filter_vivado.runs/impl_1/filter_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_drc_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt new file mode 100644 index 0000000..4b93a7c --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:58:32 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx +| Design : filter +| Device : xc7k160tffv676-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpx new file mode 100644 index 0000000..b8d2514 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt b/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt new file mode 100644 index 0000000..7bf6f97 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt @@ -0,0 +1,718 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:53:59 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_io -file filter_io_placed.rpt +| Design : filter +| Device : xc7k160t +| Speed File : -1 +| Package : ffv676 +| Package Version : FINAL 2012-06-26 +| Package Pin Delay Version : VERS. 2.0 2012-06-26 +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 436 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | MGTXTXN3_116 | Gigabit | | | | | | | | | | | | | | | | +| A4 | | | MGTXTXP3_116 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A12 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A13 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| A21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| A22 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| A23 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| A24 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| A25 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AA2 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA7 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA8 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA9 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA11 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AA12 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA13 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA14 | | High Performance | IO_L7P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA15 | | High Performance | IO_L7N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA17 | | High Performance | IO_L11P_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA18 | | High Performance | IO_L11N_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA19 | | High Performance | IO_L16P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA20 | | High Performance | IO_L16N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AA22 | | High Range | IO_L13N_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA23 | | High Range | IO_L11P_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA24 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA25 | | High Range | IO_L7P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB4 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB5 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB8 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AB9 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB10 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB11 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB12 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB14 | | High Performance | IO_L10P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB15 | | High Performance | IO_L10N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB16 | | High Performance | IO_L12P_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB17 | | High Performance | IO_L14P_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB18 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AB19 | | High Performance | IO_L18P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB20 | | High Performance | IO_L18N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L18P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB24 | | High Range | IO_L11N_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB25 | | High Range | IO_L7N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB26 | | High Range | IO_L9P_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC1 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC2 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC3 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AC6 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC7 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC9 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AC11 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC12 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC13 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC14 | | High Performance | IO_L8P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC15 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AC16 | | High Performance | IO_L12N_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC17 | | High Performance | IO_L14N_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC18 | | High Performance | IO_L13P_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC19 | | High Performance | IO_L17P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AC21 | | High Range | IO_L18N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC22 | | High Range | IO_L17N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC23 | | High Range | IO_L14P_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC24 | | High Range | IO_L14N_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC25 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AC26 | | High Range | IO_L9N_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AD3 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD4 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD6 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AD8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD9 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD10 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD11 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AD13 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD14 | | High Performance | IO_L8N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD15 | | High Performance | IO_L4P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD16 | | High Performance | IO_L6P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AD18 | | High Performance | IO_L13N_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD19 | | High Performance | IO_L17N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD20 | | High Performance | IO_L15P_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD21 | | High Range | IO_L19P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AD23 | | High Range | IO_L16P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD24 | | High Range | IO_L16N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD25 | | High Range | IO_L23P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD26 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE2 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE3 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE5 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE6 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE7 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE8 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AE10 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE11 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE12 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE15 | | High Performance | IO_L4N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE16 | | High Performance | IO_L6N_T0_VREF_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE17 | | High Performance | IO_L1P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE18 | | High Performance | IO_L3P_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE19 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AE20 | | High Performance | IO_L15N_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE21 | | High Range | IO_L19N_T3_VREF_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE22 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE23 | | High Range | IO_L22P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE25 | | High Range | IO_L23N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE26 | | High Range | IO_L21N_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF2 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF3 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF4 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF5 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF6 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AF7 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF8 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF9 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF10 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF12 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF13 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF14 | | High Performance | IO_L2P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF15 | | High Performance | IO_L2N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF16 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AF17 | | High Performance | IO_L1N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF18 | | High Performance | IO_L3N_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF19 | | High Performance | IO_L5P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF20 | | High Performance | IO_L5N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF22 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF23 | | High Range | IO_L22N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF24 | | High Range | IO_L20P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF25 | | High Range | IO_L20N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| B1 | | | MGTXTXN2_116 | Gigabit | | | | | | | | | | | | | | | | +| B2 | | | MGTXTXP2_116 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B5 | | | MGTXRXN3_116 | Gigabit | | | | | | | | | | | | | | | | +| B6 | | | MGTXRXP3_116 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B9 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B11 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B14 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B15 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| B19 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B24 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| B25 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| B26 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C3 | | | MGTXRXN2_116 | Gigabit | | | | | | | | | | | | | | | | +| C4 | | | MGTXRXP2_116 | Gigabit | | | | | | | | | | | | | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C8 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C13 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C16 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| C22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| C23 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| C24 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| C25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| C26 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| D1 | | | MGTXTXN1_116 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTXTXP1_116 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTREFCLK0N_116 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTREFCLK0P_116 | Gigabit | | | | | | | | | | | | | | | | +| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D8 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D13 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| D22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| D23 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| D24 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| D25 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| D26 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E3 | | | MGTXRXN1_116 | Gigabit | | | | | | | | | | | | | | | | +| E4 | | | MGTXRXP1_116 | Gigabit | | | | | | | | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E10 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E11 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E12 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| E20 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| E21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| E23 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E25 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E26 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | MGTXTXN0_116 | Gigabit | | | | | | | | | | | | | | | | +| F2 | | | MGTXTXP0_116 | Gigabit | | | | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F5 | | | MGTREFCLK1N_116 | Gigabit | | | | | | | | | | | | | | | | +| F6 | | | MGTREFCLK1P_116 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F9 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F13 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| F17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F18 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F22 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F23 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F24 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F25 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| F26 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G3 | | | MGTXRXN0_116 | Gigabit | | | | | | | | | | | | | | | | +| G4 | | | MGTXRXP0_116 | Gigabit | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G10 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G12 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G14 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G15 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G19 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| G23 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G24 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| G25 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| G26 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| H2 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| H3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | +| H6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H9 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| H11 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| H12 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H13 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H16 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H21 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| H22 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| H23 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| H24 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H26 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| J4 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| J7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| J8 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J11 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| J14 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J23 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| J24 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| J25 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| J26 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| K2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| K3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | +| K6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K15 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K20 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K21 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| K23 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| K24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| K25 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| K26 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| L3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| L4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| L7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| L8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L17 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L22 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| L23 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| L24 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| L25 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| M2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| M3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| M4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M5 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | +| M6 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| M19 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M24 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M25 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| M26 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| N4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N6 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | +| N7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N8 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N16 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N21 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N22 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N23 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N24 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| N26 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| P1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| P2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P16 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P18 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| P20 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| P22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| P23 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| P24 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| P25 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| P26 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| R1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| R4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| R5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R7 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| R19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| R20 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| R21 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R23 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R25 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| R26 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T2 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T5 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| T6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T7 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | +| T8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| T17 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| T18 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T22 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T23 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T24 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T25 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| U1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| U4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U9 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| U16 | | High Range | IO_25_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U19 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U20 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U21 | | High Range | IO_0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U22 | | High Range | IO_L1P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U23 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| U24 | | High Range | IO_L2P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U25 | | High Range | IO_L2N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U26 | | High Range | IO_L4P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V6 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V9 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| V11 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V12 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | +| V13 | | High Performance | IO_0_VRN_32 | User IO | | 32 | | | | | | | | | | | | | | +| V14 | | High Performance | IO_L24P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V16 | | High Performance | IO_L20P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V17 | | High Performance | IO_L20N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V18 | | High Performance | IO_L23P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V19 | | High Performance | IO_L23N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V20 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| V21 | | High Range | IO_L6P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V22 | | High Range | IO_L1N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V23 | | High Range | IO_L3P_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| V24 | | High Range | IO_L3N_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V26 | | High Range | IO_L4N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| W1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W3 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| W8 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| W9 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W10 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W11 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Performance | IO_25_VRP_32 | User IO | | 32 | | | | | | | | | | | | | | +| W14 | | High Performance | IO_L24N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W15 | | High Performance | IO_L22P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W16 | | High Performance | IO_L22N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W17 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| W18 | | High Performance | IO_L21P_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| W19 | | High Performance | IO_L21N_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L15P_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| W21 | | High Range | IO_L6N_T0_VREF_12 | User IO | | 12 | | | | | | | | | | | | | | +| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W23 | | High Range | IO_L8P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| W24 | | High Range | IO_L8N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| W25 | | High Range | IO_L5P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| W26 | | High Range | IO_L5N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| Y5 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y6 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y8 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y10 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y11 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y12 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y13 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y14 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| Y15 | | High Performance | IO_L9P_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y16 | | High Performance | IO_L9N_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y17 | | High Performance | IO_L19P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y18 | | High Performance | IO_L19N_T3_VREF_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y20 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y21 | | High Range | IO_L15N_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L13P_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y23 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y24 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| Y25 | | High Range | IO_L10P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y26 | | High Range | IO_L10N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb new file mode 100644 index 0000000..d81c0b8 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt new file mode 100644 index 0000000..831db44 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt @@ -0,0 +1,5188 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:58:37 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx +| Design : filter +| Device : xc7k160tffv676-1 +| Speed File : -1 +| Design State : Fully Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 856 ++-----------+----------+------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------------------------+------------+ +| TIMING-16 | Warning | Large setup violation | 420 | +| XDCH-2 | Warning | Same min and max delay values on IO port | 436 | ++-----------+----------+------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-16#1 Warning +Large setup violation +There is a large setup violation of -1.008 ns between registered_config.cfg_item_reg[5]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRARDADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#2 Warning +Large setup violation +There is a large setup violation of -1.058 ns between registered_config.cfg_item_reg[8]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRARDADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#3 Warning +Large setup violation +There is a large setup violation of -1.090 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRARDADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#4 Warning +Large setup violation +There is a large setup violation of -1.093 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRARDADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#5 Warning +Large setup violation +There is a large setup violation of -1.098 ns between registered_config.cfg_item_reg[6]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRARDADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#6 Warning +Large setup violation +There is a large setup violation of -1.391 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRARDADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#7 Warning +Large setup violation +There is a large setup violation of -1.689 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRARDADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#8 Warning +Large setup violation +There is a large setup violation of -16.019 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#9 Warning +Large setup violation +There is a large setup violation of -16.078 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#10 Warning +Large setup violation +There is a large setup violation of -16.094 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#11 Warning +Large setup violation +There is a large setup violation of -16.121 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#12 Warning +Large setup violation +There is a large setup violation of -16.136 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#13 Warning +Large setup violation +There is a large setup violation of -16.158 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#14 Warning +Large setup violation +There is a large setup violation of -16.198 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#15 Warning +Large setup violation +There is a large setup violation of -16.239 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#16 Warning +Large setup violation +There is a large setup violation of -16.254 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#17 Warning +Large setup violation +There is a large setup violation of -16.258 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#18 Warning +Large setup violation +There is a large setup violation of -16.275 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#19 Warning +Large setup violation +There is a large setup violation of -16.281 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#20 Warning +Large setup violation +There is a large setup violation of -16.288 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#21 Warning +Large setup violation +There is a large setup violation of -16.299 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#22 Warning +Large setup violation +There is a large setup violation of -16.302 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#23 Warning +Large setup violation +There is a large setup violation of -16.316 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#24 Warning +Large setup violation +There is a large setup violation of -16.322 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#25 Warning +Large setup violation +There is a large setup violation of -16.332 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#26 Warning +Large setup violation +There is a large setup violation of -16.338 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#27 Warning +Large setup violation +There is a large setup violation of -16.358 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#28 Warning +Large setup violation +There is a large setup violation of -16.372 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#29 Warning +Large setup violation +There is a large setup violation of -16.385 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#30 Warning +Large setup violation +There is a large setup violation of -16.388 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#31 Warning +Large setup violation +There is a large setup violation of -16.411 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#32 Warning +Large setup violation +There is a large setup violation of -16.412 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#33 Warning +Large setup violation +There is a large setup violation of -16.413 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#34 Warning +Large setup violation +There is a large setup violation of -16.414 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#35 Warning +Large setup violation +There is a large setup violation of -16.419 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#36 Warning +Large setup violation +There is a large setup violation of -16.429 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#37 Warning +Large setup violation +There is a large setup violation of -16.447 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#38 Warning +Large setup violation +There is a large setup violation of -16.451 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#39 Warning +Large setup violation +There is a large setup violation of -16.463 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#40 Warning +Large setup violation +There is a large setup violation of -16.466 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#41 Warning +Large setup violation +There is a large setup violation of -16.468 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#42 Warning +Large setup violation +There is a large setup violation of -16.470 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#43 Warning +Large setup violation +There is a large setup violation of -16.475 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#44 Warning +Large setup violation +There is a large setup violation of -16.478 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#45 Warning +Large setup violation +There is a large setup violation of -16.485 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#46 Warning +Large setup violation +There is a large setup violation of -16.487 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#47 Warning +Large setup violation +There is a large setup violation of -16.488 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#48 Warning +Large setup violation +There is a large setup violation of -16.491 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#49 Warning +Large setup violation +There is a large setup violation of -16.492 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#50 Warning +Large setup violation +There is a large setup violation of -16.501 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#51 Warning +Large setup violation +There is a large setup violation of -16.503 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#52 Warning +Large setup violation +There is a large setup violation of -16.507 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#53 Warning +Large setup violation +There is a large setup violation of -16.511 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#54 Warning +Large setup violation +There is a large setup violation of -16.513 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#55 Warning +Large setup violation +There is a large setup violation of -16.527 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#56 Warning +Large setup violation +There is a large setup violation of -16.528 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#57 Warning +Large setup violation +There is a large setup violation of -16.528 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#58 Warning +Large setup violation +There is a large setup violation of -16.528 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#59 Warning +Large setup violation +There is a large setup violation of -16.533 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#60 Warning +Large setup violation +There is a large setup violation of -16.535 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#61 Warning +Large setup violation +There is a large setup violation of -16.536 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#62 Warning +Large setup violation +There is a large setup violation of -16.544 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#63 Warning +Large setup violation +There is a large setup violation of -16.544 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#64 Warning +Large setup violation +There is a large setup violation of -16.548 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#65 Warning +Large setup violation +There is a large setup violation of -16.550 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#66 Warning +Large setup violation +There is a large setup violation of -16.551 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#67 Warning +Large setup violation +There is a large setup violation of -16.558 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#68 Warning +Large setup violation +There is a large setup violation of -16.558 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#69 Warning +Large setup violation +There is a large setup violation of -16.561 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#70 Warning +Large setup violation +There is a large setup violation of -16.563 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#71 Warning +Large setup violation +There is a large setup violation of -16.564 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#72 Warning +Large setup violation +There is a large setup violation of -16.564 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#73 Warning +Large setup violation +There is a large setup violation of -16.566 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#74 Warning +Large setup violation +There is a large setup violation of -16.570 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#75 Warning +Large setup violation +There is a large setup violation of -16.572 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#76 Warning +Large setup violation +There is a large setup violation of -16.578 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#77 Warning +Large setup violation +There is a large setup violation of -16.580 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#78 Warning +Large setup violation +There is a large setup violation of -16.582 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#79 Warning +Large setup violation +There is a large setup violation of -16.597 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#80 Warning +Large setup violation +There is a large setup violation of -16.597 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#81 Warning +Large setup violation +There is a large setup violation of -16.604 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#82 Warning +Large setup violation +There is a large setup violation of -16.606 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#83 Warning +Large setup violation +There is a large setup violation of -16.607 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#84 Warning +Large setup violation +There is a large setup violation of -16.610 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#85 Warning +Large setup violation +There is a large setup violation of -16.614 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#86 Warning +Large setup violation +There is a large setup violation of -16.618 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#87 Warning +Large setup violation +There is a large setup violation of -16.619 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#88 Warning +Large setup violation +There is a large setup violation of -16.619 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#89 Warning +Large setup violation +There is a large setup violation of -16.621 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#90 Warning +Large setup violation +There is a large setup violation of -16.622 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#91 Warning +Large setup violation +There is a large setup violation of -16.624 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#92 Warning +Large setup violation +There is a large setup violation of -16.624 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#93 Warning +Large setup violation +There is a large setup violation of -16.632 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#94 Warning +Large setup violation +There is a large setup violation of -16.632 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#95 Warning +Large setup violation +There is a large setup violation of -16.633 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#96 Warning +Large setup violation +There is a large setup violation of -16.636 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#97 Warning +Large setup violation +There is a large setup violation of -16.638 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#98 Warning +Large setup violation +There is a large setup violation of -16.643 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#99 Warning +Large setup violation +There is a large setup violation of -16.643 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#100 Warning +Large setup violation +There is a large setup violation of -16.645 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#101 Warning +Large setup violation +There is a large setup violation of -16.648 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#102 Warning +Large setup violation +There is a large setup violation of -16.653 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#103 Warning +Large setup violation +There is a large setup violation of -16.659 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#104 Warning +Large setup violation +There is a large setup violation of -16.663 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#105 Warning +Large setup violation +There is a large setup violation of -16.665 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#106 Warning +Large setup violation +There is a large setup violation of -16.666 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#107 Warning +Large setup violation +There is a large setup violation of -16.668 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#108 Warning +Large setup violation +There is a large setup violation of -16.675 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#109 Warning +Large setup violation +There is a large setup violation of -16.677 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#110 Warning +Large setup violation +There is a large setup violation of -16.678 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#111 Warning +Large setup violation +There is a large setup violation of -16.679 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#112 Warning +Large setup violation +There is a large setup violation of -16.679 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#113 Warning +Large setup violation +There is a large setup violation of -16.680 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#114 Warning +Large setup violation +There is a large setup violation of -16.680 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#115 Warning +Large setup violation +There is a large setup violation of -16.682 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#116 Warning +Large setup violation +There is a large setup violation of -16.682 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#117 Warning +Large setup violation +There is a large setup violation of -16.685 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#118 Warning +Large setup violation +There is a large setup violation of -16.685 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#119 Warning +Large setup violation +There is a large setup violation of -16.686 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#120 Warning +Large setup violation +There is a large setup violation of -16.688 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#121 Warning +Large setup violation +There is a large setup violation of -16.689 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#122 Warning +Large setup violation +There is a large setup violation of -16.691 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#123 Warning +Large setup violation +There is a large setup violation of -16.693 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#124 Warning +Large setup violation +There is a large setup violation of -16.697 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#125 Warning +Large setup violation +There is a large setup violation of -16.698 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#126 Warning +Large setup violation +There is a large setup violation of -16.700 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#127 Warning +Large setup violation +There is a large setup violation of -16.702 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#128 Warning +Large setup violation +There is a large setup violation of -16.705 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#129 Warning +Large setup violation +There is a large setup violation of -16.707 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#130 Warning +Large setup violation +There is a large setup violation of -16.708 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#131 Warning +Large setup violation +There is a large setup violation of -16.713 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#132 Warning +Large setup violation +There is a large setup violation of -16.714 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#133 Warning +Large setup violation +There is a large setup violation of -16.715 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#134 Warning +Large setup violation +There is a large setup violation of -16.716 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#135 Warning +Large setup violation +There is a large setup violation of -16.719 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#136 Warning +Large setup violation +There is a large setup violation of -16.720 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#137 Warning +Large setup violation +There is a large setup violation of -16.725 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#138 Warning +Large setup violation +There is a large setup violation of -16.732 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#139 Warning +Large setup violation +There is a large setup violation of -16.744 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#140 Warning +Large setup violation +There is a large setup violation of -16.747 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#141 Warning +Large setup violation +There is a large setup violation of -16.749 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#142 Warning +Large setup violation +There is a large setup violation of -16.751 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#143 Warning +Large setup violation +There is a large setup violation of -16.753 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#144 Warning +Large setup violation +There is a large setup violation of -16.757 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#145 Warning +Large setup violation +There is a large setup violation of -16.758 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#146 Warning +Large setup violation +There is a large setup violation of -16.759 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#147 Warning +Large setup violation +There is a large setup violation of -16.759 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#148 Warning +Large setup violation +There is a large setup violation of -16.760 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#149 Warning +Large setup violation +There is a large setup violation of -16.762 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#150 Warning +Large setup violation +There is a large setup violation of -16.765 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#151 Warning +Large setup violation +There is a large setup violation of -16.767 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#152 Warning +Large setup violation +There is a large setup violation of -16.767 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#153 Warning +Large setup violation +There is a large setup violation of -16.771 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#154 Warning +Large setup violation +There is a large setup violation of -16.771 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#155 Warning +Large setup violation +There is a large setup violation of -16.771 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#156 Warning +Large setup violation +There is a large setup violation of -16.774 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#157 Warning +Large setup violation +There is a large setup violation of -16.774 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#158 Warning +Large setup violation +There is a large setup violation of -16.774 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#159 Warning +Large setup violation +There is a large setup violation of -16.776 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#160 Warning +Large setup violation +There is a large setup violation of -16.777 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#161 Warning +Large setup violation +There is a large setup violation of -16.781 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#162 Warning +Large setup violation +There is a large setup violation of -16.785 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#163 Warning +Large setup violation +There is a large setup violation of -16.786 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#164 Warning +Large setup violation +There is a large setup violation of -16.787 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#165 Warning +Large setup violation +There is a large setup violation of -16.788 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#166 Warning +Large setup violation +There is a large setup violation of -16.789 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#167 Warning +Large setup violation +There is a large setup violation of -16.789 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#168 Warning +Large setup violation +There is a large setup violation of -16.790 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#169 Warning +Large setup violation +There is a large setup violation of -16.792 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#170 Warning +Large setup violation +There is a large setup violation of -16.793 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#171 Warning +Large setup violation +There is a large setup violation of -16.793 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#172 Warning +Large setup violation +There is a large setup violation of -16.795 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#173 Warning +Large setup violation +There is a large setup violation of -16.796 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#174 Warning +Large setup violation +There is a large setup violation of -16.804 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#175 Warning +Large setup violation +There is a large setup violation of -16.807 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#176 Warning +Large setup violation +There is a large setup violation of -16.807 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#177 Warning +Large setup violation +There is a large setup violation of -16.807 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#178 Warning +Large setup violation +There is a large setup violation of -16.809 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#179 Warning +Large setup violation +There is a large setup violation of -16.810 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#180 Warning +Large setup violation +There is a large setup violation of -16.811 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#181 Warning +Large setup violation +There is a large setup violation of -16.814 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#182 Warning +Large setup violation +There is a large setup violation of -16.815 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#183 Warning +Large setup violation +There is a large setup violation of -16.816 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#184 Warning +Large setup violation +There is a large setup violation of -16.818 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#185 Warning +Large setup violation +There is a large setup violation of -16.820 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#186 Warning +Large setup violation +There is a large setup violation of -16.822 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#187 Warning +Large setup violation +There is a large setup violation of -16.822 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#188 Warning +Large setup violation +There is a large setup violation of -16.824 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#189 Warning +Large setup violation +There is a large setup violation of -16.827 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#190 Warning +Large setup violation +There is a large setup violation of -16.830 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#191 Warning +Large setup violation +There is a large setup violation of -16.830 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#192 Warning +Large setup violation +There is a large setup violation of -16.833 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#193 Warning +Large setup violation +There is a large setup violation of -16.835 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#194 Warning +Large setup violation +There is a large setup violation of -16.836 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#195 Warning +Large setup violation +There is a large setup violation of -16.838 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#196 Warning +Large setup violation +There is a large setup violation of -16.842 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#197 Warning +Large setup violation +There is a large setup violation of -16.844 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#198 Warning +Large setup violation +There is a large setup violation of -16.847 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#199 Warning +Large setup violation +There is a large setup violation of -16.847 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#200 Warning +Large setup violation +There is a large setup violation of -16.847 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#201 Warning +Large setup violation +There is a large setup violation of -16.851 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#202 Warning +Large setup violation +There is a large setup violation of -16.862 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#203 Warning +Large setup violation +There is a large setup violation of -16.867 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#204 Warning +Large setup violation +There is a large setup violation of -16.869 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#205 Warning +Large setup violation +There is a large setup violation of -16.871 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#206 Warning +Large setup violation +There is a large setup violation of -16.875 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#207 Warning +Large setup violation +There is a large setup violation of -16.879 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#208 Warning +Large setup violation +There is a large setup violation of -16.881 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#209 Warning +Large setup violation +There is a large setup violation of -16.888 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#210 Warning +Large setup violation +There is a large setup violation of -16.892 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#211 Warning +Large setup violation +There is a large setup violation of -16.897 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#212 Warning +Large setup violation +There is a large setup violation of -16.898 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#213 Warning +Large setup violation +There is a large setup violation of -16.903 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#214 Warning +Large setup violation +There is a large setup violation of -16.906 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#215 Warning +Large setup violation +There is a large setup violation of -16.908 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#216 Warning +Large setup violation +There is a large setup violation of -16.915 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#217 Warning +Large setup violation +There is a large setup violation of -16.917 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#218 Warning +Large setup violation +There is a large setup violation of -16.918 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#219 Warning +Large setup violation +There is a large setup violation of -16.918 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#220 Warning +Large setup violation +There is a large setup violation of -16.920 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#221 Warning +Large setup violation +There is a large setup violation of -16.930 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#222 Warning +Large setup violation +There is a large setup violation of -16.930 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#223 Warning +Large setup violation +There is a large setup violation of -16.933 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#224 Warning +Large setup violation +There is a large setup violation of -16.935 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#225 Warning +Large setup violation +There is a large setup violation of -16.935 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#226 Warning +Large setup violation +There is a large setup violation of -16.936 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#227 Warning +Large setup violation +There is a large setup violation of -16.945 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#228 Warning +Large setup violation +There is a large setup violation of -16.946 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#229 Warning +Large setup violation +There is a large setup violation of -16.948 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#230 Warning +Large setup violation +There is a large setup violation of -16.949 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#231 Warning +Large setup violation +There is a large setup violation of -16.950 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#232 Warning +Large setup violation +There is a large setup violation of -16.951 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#233 Warning +Large setup violation +There is a large setup violation of -16.953 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#234 Warning +Large setup violation +There is a large setup violation of -16.954 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#235 Warning +Large setup violation +There is a large setup violation of -16.955 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#236 Warning +Large setup violation +There is a large setup violation of -16.956 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#237 Warning +Large setup violation +There is a large setup violation of -16.957 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#238 Warning +Large setup violation +There is a large setup violation of -16.958 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#239 Warning +Large setup violation +There is a large setup violation of -16.960 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#240 Warning +Large setup violation +There is a large setup violation of -16.964 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#241 Warning +Large setup violation +There is a large setup violation of -16.965 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#242 Warning +Large setup violation +There is a large setup violation of -16.966 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#243 Warning +Large setup violation +There is a large setup violation of -16.969 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#244 Warning +Large setup violation +There is a large setup violation of -16.969 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#245 Warning +Large setup violation +There is a large setup violation of -16.969 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#246 Warning +Large setup violation +There is a large setup violation of -16.970 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#247 Warning +Large setup violation +There is a large setup violation of -16.972 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#248 Warning +Large setup violation +There is a large setup violation of -16.973 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#249 Warning +Large setup violation +There is a large setup violation of -16.975 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#250 Warning +Large setup violation +There is a large setup violation of -16.983 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#251 Warning +Large setup violation +There is a large setup violation of -16.984 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#252 Warning +Large setup violation +There is a large setup violation of -16.985 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#253 Warning +Large setup violation +There is a large setup violation of -16.986 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#254 Warning +Large setup violation +There is a large setup violation of -16.986 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#255 Warning +Large setup violation +There is a large setup violation of -16.986 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#256 Warning +Large setup violation +There is a large setup violation of -16.988 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#257 Warning +Large setup violation +There is a large setup violation of -16.989 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#258 Warning +Large setup violation +There is a large setup violation of -16.994 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#259 Warning +Large setup violation +There is a large setup violation of -16.996 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#260 Warning +Large setup violation +There is a large setup violation of -16.996 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#261 Warning +Large setup violation +There is a large setup violation of -17.002 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#262 Warning +Large setup violation +There is a large setup violation of -17.008 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#263 Warning +Large setup violation +There is a large setup violation of -17.009 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#264 Warning +Large setup violation +There is a large setup violation of -17.014 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#265 Warning +Large setup violation +There is a large setup violation of -17.014 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#266 Warning +Large setup violation +There is a large setup violation of -17.014 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#267 Warning +Large setup violation +There is a large setup violation of -17.015 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#268 Warning +Large setup violation +There is a large setup violation of -17.016 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#269 Warning +Large setup violation +There is a large setup violation of -17.017 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#270 Warning +Large setup violation +There is a large setup violation of -17.017 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#271 Warning +Large setup violation +There is a large setup violation of -17.017 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#272 Warning +Large setup violation +There is a large setup violation of -17.022 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#273 Warning +Large setup violation +There is a large setup violation of -17.023 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#274 Warning +Large setup violation +There is a large setup violation of -17.025 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#275 Warning +Large setup violation +There is a large setup violation of -17.033 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#276 Warning +Large setup violation +There is a large setup violation of -17.033 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#277 Warning +Large setup violation +There is a large setup violation of -17.034 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#278 Warning +Large setup violation +There is a large setup violation of -17.035 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#279 Warning +Large setup violation +There is a large setup violation of -17.044 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#280 Warning +Large setup violation +There is a large setup violation of -17.054 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#281 Warning +Large setup violation +There is a large setup violation of -17.056 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#282 Warning +Large setup violation +There is a large setup violation of -17.058 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#283 Warning +Large setup violation +There is a large setup violation of -17.060 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#284 Warning +Large setup violation +There is a large setup violation of -17.060 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#285 Warning +Large setup violation +There is a large setup violation of -17.061 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#286 Warning +Large setup violation +There is a large setup violation of -17.062 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#287 Warning +Large setup violation +There is a large setup violation of -17.063 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#288 Warning +Large setup violation +There is a large setup violation of -17.063 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#289 Warning +Large setup violation +There is a large setup violation of -17.065 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#290 Warning +Large setup violation +There is a large setup violation of -17.067 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#291 Warning +Large setup violation +There is a large setup violation of -17.068 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#292 Warning +Large setup violation +There is a large setup violation of -17.070 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#293 Warning +Large setup violation +There is a large setup violation of -17.074 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#294 Warning +Large setup violation +There is a large setup violation of -17.076 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#295 Warning +Large setup violation +There is a large setup violation of -17.076 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#296 Warning +Large setup violation +There is a large setup violation of -17.076 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#297 Warning +Large setup violation +There is a large setup violation of -17.078 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#298 Warning +Large setup violation +There is a large setup violation of -17.078 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#299 Warning +Large setup violation +There is a large setup violation of -17.079 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#300 Warning +Large setup violation +There is a large setup violation of -17.081 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#301 Warning +Large setup violation +There is a large setup violation of -17.081 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#302 Warning +Large setup violation +There is a large setup violation of -17.082 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#303 Warning +Large setup violation +There is a large setup violation of -17.083 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#304 Warning +Large setup violation +There is a large setup violation of -17.083 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#305 Warning +Large setup violation +There is a large setup violation of -17.083 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#306 Warning +Large setup violation +There is a large setup violation of -17.087 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#307 Warning +Large setup violation +There is a large setup violation of -17.089 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#308 Warning +Large setup violation +There is a large setup violation of -17.091 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#309 Warning +Large setup violation +There is a large setup violation of -17.093 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#310 Warning +Large setup violation +There is a large setup violation of -17.094 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#311 Warning +Large setup violation +There is a large setup violation of -17.094 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#312 Warning +Large setup violation +There is a large setup violation of -17.095 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#313 Warning +Large setup violation +There is a large setup violation of -17.097 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#314 Warning +Large setup violation +There is a large setup violation of -17.097 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#315 Warning +Large setup violation +There is a large setup violation of -17.099 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#316 Warning +Large setup violation +There is a large setup violation of -17.105 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#317 Warning +Large setup violation +There is a large setup violation of -17.107 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#318 Warning +Large setup violation +There is a large setup violation of -17.108 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#319 Warning +Large setup violation +There is a large setup violation of -17.110 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#320 Warning +Large setup violation +There is a large setup violation of -17.110 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#321 Warning +Large setup violation +There is a large setup violation of -17.111 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#322 Warning +Large setup violation +There is a large setup violation of -17.112 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#323 Warning +Large setup violation +There is a large setup violation of -17.114 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#324 Warning +Large setup violation +There is a large setup violation of -17.118 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#325 Warning +Large setup violation +There is a large setup violation of -17.123 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#326 Warning +Large setup violation +There is a large setup violation of -17.123 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#327 Warning +Large setup violation +There is a large setup violation of -17.124 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#328 Warning +Large setup violation +There is a large setup violation of -17.128 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#329 Warning +Large setup violation +There is a large setup violation of -17.131 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#330 Warning +Large setup violation +There is a large setup violation of -17.131 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#331 Warning +Large setup violation +There is a large setup violation of -17.132 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#332 Warning +Large setup violation +There is a large setup violation of -17.134 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#333 Warning +Large setup violation +There is a large setup violation of -17.136 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#334 Warning +Large setup violation +There is a large setup violation of -17.136 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#335 Warning +Large setup violation +There is a large setup violation of -17.144 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#336 Warning +Large setup violation +There is a large setup violation of -17.148 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#337 Warning +Large setup violation +There is a large setup violation of -17.149 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#338 Warning +Large setup violation +There is a large setup violation of -17.149 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#339 Warning +Large setup violation +There is a large setup violation of -17.150 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#340 Warning +Large setup violation +There is a large setup violation of -17.152 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#341 Warning +Large setup violation +There is a large setup violation of -17.152 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#342 Warning +Large setup violation +There is a large setup violation of -17.153 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#343 Warning +Large setup violation +There is a large setup violation of -17.155 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#344 Warning +Large setup violation +There is a large setup violation of -17.158 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#345 Warning +Large setup violation +There is a large setup violation of -17.158 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#346 Warning +Large setup violation +There is a large setup violation of -17.159 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#347 Warning +Large setup violation +There is a large setup violation of -17.162 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#348 Warning +Large setup violation +There is a large setup violation of -17.162 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#349 Warning +Large setup violation +There is a large setup violation of -17.163 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#350 Warning +Large setup violation +There is a large setup violation of -17.164 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#351 Warning +Large setup violation +There is a large setup violation of -17.165 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#352 Warning +Large setup violation +There is a large setup violation of -17.166 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#353 Warning +Large setup violation +There is a large setup violation of -17.170 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#354 Warning +Large setup violation +There is a large setup violation of -17.173 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#355 Warning +Large setup violation +There is a large setup violation of -17.176 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#356 Warning +Large setup violation +There is a large setup violation of -17.178 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#357 Warning +Large setup violation +There is a large setup violation of -17.183 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#358 Warning +Large setup violation +There is a large setup violation of -17.186 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#359 Warning +Large setup violation +There is a large setup violation of -17.186 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#360 Warning +Large setup violation +There is a large setup violation of -17.187 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#361 Warning +Large setup violation +There is a large setup violation of -17.190 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#362 Warning +Large setup violation +There is a large setup violation of -17.192 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#363 Warning +Large setup violation +There is a large setup violation of -17.199 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#364 Warning +Large setup violation +There is a large setup violation of -17.202 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#365 Warning +Large setup violation +There is a large setup violation of -17.203 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#366 Warning +Large setup violation +There is a large setup violation of -17.208 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#367 Warning +Large setup violation +There is a large setup violation of -17.211 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#368 Warning +Large setup violation +There is a large setup violation of -17.212 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#369 Warning +Large setup violation +There is a large setup violation of -17.213 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#370 Warning +Large setup violation +There is a large setup violation of -17.213 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#371 Warning +Large setup violation +There is a large setup violation of -17.214 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#372 Warning +Large setup violation +There is a large setup violation of -17.214 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#373 Warning +Large setup violation +There is a large setup violation of -17.214 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#374 Warning +Large setup violation +There is a large setup violation of -17.215 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#375 Warning +Large setup violation +There is a large setup violation of -17.216 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#376 Warning +Large setup violation +There is a large setup violation of -17.218 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#377 Warning +Large setup violation +There is a large setup violation of -17.219 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#378 Warning +Large setup violation +There is a large setup violation of -17.226 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#379 Warning +Large setup violation +There is a large setup violation of -17.226 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#380 Warning +Large setup violation +There is a large setup violation of -17.228 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#381 Warning +Large setup violation +There is a large setup violation of -17.233 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#382 Warning +Large setup violation +There is a large setup violation of -17.235 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#383 Warning +Large setup violation +There is a large setup violation of -17.241 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#384 Warning +Large setup violation +There is a large setup violation of -17.245 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#385 Warning +Large setup violation +There is a large setup violation of -17.250 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#386 Warning +Large setup violation +There is a large setup violation of -17.258 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#387 Warning +Large setup violation +There is a large setup violation of -17.265 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#388 Warning +Large setup violation +There is a large setup violation of -17.273 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#389 Warning +Large setup violation +There is a large setup violation of -17.282 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#390 Warning +Large setup violation +There is a large setup violation of -17.283 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#391 Warning +Large setup violation +There is a large setup violation of -17.288 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#392 Warning +Large setup violation +There is a large setup violation of -17.290 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#393 Warning +Large setup violation +There is a large setup violation of -17.291 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#394 Warning +Large setup violation +There is a large setup violation of -17.298 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#395 Warning +Large setup violation +There is a large setup violation of -17.309 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#396 Warning +Large setup violation +There is a large setup violation of -17.310 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#397 Warning +Large setup violation +There is a large setup violation of -17.330 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#398 Warning +Large setup violation +There is a large setup violation of -17.331 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#399 Warning +Large setup violation +There is a large setup violation of -17.335 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#400 Warning +Large setup violation +There is a large setup violation of -17.342 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#401 Warning +Large setup violation +There is a large setup violation of -17.363 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#402 Warning +Large setup violation +There is a large setup violation of -17.364 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#403 Warning +Large setup violation +There is a large setup violation of -17.396 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#404 Warning +Large setup violation +There is a large setup violation of -2.635 ns between storage_generate[3].storage/memory_reg_4/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_KEY_FOUND_reg/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#405 Warning +Large setup violation +There is a large setup violation of -3.138 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[4]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#406 Warning +Large setup violation +There is a large setup violation of -3.260 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[10]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#407 Warning +Large setup violation +There is a large setup violation of -3.277 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[12]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#408 Warning +Large setup violation +There is a large setup violation of -3.324 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[3]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#409 Warning +Large setup violation +There is a large setup violation of -3.340 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[7]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#410 Warning +Large setup violation +There is a large setup violation of -3.352 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[15]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#411 Warning +Large setup violation +There is a large setup violation of -3.354 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[13]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#412 Warning +Large setup violation +There is a large setup violation of -3.511 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[1]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#413 Warning +Large setup violation +There is a large setup violation of -3.513 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[5]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#414 Warning +Large setup violation +There is a large setup violation of -3.520 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[9]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#415 Warning +Large setup violation +There is a large setup violation of -3.533 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[11]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#416 Warning +Large setup violation +There is a large setup violation of -3.554 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[0]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#417 Warning +Large setup violation +There is a large setup violation of -3.592 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[8]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#418 Warning +Large setup violation +There is a large setup violation of -3.609 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[14]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#419 Warning +Large setup violation +There is a large setup violation of -3.810 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[2]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#420 Warning +Large setup violation +There is a large setup violation of -3.961 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[6]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +XDCH-2#1 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CLK' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#2 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#3 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[10]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#4 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#5 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[2]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#6 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[3]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#7 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[4]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#8 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[5]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#9 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[6]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#10 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[7]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#11 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[8]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#12 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_ITEM[9]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#13 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_TABLE[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#14 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_ADDRESS_TABLE[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#15 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#16 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[10]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#17 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[11]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#18 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[12]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#19 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[13]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#20 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[14]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#21 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[15]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#22 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#23 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[2]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#24 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[3]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#25 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[4]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#26 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[5]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#27 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[6]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#28 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[7]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#29 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[8]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#30 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_DATA[9]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#31 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_EMPTY' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#32 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#33 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[100]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#34 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[101]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#35 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[102]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#36 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[103]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#37 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[104]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#38 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[105]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#39 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[106]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#40 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[107]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#41 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[108]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#42 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[109]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#43 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[10]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#44 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[110]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#45 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[111]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#46 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[112]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#47 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[113]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#48 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[114]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#49 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[115]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#50 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[116]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#51 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[117]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#52 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[118]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#53 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[119]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#54 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[11]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#55 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[120]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#56 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[121]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#57 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[122]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#58 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[123]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#59 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[124]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#60 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[125]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#61 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[126]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#62 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[127]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#63 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[12]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#64 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[13]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#65 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[14]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#66 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[15]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#67 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[16]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#68 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[17]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#69 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[18]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#70 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[19]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#71 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#72 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[20]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#73 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[21]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#74 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[22]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#75 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[23]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#76 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[24]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#77 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[25]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#78 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[26]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#79 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[27]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#80 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[28]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#81 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[29]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#82 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[2]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#83 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[30]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#84 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[31]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#85 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[32]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#86 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[33]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#87 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[34]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#88 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[35]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#89 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[36]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#90 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[37]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#91 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[38]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#92 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[39]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#93 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[3]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#94 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[40]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#95 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[41]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#96 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[42]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#97 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[43]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#98 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[44]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#99 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[45]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#100 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[46]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#101 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[47]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#102 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[48]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#103 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[49]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#104 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[4]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#105 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[50]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#106 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[51]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#107 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[52]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#108 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[53]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#109 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[54]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#110 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[55]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#111 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[56]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#112 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[57]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#113 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[58]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#114 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[59]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#115 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[5]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#116 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[60]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#117 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[61]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#118 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[62]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#119 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[63]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#120 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[64]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#121 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[65]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#122 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[66]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#123 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[67]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#124 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[68]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#125 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[69]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#126 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[6]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#127 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[70]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#128 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[71]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#129 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[72]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#130 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[73]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#131 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[74]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#132 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[75]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#133 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[76]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#134 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[77]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#135 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[78]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#136 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[79]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#137 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[7]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#138 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[80]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#139 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[81]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#140 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[82]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#141 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[83]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#142 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[84]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#143 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[85]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#144 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[86]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#145 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[87]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#146 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[88]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#147 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[89]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#148 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[8]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#149 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[90]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#150 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[91]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#151 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[92]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#152 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[93]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#153 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[94]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#154 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[95]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#155 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[96]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#156 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[97]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#157 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[98]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#158 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[99]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#159 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_KEY[9]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#160 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'CONFIG_WRITE' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#161 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#162 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[100]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#163 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[101]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#164 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[102]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#165 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[103]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#166 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[104]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#167 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[105]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#168 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[106]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#169 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[107]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#170 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[108]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#171 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[109]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#172 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[10]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#173 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[110]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#174 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[111]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#175 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[112]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#176 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[113]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#177 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[114]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#178 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[115]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#179 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[116]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#180 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[117]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#181 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[118]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#182 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[119]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#183 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[11]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#184 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[120]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#185 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[121]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#186 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[122]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#187 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[123]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#188 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[124]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#189 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[125]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#190 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[126]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#191 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[127]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#192 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[12]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#193 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[13]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#194 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[14]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#195 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[15]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#196 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[16]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#197 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[17]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#198 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[18]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#199 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[19]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#200 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#201 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[20]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#202 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[21]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#203 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[22]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#204 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[23]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#205 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[24]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#206 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[25]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#207 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[26]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#208 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[27]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#209 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[28]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#210 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[29]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#211 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[2]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#212 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[30]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#213 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[31]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#214 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[32]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#215 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[33]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#216 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[34]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#217 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[35]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#218 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[36]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#219 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[37]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#220 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[38]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#221 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[39]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#222 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[3]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#223 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[40]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#224 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[41]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#225 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[42]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#226 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[43]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#227 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[44]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#228 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[45]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#229 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[46]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#230 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[47]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#231 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[48]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#232 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[49]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#233 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[4]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#234 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[50]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#235 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[51]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#236 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[52]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#237 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[53]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#238 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[54]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#239 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[55]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#240 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[56]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#241 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[57]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#242 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[58]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#243 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[59]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#244 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[5]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#245 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[60]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#246 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[61]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#247 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[62]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#248 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[63]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#249 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[64]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#250 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[65]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#251 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[66]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#252 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[67]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#253 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[68]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#254 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[69]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#255 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[6]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#256 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[70]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#257 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[71]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#258 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[72]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#259 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[73]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#260 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[74]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#261 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[75]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#262 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[76]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#263 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[77]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#264 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[78]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#265 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[79]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#266 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[7]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#267 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[80]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#268 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[81]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#269 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[82]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#270 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[83]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#271 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[84]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#272 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[85]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#273 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[86]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#274 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[87]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#275 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[88]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#276 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[89]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#277 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[8]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#278 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[90]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#279 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[91]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#280 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[92]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#281 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[93]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#282 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[94]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#283 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[95]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#284 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[96]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#285 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[97]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#286 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[98]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#287 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[99]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#288 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_KEY[9]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#289 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'INPUT_VALID' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#290 Warning +Same min and max delay values on IO port +The same input delay of 1.000 ns has been defined on port 'RESET' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_input_delay -clock [get_clocks CLK] 1.000 [all_inputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 13) +Related violations: + +XDCH-2#291 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#292 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[10]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#293 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[11]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#294 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[12]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#295 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[13]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#296 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[14]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#297 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[15]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#298 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#299 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[2]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#300 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[3]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#301 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[4]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#302 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[5]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#303 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[6]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#304 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[7]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#305 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[8]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#306 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_DATA[9]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#307 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[0]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#308 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[100]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#309 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[101]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#310 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[102]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#311 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[103]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#312 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[104]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#313 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[105]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#314 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[106]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#315 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[107]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#316 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[108]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#317 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[109]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#318 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[10]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#319 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[110]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#320 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[111]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#321 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[112]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#322 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[113]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#323 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[114]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#324 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[115]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#325 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[116]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#326 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[117]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#327 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[118]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#328 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[119]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#329 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[11]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#330 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[120]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#331 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[121]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#332 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[122]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#333 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[123]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#334 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[124]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#335 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[125]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#336 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[126]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#337 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[127]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#338 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[12]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#339 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[13]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#340 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[14]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#341 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[15]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#342 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[16]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#343 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[17]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#344 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[18]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#345 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[19]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#346 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[1]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#347 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[20]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#348 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[21]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#349 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[22]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#350 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[23]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#351 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[24]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#352 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[25]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#353 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[26]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#354 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[27]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#355 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[28]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#356 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[29]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#357 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[2]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#358 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[30]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#359 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[31]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#360 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[32]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#361 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[33]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#362 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[34]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#363 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[35]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#364 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[36]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#365 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[37]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#366 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[38]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#367 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[39]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#368 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[3]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#369 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[40]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#370 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[41]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#371 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[42]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#372 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[43]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#373 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[44]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#374 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[45]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#375 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[46]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#376 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[47]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#377 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[48]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#378 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[49]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#379 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[4]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#380 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[50]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#381 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[51]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#382 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[52]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#383 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[53]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#384 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[54]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#385 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[55]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#386 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[56]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#387 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[57]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#388 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[58]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#389 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[59]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#390 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[5]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#391 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[60]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#392 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[61]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#393 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[62]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#394 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[63]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#395 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[64]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#396 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[65]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#397 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[66]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#398 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[67]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#399 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[68]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#400 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[69]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#401 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[6]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#402 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[70]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#403 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[71]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#404 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[72]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#405 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[73]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#406 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[74]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#407 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[75]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#408 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[76]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#409 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[77]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#410 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[78]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#411 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[79]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#412 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[7]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#413 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[80]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#414 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[81]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#415 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[82]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#416 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[83]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#417 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[84]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#418 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[85]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#419 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[86]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#420 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[87]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#421 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[88]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#422 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[89]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#423 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[8]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#424 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[90]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#425 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[91]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#426 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[92]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#427 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[93]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#428 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[94]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#429 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[95]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#430 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[96]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#431 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[97]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#432 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[98]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#433 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[99]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#434 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY[9]' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#435 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_KEY_FOUND' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + +XDCH-2#436 Warning +Same min and max delay values on IO port +The same output delay of 1.000 ns has been defined on port 'OUTPUT_VALID' relative to clock CLK for both max and min. Make sure this reflects the design intent. +set_output_delay -clock [get_clocks CLK] 1.000 [all_outputs] +/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc (Line: 14) +Related violations: + + diff --git a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx new file mode 100644 index 0000000..c0a455d Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_opt.dcp b/synth/filter_vivado.runs/impl_1/filter_opt.dcp new file mode 100644 index 0000000..1e8c71e Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_opt.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_physopt.dcp b/synth/filter_vivado.runs/impl_1/filter_physopt.dcp new file mode 100644 index 0000000..aefe4f3 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_physopt.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_placed.dcp b/synth/filter_vivado.runs/impl_1/filter_placed.dcp new file mode 100644 index 0000000..a6f4539 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_placed.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt new file mode 100644 index 0000000..5b6ccba --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt @@ -0,0 +1,163 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:58:40 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx +| Design : filter +| Device : xc7k160tffv676-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.790 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.675 | +| Device Static (W) | 0.114 | +| Effective TJA (C/W) | 1.9 | +| Max Ambient (C) | 83.5 | +| Junction Temperature (C) | 26.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.024 | 3 | --- | --- | +| Slice Logic | 0.175 | 5524 | --- | --- | +| LUT as Logic | 0.163 | 3508 | 101400 | 3.46 | +| CARRY4 | 0.012 | 681 | 25350 | 2.69 | +| Register | <0.001 | 597 | 202800 | 0.29 | +| Others | 0.000 | 34 | --- | --- | +| Signals | 0.270 | 5168 | --- | --- | +| Block RAM | 0.206 | 34 | 325 | 10.46 | +| Static Power | 0.114 | | | | +| Total | 0.790 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.703 | 0.660 | 0.043 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.018 | 0.016 | 0.002 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | High | User specified more than 95% of inputs | | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 1.9 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 3.4 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| CLK | CLK | 4.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------------------------------+-----------+ +| Name | Power (W) | ++-------------------------------+-----------+ +| filter | 0.675 | +| hash_generate[0].hash | 0.100 | +| final | 0.023 | +| mix_pipeline[0].mix | 0.076 | +| hash_generate[1].hash | 0.105 | +| final | 0.023 | +| mix_pipeline[0].mix | 0.081 | +| hash_generate[2].hash | 0.101 | +| final | 0.022 | +| mix_pipeline[0].mix | 0.079 | +| hash_generate[3].hash | 0.102 | +| final | 0.024 | +| mix_pipeline[0].mix | 0.072 | +| storage_generate[0].storage | 0.057 | +| storage_generate[1].storage | 0.059 | +| storage_generate[2].storage | 0.057 | +| storage_generate[3].storage | 0.057 | ++-------------------------------+-----------+ + + diff --git a/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx new file mode 100644 index 0000000..d388c7c Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb b/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb new file mode 100644 index 0000000..653fd54 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_reports.tcl b/synth/filter_vivado.runs/impl_1/filter_reports.tcl new file mode 100644 index 0000000..296f467 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_reports.tcl @@ -0,0 +1,129 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +namespace eval ::optrace { + variable script "/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_reports.tcl" + variable category "vivado_impl" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } elseif { [info exist ::env(HOST)] } { + set host $::env(HOST) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +OPTRACE "impl_1" END { } +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +if {$argv == "opt_design"} { + set retval [open_checkpoint filter_opt.dcp] + if { $retval == "checkpoint_filter_opt" } { + create_report "impl_1_opt_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx" + + close_design + } +} + diff --git a/synth/filter_vivado.runs/impl_1/filter_route_status.pb b/synth/filter_vivado.runs/impl_1/filter_route_status.pb new file mode 100644 index 0000000..b57c662 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_route_status.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_route_status.rpt b/synth/filter_vivado.runs/impl_1/filter_route_status.rpt new file mode 100644 index 0000000..2bdcb2b --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_route_status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 8803 : + # of nets not needing routing.......... : 3633 : + # of internally routed nets........ : 3197 : + # of implicitly routed ports....... : 436 : + # of routable nets..................... : 5170 : + # of fully routed nets............. : 5170 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/synth/filter_vivado.runs/impl_1/filter_routed.dcp b/synth/filter_vivado.runs/impl_1/filter_routed.dcp new file mode 100644 index 0000000..fec1c74 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_routed.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb new file mode 100644 index 0000000..78fa794 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt new file mode 100644 index 0000000..3f03922 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt @@ -0,0 +1,2511 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 19:06:33 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx +| Design : filter +| Device : 7k160t-ffv676 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +| Design State : Optimized +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (0) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (0) +------------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + -14.185 -5464.168 413 2121 0.190 0.000 0 2121 1.505 0.000 0 635 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +CLK {0.000 2.000} 4.000 250.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +CLK -14.185 -5464.168 413 2121 0.190 0.000 0 2121 1.505 0.000 0 635 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: CLK + To Clock: CLK + +Setup : 413 Failing Endpoints, Worst Slack -14.185ns, Total Violation -5464.168ns +Hold : 0 Failing Endpoints, Worst Slack 0.190ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.505ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_3/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_3 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_4/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_4 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_5/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_5 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB36E1 r storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[2].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.185ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] + RAMB18E1 r storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB18E1 r storage_generate[2].storage/memory_reg_8/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.578 4.025 storage_generate[2].storage/memory_reg_8 + ------------------------------------------------------------------- + required time 4.025 + arrival time -18.210 + ------------------------------------------------------------------- + slack -14.185 + +Slack (VIOLATED) : -14.110ns (required time - arrival time) + Source: registered_input.in_key_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) + Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.672 0.672 CLK + FDRE r registered_input.in_key_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q + net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] + CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] + net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] + net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 + LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O + net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] + net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] + LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O + net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] + net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] + net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] + LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O + net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 + LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O + net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] + net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] + net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] + LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O + net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 + CARRY4 (Prop_carry4_S[1]_O[2]) + 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] + net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] + LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O + net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] + LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O + net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 + CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] + net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] + net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O + net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] + net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] + net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] + LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O + net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] + CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] + net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] + LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O + net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] + net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] + LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O + net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] + LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] + net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 + LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O + net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + CARRY4 (Prop_carry4_CI_O[0]) + 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] + net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] + RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) + -0.581 4.022 storage_generate[2].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.022 + arrival time -18.132 + ------------------------------------------------------------------- + slack -14.110 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[6]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[6]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[7]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[7]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[8]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[8]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[9]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[0]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[4] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[1]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[6] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[7] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[3]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + +Slack (MET) : 0.190ns (arrival time - required time) + Source: registered_config.cfg_item_reg[4]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.283 0.283 CLK + FDRE r registered_config.cfg_item_reg[4]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q + net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] + RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK + RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) + 0.145 0.443 storage_generate[0].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.443 + arrival time 0.633 + ------------------------------------------------------------------- + slack 0.190 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: CLK +Waveform(ns): { 0.000 2.000 } +Period(ns): 4.000 +Sources: { CLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_0/CLKARDCLK +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C + + + diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx new file mode 100644 index 0000000..4f75903 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb new file mode 100644 index 0000000..6525ab0 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt new file mode 100644 index 0000000..810d424 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt @@ -0,0 +1,2639 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:58:40 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation +| Design : filter +| Device : 7k160t-ffv676 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +Rule Severity Description Violations +--------- -------- ---------------------------------------- ---------- +TIMING-16 Warning Large setup violation 420 +XDCH-2 Warning Same min and max delay values on IO port 436 + +Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (0) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (0) +------------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + -17.396 -6762.482 465 2155 0.081 0.000 0 2155 1.505 0.000 0 669 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +CLK {0.000 2.000} 4.000 250.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +CLK -17.396 -6762.482 465 2155 0.081 0.000 0 2155 1.505 0.000 0 669 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: CLK + To Clock: CLK + +Setup : 465 Failing Endpoints, Worst Slack -17.396ns, Total Violation -6762.482ns +Hold : 0 Failing Endpoints, Worst Slack 0.081ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.505ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -17.396ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.749ns (logic 9.946ns (47.935%) route 10.803ns (52.065%)) + Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 20.502 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, routed) 0.919 21.421 storage_generate[1].storage/O76[9] + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.421 + ------------------------------------------------------------------- + slack -17.396 + +Slack (VIOLATED) : -17.364ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.727ns (logic 9.854ns (47.542%) route 10.873ns (52.458%)) + Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[3]) + 0.179 20.410 r hash_generate[1].hash/final/memory_reg_0_i_3/O[3] + net (fo=9, routed) 0.989 21.399 storage_generate[1].storage/O76[7] + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[11]) + -0.568 4.035 storage_generate[1].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.035 + arrival time -21.399 + ------------------------------------------------------------------- + slack -17.364 + +Slack (VIOLATED) : -17.363ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.716ns (logic 9.888ns (47.731%) route 10.828ns (52.269%)) + Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 20.444 r hash_generate[1].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, routed) 0.944 21.388 storage_generate[1].storage/O76[5] + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[1].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.388 + ------------------------------------------------------------------- + slack -17.363 + +Slack (VIOLATED) : -17.342ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.695ns (logic 9.869ns (47.688%) route 10.826ns (52.312%)) + Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[2]) + 0.136 20.425 r hash_generate[1].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, routed) 0.942 21.367 storage_generate[1].storage/O76[10] + RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y37 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[1].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.367 + ------------------------------------------------------------------- + slack -17.342 + +Slack (VIOLATED) : -17.335ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.688ns (logic 9.946ns (48.077%) route 10.742ns (51.923%)) + Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 20.502 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] + net (fo=9, routed) 0.858 21.360 storage_generate[1].storage/O76[9] + RAMB36_X2Y33 RAMB36E1 r storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y33 RAMB36E1 r storage_generate[1].storage/memory_reg_0/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y33 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) + -0.578 4.025 storage_generate[1].storage/memory_reg_0 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.360 + ------------------------------------------------------------------- + slack -17.335 + +Slack (VIOLATED) : -17.331ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.684ns (logic 9.869ns (47.714%) route 10.815ns (52.286%)) + Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 + SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[2]) + 0.136 20.425 r hash_generate[1].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, routed) 0.931 21.356 storage_generate[1].storage/O76[10] + RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X3Y36 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[1].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.356 + ------------------------------------------------------------------- + slack -17.331 + +Slack (VIOLATED) : -17.330ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.683ns (logic 9.888ns (47.807%) route 10.795ns (52.193%)) + Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 20.444 r hash_generate[1].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, routed) 0.911 21.355 storage_generate[1].storage/O76[5] + RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y37 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[1].storage/memory_reg_2 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.355 + ------------------------------------------------------------------- + slack -17.330 + +Slack (VIOLATED) : -17.310ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[10] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.663ns (logic 9.811ns (47.480%) route 10.852ns (52.520%)) + Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[2]) + 0.136 20.367 r hash_generate[1].hash/final/memory_reg_0_i_3/O[2] + net (fo=9, routed) 0.969 21.335 storage_generate[1].storage/O76[6] + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[10]) + -0.578 4.025 storage_generate[1].storage/memory_reg_1 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.335 + ------------------------------------------------------------------- + slack -17.310 + +Slack (VIOLATED) : -17.309ns (required time - arrival time) + Source: registered_input.in_key_reg[64]_replica_5/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.662ns (logic 9.888ns (47.855%) route 10.774ns (52.145%)) + Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q + net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias + SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] + net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 + SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] + net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 + SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O + net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 + SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] + net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 + SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] + net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] + SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O + net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 + SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] + net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] + SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O + net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 + SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] + net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 + SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] + net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] + SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O + net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 + SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] + net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 + SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] + net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] + SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O + net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] + SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O + net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 + SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] + net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 + SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] + net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] + SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O + net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 + SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] + net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 + SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) + 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] + net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] + SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O + net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] + SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] + net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 + SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] + net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] + SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O + net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 + SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] + net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 + SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] + net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 + SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] + net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 + SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] + net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] + SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O + net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 + SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 + SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] + SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O + net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 + SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 + SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 + SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 + SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 + SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 + SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 + SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 + SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] + SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O + net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 + SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 + SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 + SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 + SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 + SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 + SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] + net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 + SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] + net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 + SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O + net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] + net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 + SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] + net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 + SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O + net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 + SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] + net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 + SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 20.444 r hash_generate[1].hash/final/memory_reg_0_i_3/O[1] + net (fo=9, routed) 0.891 21.334 storage_generate[1].storage/O76[5] + RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK + RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X3Y36 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) + -0.578 4.025 storage_generate[1].storage/memory_reg_7 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.334 + ------------------------------------------------------------------- + slack -17.309 + +Slack (VIOLATED) : -17.298ns (required time - arrival time) + Source: registered_input.in_key_reg[65]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 20.651ns (logic 9.316ns (45.111%) route 11.335ns (54.889%)) + Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.672 0.672 CLK + SLICE_X40Y170 FDRE r registered_input.in_key_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y170 FDRE (Prop_fdre_C_Q) 0.308 0.980 r registered_input.in_key_reg[65]/Q + net (fo=4, routed) 0.474 1.454 hash_generate[2].hash/mix_pipeline[0].mix/Q[61] + SLICE_X40Y172 CARRY4 (Prop_carry4_DI[1]_O[2]) + 0.326 1.780 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_419__0/O[2] + net (fo=18, routed) 0.571 2.351 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_419__0_n_5 + SLICE_X43Y175 LUT2 (Prop_lut2_I1_O) 0.152 2.503 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_900__2/O + net (fo=1, routed) 0.000 2.503 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_900__2_n_0 + SLICE_X43Y175 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.235 2.738 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_594/CO[3] + net (fo=1, routed) 0.000 2.738 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_594_n_0 + SLICE_X43Y176 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 2.951 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/O[1] + net (fo=11, routed) 0.626 3.577 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[5] + SLICE_X47Y179 LUT3 (Prop_lut3_I1_O) 0.152 3.729 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_896__0/O + net (fo=1, routed) 0.000 3.729 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_896__0_n_0 + SLICE_X47Y179 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.053 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_593/CO[3] + net (fo=1, routed) 0.000 4.053 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_593_n_0 + SLICE_X47Y180 CARRY4 (Prop_carry4_CI_O[0]) + 0.139 4.192 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/O[0] + net (fo=9, routed) 0.578 4.771 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[8] + SLICE_X48Y180 LUT3 (Prop_lut3_I0_O) 0.155 4.926 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_682/O + net (fo=11, routed) 0.487 5.413 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[94] + SLICE_X49Y180 LUT6 (Prop_lut6_I0_O) 0.053 5.466 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O + net (fo=1, routed) 0.000 5.466 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 + SLICE_X49Y180 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.345 5.811 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_568/O[2] + net (fo=8, routed) 0.601 6.411 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[9] + SLICE_X50Y181 LUT5 (Prop_lut5_I4_O) 0.152 6.563 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_546__1/O + net (fo=1, routed) 0.000 6.563 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_546__1_n_0 + SLICE_X50Y181 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.219 6.782 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_306/CO[3] + net (fo=1, routed) 0.000 6.782 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_306_n_0 + SLICE_X50Y182 CARRY4 (Prop_carry4_CI_O[2]) + 0.137 6.919 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_291/O[2] + net (fo=5, routed) 0.402 7.322 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[13] + SLICE_X48Y180 LUT5 (Prop_lut5_I4_O) 0.152 7.474 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_298__1/O + net (fo=4, routed) 0.382 7.856 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_298__1_n_0 + SLICE_X53Y180 LUT5 (Prop_lut5_I4_O) 0.053 7.909 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1062__1/O + net (fo=1, routed) 0.778 8.687 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1062__1_n_0 + SLICE_X51Y183 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.230 8.917 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_741/CO[3] + net (fo=1, routed) 0.000 8.917 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0 + SLICE_X51Y184 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 9.130 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/O[1] + net (fo=4, routed) 0.734 9.864 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[17] + SLICE_X56Y185 LUT5 (Prop_lut5_I1_O) 0.152 10.016 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1147__1/O + net (fo=1, routed) 0.000 10.016 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1147__1_n_0 + SLICE_X56Y185 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.379 10.395 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1099/O[3] + net (fo=2, routed) 0.550 10.945 hash_generate[2].hash/final/minusOp1_out[19] + SLICE_X55Y185 LUT6 (Prop_lut6_I5_O) 0.142 11.087 r hash_generate[2].hash/final/memory_reg_0_i_829/O + net (fo=1, routed) 0.501 11.588 hash_generate[2].hash/final/L8_out[19] + SLICE_X54Y188 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.234 11.822 r hash_generate[2].hash/final/memory_reg_0_i_573/CO[3] + net (fo=1, routed) 0.000 11.822 hash_generate[2].hash/final/memory_reg_0_i_573_n_0 + SLICE_X54Y189 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 12.034 r hash_generate[2].hash/final/memory_reg_0_i_579/O[1] + net (fo=5, routed) 0.696 12.730 hash_generate[2].hash/final/minusOp12_out[21] + SLICE_X55Y186 LUT3 (Prop_lut3_I2_O) 0.155 12.885 r hash_generate[2].hash/final/memory_reg_0_i_444__0/O + net (fo=1, routed) 0.000 12.885 hash_generate[2].hash/final/memory_reg_0_i_444__0_n_0 + SLICE_X55Y186 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 13.198 r hash_generate[2].hash/final/memory_reg_0_i_281/CO[3] + net (fo=1, routed) 0.000 13.198 hash_generate[2].hash/final/memory_reg_0_i_281_n_0 + SLICE_X55Y187 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 13.256 r hash_generate[2].hash/final/memory_reg_0_i_286/CO[3] + net (fo=1, routed) 0.000 13.256 hash_generate[2].hash/final/memory_reg_0_i_286_n_0 + SLICE_X55Y188 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 13.469 r hash_generate[2].hash/final/memory_reg_0_i_256/O[1] + net (fo=5, routed) 0.695 14.164 hash_generate[2].hash/final/minusOp10_out_0[9] + SLICE_X52Y190 LUT3 (Prop_lut3_I1_O) 0.152 14.316 r hash_generate[2].hash/final/memory_reg_0_i_127__1/O + net (fo=1, routed) 0.000 14.316 hash_generate[2].hash/final/memory_reg_0_i_127__1_n_0 + SLICE_X52Y190 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 14.640 r hash_generate[2].hash/final/memory_reg_0_i_96/CO[3] + net (fo=1, routed) 0.000 14.640 hash_generate[2].hash/final/memory_reg_0_i_96_n_0 + SLICE_X52Y191 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 14.698 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] + net (fo=1, routed) 0.000 14.698 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 + SLICE_X52Y192 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 14.911 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] + net (fo=5, routed) 0.643 15.554 hash_generate[2].hash/final/minusOp8_out[17] + SLICE_X49Y189 LUT3 (Prop_lut3_I2_O) 0.152 15.706 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O + net (fo=1, routed) 0.000 15.706 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 + SLICE_X49Y189 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 16.030 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] + net (fo=1, routed) 0.000 16.030 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + SLICE_X49Y190 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 16.088 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] + net (fo=1, routed) 0.000 16.088 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + SLICE_X49Y191 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 16.146 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] + net (fo=1, routed) 0.000 16.146 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + SLICE_X49Y192 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 16.204 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] + net (fo=1, routed) 0.000 16.204 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + SLICE_X49Y193 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 16.262 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] + net (fo=1, routed) 0.000 16.262 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + SLICE_X49Y194 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 16.320 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] + net (fo=1, routed) 0.000 16.320 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + SLICE_X49Y195 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 16.378 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] + net (fo=1, routed) 0.000 16.378 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 + SLICE_X49Y196 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 16.591 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] + net (fo=3, routed) 0.582 17.172 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] + SLICE_X51Y192 LUT3 (Prop_lut3_I2_O) 0.152 17.324 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O + net (fo=1, routed) 0.000 17.324 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 + SLICE_X51Y192 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 17.648 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] + net (fo=1, routed) 0.000 17.648 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + SLICE_X51Y193 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.706 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] + net (fo=1, routed) 0.000 17.706 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + SLICE_X51Y194 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.764 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] + net (fo=1, routed) 0.000 17.764 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + SLICE_X51Y195 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.822 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] + net (fo=1, routed) 0.000 17.822 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 + SLICE_X51Y196 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 17.880 r hash_generate[2].hash/final/memory_reg_0_i_101/CO[3] + net (fo=1, routed) 0.000 17.880 hash_generate[2].hash/final/memory_reg_0_i_101_n_0 + SLICE_X51Y197 CARRY4 (Prop_carry4_CI_O[1]) + 0.213 18.093 r hash_generate[2].hash/final/memory_reg_0_i_106/O[1] + net (fo=1, routed) 0.426 18.519 hash_generate[2].hash/final/memory_reg_0_i_106_n_6 + SLICE_X50Y194 LUT3 (Prop_lut3_I2_O) 0.152 18.671 r hash_generate[2].hash/final/memory_reg_0_i_83__1/O + net (fo=1, routed) 0.000 18.671 hash_generate[2].hash/final/memory_reg_0_i_83__1_n_0 + SLICE_X50Y194 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.216 18.887 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] + net (fo=1, routed) 0.000 18.887 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 + SLICE_X50Y195 CARRY4 (Prop_carry4_CI_O[1]) + 0.212 19.099 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] + net (fo=2, routed) 0.655 19.754 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 + SLICE_X49Y198 LUT3 (Prop_lut3_I1_O) 0.155 19.909 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O + net (fo=1, routed) 0.000 19.909 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 + SLICE_X49Y198 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 20.233 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] + net (fo=1, routed) 0.000 20.233 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 + SLICE_X49Y199 CARRY4 (Prop_carry4_CI_O[2]) + 0.136 20.369 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] + net (fo=9, routed) 0.954 21.323 storage_generate[2].storage/O76[10] + RAMB36_X2Y42 RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=668, unset) 0.638 4.638 storage_generate[2].storage/CLK + RAMB36_X2Y42 RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + RAMB36_X2Y42 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) + -0.578 4.025 storage_generate[2].storage/memory_reg_6 + ------------------------------------------------------------------- + required time 4.025 + arrival time -21.323 + ------------------------------------------------------------------- + slack -17.298 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.081ns (arrival time - required time) + Source: registered_config.cfg_record_reg[2]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_0/DIADI[2] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.251ns (logic 0.100ns (39.889%) route 0.151ns (60.111%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X26Y200 FDRE r registered_config.cfg_record_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X26Y200 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[2]/Q + net (fo=4, routed) 0.151 0.534 storage_generate[3].storage/memory_reg_8_1[2] + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[2] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2]) + 0.155 0.453 storage_generate[3].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.534 + ------------------------------------------------------------------- + slack 0.081 + +Slack (MET) : 0.092ns (arrival time - required time) + Source: registered_config.cfg_record_reg[3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_0/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.262ns (logic 0.100ns (38.194%) route 0.162ns (61.806%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X24Y202 FDRE r registered_config.cfg_record_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[3]/Q + net (fo=4, routed) 0.162 0.545 storage_generate[3].storage/memory_reg_8_1[3] + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[3]) + 0.155 0.453 storage_generate[3].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.545 + ------------------------------------------------------------------- + slack 0.092 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: registered_config.cfg_record_reg[26]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_1/DIADI[8] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.289ns (logic 0.118ns (40.800%) route 0.171ns (59.200%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X10Y196 FDRE r registered_config.cfg_record_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y196 FDRE (Prop_fdre_C_Q) 0.118 0.401 r registered_config.cfg_record_reg[26]/Q + net (fo=4, routed) 0.171 0.572 storage_generate[3].storage/memory_reg_8_1[26] + RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X0Y39 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[8]) + 0.155 0.453 storage_generate[3].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.572 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: registered_config.cfg_record_reg[30]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_1/DIADI[12] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.291ns (logic 0.118ns (40.578%) route 0.173ns (59.422%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X10Y196 FDRE r registered_config.cfg_record_reg[30]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y196 FDRE (Prop_fdre_C_Q) 0.118 0.401 r registered_config.cfg_record_reg[30]/Q + net (fo=4, routed) 0.173 0.574 storage_generate[3].storage/memory_reg_8_1[30] + RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/DIADI[12] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X0Y39 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[12]) + 0.155 0.453 storage_generate[3].storage/memory_reg_1 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.574 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: registered_config.cfg_record_reg[5]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_0/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.292ns (logic 0.100ns (34.221%) route 0.192ns (65.779%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X24Y202 FDRE r registered_config.cfg_record_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[5]/Q + net (fo=4, routed) 0.192 0.575 storage_generate[3].storage/memory_reg_8_1[5] + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[5]) + 0.155 0.453 storage_generate[3].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.575 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.124ns (arrival time - required time) + Source: registered_config.cfg_record_reg[101]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_5/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.294ns (logic 0.100ns (34.020%) route 0.194ns (65.980%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X25Y208 FDRE r registered_config.cfg_record_reg[101]/C + ------------------------------------------------------------------- ------------------- + SLICE_X25Y208 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[101]/Q + net (fo=4, routed) 0.194 0.577 storage_generate[3].storage/memory_reg_8_1[101] + RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y41 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[11]) + 0.155 0.453 storage_generate[3].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.577 + ------------------------------------------------------------------- + slack 0.124 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: registered_config.cfg_record_reg[103]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_5/DIADI[13] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.295ns (logic 0.100ns (33.917%) route 0.195ns (66.083%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X25Y208 FDRE r registered_config.cfg_record_reg[103]/C + ------------------------------------------------------------------- ------------------- + SLICE_X25Y208 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[103]/Q + net (fo=4, routed) 0.195 0.578 storage_generate[3].storage/memory_reg_8_1[103] + RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/DIADI[13] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y41 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[13]) + 0.155 0.453 storage_generate[3].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.578 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.132ns (arrival time - required time) + Source: registered_config.cfg_record_reg[93]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_5/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.302ns (logic 0.100ns (33.081%) route 0.202ns (66.919%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X24Y205 FDRE r registered_config.cfg_record_reg[93]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y205 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[93]/Q + net (fo=4, routed) 0.202 0.586 storage_generate[3].storage/memory_reg_8_1[93] + RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y41 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[3]) + 0.155 0.453 storage_generate[3].storage/memory_reg_5 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.586 + ------------------------------------------------------------------- + slack 0.132 + +Slack (MET) : 0.138ns (arrival time - required time) + Source: registered_config.cfg_record_reg[14]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_0/DIADI[14] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.307ns (logic 0.100ns (32.526%) route 0.207ns (67.474%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X29Y202 FDRE r registered_config.cfg_record_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X29Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[14]/Q + net (fo=4, routed) 0.207 0.591 storage_generate[3].storage/memory_reg_8_1[14] + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[14] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[14]) + 0.155 0.453 storage_generate[3].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.591 + ------------------------------------------------------------------- + slack 0.138 + +Slack (MET) : 0.140ns (arrival time - required time) + Source: registered_config.cfg_record_reg[9]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: storage_generate[3].storage/memory_reg_0/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.309ns (logic 0.100ns (32.319%) route 0.209ns (67.681%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.283 0.283 CLK + SLICE_X28Y202 FDRE r registered_config.cfg_record_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X28Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[9]/Q + net (fo=4, routed) 0.209 0.593 storage_generate[3].storage/memory_reg_8_1[9] + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK + RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + clock pessimism 0.000 0.298 + RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[9]) + 0.155 0.453 storage_generate[3].storage/memory_reg_0 + ------------------------------------------------------------------- + required time -0.453 + arrival time 0.593 + ------------------------------------------------------------------- + slack 0.140 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: CLK +Waveform(ns): { 0.000 2.000 } +Period(ns): 4.000 +Sources: { CLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y35 storage_generate[0].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y34 storage_generate[0].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y32 storage_generate[0].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y36 storage_generate[0].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y38 storage_generate[0].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y33 storage_generate[0].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y37 storage_generate[0].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y36 storage_generate[0].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB18_X0Y70 storage_generate[0].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X2Y33 storage_generate[1].storage/memory_reg_0/CLKARDCLK +Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X17Y189 memory_key_reg[118]/C +Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X17Y189 memory_key_reg[118]/C +Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[125]/C +Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[125]/C +Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[131]/C +Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[131]/C +Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[133]/C +Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[133]/C +Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[47]/C +Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[47]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X37Y182 memory_key_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X37Y182 memory_key_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[100]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[100]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y186 memory_key_reg[101]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y186 memory_key_reg[101]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y189 memory_key_reg[102]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y189 memory_key_reg[102]/C +High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[103]/C +High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[103]/C + + + diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx new file mode 100644 index 0000000..133a998 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb new file mode 100644 index 0000000..d0831f5 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt new file mode 100644 index 0000000..fdf26d2 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt @@ -0,0 +1,212 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:54:00 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb +| Design : filter +| Device : xc7k160tffv676-1 +| Speed File : -1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs | 3503 | 0 | 0 | 101400 | 3.45 | +| LUT as Logic | 3503 | 0 | 0 | 101400 | 3.45 | +| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | +| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 | +| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 563 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+------+-------+------------+-----------+-------+ +| Slice | 1066 | 0 | 0 | 25350 | 4.21 | +| SLICEL | 659 | 0 | | | | +| SLICEM | 407 | 0 | | | | +| LUT as Logic | 3503 | 0 | 0 | 101400 | 3.45 | +| using O5 output only | 0 | | | | | +| using O6 output only | 2799 | | | | | +| using O5 and O6 | 704 | | | | | +| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | | +| LUT as Shift Register | 0 | 0 | | | | +| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | +| Register driven from within the Slice | 19 | | | | | +| Register driven from outside the Slice | 544 | | | | | +| LUT in front of the register is unused | 298 | | | | | +| LUT in front of the register is used | 246 | | | | | +| Unique Control Sets | 2 | | 0 | 25350 | <0.01 | ++--------------------------------------------+------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 34 | 0 | 0 | 325 | 10.46 | +| RAMB36/FIFO* | 32 | 0 | 0 | 325 | 9.85 | +| RAMB36E1 only | 32 | | | | | +| RAMB18 | 4 | 0 | 0 | 650 | 0.62 | +| RAMB18E1 only | 4 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 0 | 0 | 0 | 400 | 0.00 | +| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 384 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 0 | 32 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT5 | 995 | LUT | +| LUT6 | 950 | LUT | +| LUT3 | 900 | LUT | +| LUT2 | 874 | LUT | +| CARRY4 | 681 | CarryLogic | +| FDRE | 563 | Flop & Latch | +| LUT4 | 260 | LUT | +| LUT1 | 228 | LUT | +| RAMB36E1 | 32 | Block Memory | +| RAMB18E1 | 4 | Block Memory | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/synth/filter_vivado.runs/impl_1/gen_run.xml b/synth/filter_vivado.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..467eff5 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/gen_run.xml @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/impl_1/htr.txt b/synth/filter_vivado.runs/impl_1/htr.txt new file mode 100644 index 0000000..4e70aab --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace diff --git a/synth/filter_vivado.runs/impl_1/init_design.pb b/synth/filter_vivado.runs/impl_1/init_design.pb new file mode 100644 index 0000000..4af5cfe Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/init_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/opt_design.pb b/synth/filter_vivado.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..121acc1 Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/opt_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/opt_design_reports.log b/synth/filter_vivado.runs/impl_1/opt_design_reports.log new file mode 100644 index 0000000..1318f22 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/opt_design_reports.log @@ -0,0 +1,41 @@ + +*** Running vivado + with args -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs opt_design + + +****** Vivado v2023.2 (64-bit) + **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 + **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 + **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +source filter_reports.tcl -notrace +Command: open_checkpoint filter_opt.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1242.316 ; gain = 0.000 ; free physical = 206 ; free virtual = 6416 +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1629.965 ; gain = 0.000 ; free physical = 208 ; free virtual = 7125 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1706.652 ; gain = 1.000 ; free physical = 224 ; free virtual = 7060 +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.262 ; gain = 0.000 ; free physical = 124 ; free virtual = 6613 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2023.2 (64-bit) build 4029153 +open_checkpoint: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2311.297 ; gain = 1068.980 ; free physical = 119 ; free virtual = 6616 +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 19:06:34 2023... diff --git a/synth/filter_vivado.runs/impl_1/phys_opt_design.pb b/synth/filter_vivado.runs/impl_1/phys_opt_design.pb new file mode 100644 index 0000000..17e46dc Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/phys_opt_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/place_design.pb b/synth/filter_vivado.runs/impl_1/place_design.pb new file mode 100644 index 0000000..54c71ec Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/place_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/project.wdf b/synth/filter_vivado.runs/impl_1/project.wdf new file mode 100644 index 0000000..ca8c64f --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ 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b/synth/filter_vivado.runs/impl_1/route_design_reports.bat new file mode 100644 index 0000000..ffdb67f --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/route_design_reports.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem route_design_reports.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\route_design_reports.js" %* diff --git a/synth/filter_vivado.runs/impl_1/route_design_reports.js b/synth/filter_vivado.runs/impl_1/route_design_reports.js new file mode 100644 index 0000000..32e7621 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/route_design_reports.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// route_design_reports.js: a Vivado-generated reports generation script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrapReports.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + " -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs route_design" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/synth/filter_vivado.runs/impl_1/route_design_reports.sh b/synth/filter_vivado.runs/impl_1/route_design_reports.sh new file mode 100755 index 0000000..b5ca98b --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/route_design_reports.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# route_design_reports.sh: a Vivado-generated reports generation script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin +else + PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=route_design_reports.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrapReports.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs route_design \ No newline at end of file diff --git a/synth/filter_vivado.runs/impl_1/rundef.js b/synth/filter_vivado.runs/impl_1/rundef.js new file mode 100644 index 0000000..3b636df --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/rundef.js @@ -0,0 +1,45 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/synth/filter_vivado.runs/impl_1/runme.bat b/synth/filter_vivado.runs/impl_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/synth/filter_vivado.runs/impl_1/runme.log b/synth/filter_vivado.runs/impl_1/runme.log new file mode 100644 index 0000000..acf5508 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/runme.log @@ -0,0 +1,1320 @@ + +*** Running vivado + with args -log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace + + +****** Vivado v2023.2 (64-bit) + **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 + **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 + **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +source filter.tcl -notrace +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.508 ; gain = 0.023 ; free physical = 106 ; free virtual = 6598 +Command: link_design -top filter -part xc7k160tffv676-1 -mode out_of_context +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.383 ; gain = 0.000 ; free physical = 131 ; free virtual = 6415 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1767.770 ; gain = 0.000 ; free physical = 122 ; free virtual = 6282 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1773.742 ; gain = 465.234 ; free physical = 114 ; free virtual = 6277 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1824.535 ; gain = 50.793 ; free physical = 205 ; free virtual = 6272 + +Starting Cache Timing Information Task +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 10236edc4 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2345.418 ; gain = 520.883 ; free physical = 117 ; free virtual = 5807 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 146 ; free virtual = 5487 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 +Phase 1 Initialization | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 138 ; free virtual = 5486 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 +Phase 2 Timer Update And Timing Data Collection | Checksum: 10236edc4 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 + +Phase 3 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 10c3daf90 + +Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 134 ; free virtual = 5484 +Retarget | Checksum: 10c3daf90 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 9bde81ac + +Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 132 ; free virtual = 5484 +Constant propagation | Checksum: 9bde81ac +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 5 Sweep +Phase 5 Sweep | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 115 ; free virtual = 5482 +Sweep | Checksum: f9b192b3 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 +BUFG optimization | Checksum: f9b192b3 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 +Shift Register Optimization | Checksum: f9b192b3 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 8 Post Processing Netlist +Phase 8 Post Processing Netlist | Checksum: f9b192b3 + +Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 +Post Processing Netlist | Checksum: f9b192b3 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Phase 9 Finalization + +Phase 9.1 Finalizing Design Cores and Updating Shapes +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 112 ; free virtual = 5479 + +Phase 9.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 111 ; free virtual = 5479 +Phase 9.2 Verifying Netlist Connectivity | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 +Phase 9 Finalization | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 109 ; free virtual = 5479 +INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 105 ; free virtual = 5477 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 36 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports +Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 72 +Ending PowerOpt Patch Enables Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 192 ; free virtual = 5341 +Ending Power Optimization Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 137.883 ; free physical = 172 ; free virtual = 5341 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 172 ; free virtual = 5341 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 +Ending Netlist Obfuscation Task | Checksum: d19459d4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 +INFO: [Common 17-83] Releasing license: Implementation +30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2817.184 ; gain = 1043.441 ; free physical = 171 ; free virtual = 5343 +INFO: [runtcl-4] Executing : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx +Command: report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt. +report_drc completed successfully +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5315 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_opt.dcp' has been generated. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3583ee0c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3d558abc + +Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 132 ; free virtual = 5293 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 8cce5483 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 8cce5483 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 +Phase 1 Placer Initialization | Checksum: 8cce5483 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 47fa083f + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1275ad596 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5286 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 1275ad596 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1457cd503 + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 169 ; free virtual = 5289 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 10 LUTNM shape to break, 4 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 10, total 10, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 12 nets or LUTs. Breaked 10 LUTs, combined 2 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. +INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 10 | 2 | 12 | 0 | 1 | 00:00:00 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 10 | 2 | 12 | 0 | 9 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 19c5c57a6 + +Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 +Phase 2.4 Global Placement Core | Checksum: 1b40ef446 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 +Phase 2 Global Placement | Checksum: 1b40ef446 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 11f4d2582 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5283 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12b805f00 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:21 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 137 ; free virtual = 5282 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 157230410 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 128b350f2 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 + +Phase 3.5 Fast Optimization +Phase 3.5 Fast Optimization | Checksum: 1632181f8 + +Time (s): cpu = 00:00:58 ; elapsed = 00:00:24 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 130 ; free virtual = 5276 + +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: f844008a + +Time (s): cpu = 00:01:00 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5275 + +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 14d2456fe + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 + +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 17ad421e0 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 + +Phase 3.9 Fast Optimization +Phase 3.9 Fast Optimization | Checksum: 17f4b35b0 + +Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 +Phase 3 Detail Placement | Checksum: 17f4b35b0 + +Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 1caaa20ca + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.908 | TNS=-6490.125 | +Phase 1 Physical Synthesis Initialization | Checksum: 179e6ab06 + +Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 153 ; free virtual = 5299 +INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 179e6ab06 + +Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1caaa20ca + +Time (s): cpu = 00:01:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=-16.162. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 186ecb07f + +Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 + +Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 +Phase 4.1 Post Commit Optimization | Checksum: 186ecb07f + +Time (s): cpu = 00:01:54 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5295 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 186ecb07f + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 4x4| 8x8| +|___________|___________________|___________________| +| South| 2x2| 4x4| +|___________|___________________|___________________| +| East| 4x4| 8x8| +|___________|___________________|___________________| +| West| 4x4| 4x4| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 186ecb07f + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Phase 4.3 Placer Reporting | Checksum: 186ecb07f + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2313e4908 + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Ending Placer Task | Checksum: 1402e79b2 + +Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +75 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:01:57 ; elapsed = 00:01:13 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +INFO: [runtcl-4] Executing : report_io -file filter_io_placed.rpt +report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 123 ; free virtual = 5306 +INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file filter_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 129 ; free virtual = 5308 +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 133 ; free virtual = 5307 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 191 ; free virtual = 5293 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_placed.dcp' has been generated. +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' + +Starting Initial Update Timing Task +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 +INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 2.64s | WALL: 1.05s +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | +Phase 1 Physical Synthesis Initialization | Checksum: 1c58d1c6b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5268 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | + +Phase 2 DSP Register Optimization +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Phase 2 DSP Register Optimization | Checksum: 1c58d1c6b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5269 + +Phase 3 Critical Path Optimization +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net in_key[8]. Re-placed instance registered_input.in_key_reg[8] +INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.142 | TNS=-6267.728 | +INFO: [Physopt 32-81] Processed net in_key[72]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.119 | TNS=-6265.451 | +INFO: [Physopt 32-702] Processed net in_key[72]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_24_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_59_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_98_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_190_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_350[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_93_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_96_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_127_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp10_out_0[9]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_286_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_479_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp12_out[25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_577_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_571_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_429_0[29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_434_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_535_0[24]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_725_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1100__0_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.103 | TNS=-6263.768 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net in_key[0]. Re-placed instance registered_input.in_key_reg[0] +INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.102 | TNS=-6259.511 | +INFO: [Physopt 32-81] Processed net in_key[8]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.099 | TNS=-6259.214 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.072 | TNS=-6256.541 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_433_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_721_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][a][23]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.060 | TNS=-6253.472 | +INFO: [Physopt 32-81] Processed net in_key[2]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[2]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.059 | TNS=-6252.086 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.046 | TNS=-6250.701 | +INFO: [Physopt 32-81] Processed net in_key[64]. Replicated 5 times. +INFO: [Physopt 32-735] Processed net in_key[64]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | +INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] +INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | +INFO: [Physopt 32-81] Processed net in_key[68]. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[68]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.007 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[1]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[1]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.043 | TNS=-6248.027 | +INFO: [Physopt 32-663] Processed net in_key[5]. Re-placed instance registered_input.in_key_reg[5] +INFO: [Physopt 32-735] Processed net in_key[5]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.041 | TNS=-6247.730 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_431_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/minusOp4_out[27]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_comp. +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[25]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6247.631 | +INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Re-placed instance hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1101 +INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6245.453 | +INFO: [Physopt 32-663] Processed net in_key[74]. Re-placed instance registered_input.in_key_reg[74] +INFO: [Physopt 32-735] Processed net in_key[74]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.057 | +INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] +INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.255 | +INFO: [Physopt 32-81] Processed net in_key[69]. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[69]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.036 | TNS=-6244.364 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net in_key[66]. Re-placed instance registered_input.in_key_reg[66] +INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.030 | TNS=-6243.770 | +INFO: [Physopt 32-702] Processed net in_key[66]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1066_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.029 | TNS=-6243.275 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net in_key[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_350__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp10_out_0[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_322__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_808__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 22 pins. +INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1151__1_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6243.176 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_724_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Re-placed instance hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_732 +INFO: [Physopt 32-735] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6241.592 | +INFO: [Physopt 32-702] Processed net in_key[65]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1155__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-663] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Re-placed instance hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1 +INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +INFO: [Physopt 32-663] Processed net in_key[10]. Re-placed instance registered_input.in_key_reg[10] +INFO: [Physopt 32-735] Processed net in_key[10]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +INFO: [Physopt 32-702] Processed net in_key[71]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[30]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_430_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_670_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[19]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_962_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[15]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_889__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_797__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/O76[9]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 137 ; free virtual = 5271 +Phase 3 Critical Path Optimization | Checksum: 17af5ebfb + +Time (s): cpu = 00:00:41 ; elapsed = 00:00:21 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 131 ; free virtual = 5271 + +Phase 4 Critical Path Optimization +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[71]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[71]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.023 | TNS=-6240.602 | +INFO: [Physopt 32-81] Processed net in_key[66]. Replicated 2 times. +INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.021 | TNS=-6240.404 | +INFO: [Physopt 32-81] Processed net in_key[64]_repN. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[64]_repN. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6240.008 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[9]. Replicated 3 times. +INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6239.810 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-81] Processed net in_key[0]. Replicated 5 times. +INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.018 | TNS=-6239.316 | +INFO: [Physopt 32-663] Processed net in_key[72]. Re-placed instance registered_input.in_key_reg[72] +INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.017 | TNS=-6238.820 | +INFO: [Physopt 32-702] Processed net in_key[2]_repN. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_3_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_258_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_259_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_256_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_580_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_579_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_575_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_677_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Critical path length was reduced through logic transformation on cell hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_comp. +INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[16]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.015 | TNS=-6237.929 | +INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 1 times. +INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.732 | +INFO: [Physopt 32-663] Processed net in_key[78]. Re-placed instance registered_input.in_key_reg[78] +INFO: [Physopt 32-735] Processed net in_key[78]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.533 | +INFO: [Physopt 32-663] Processed net in_key[13]. Re-placed instance registered_input.in_key_reg[13] +INFO: [Physopt 32-735] Processed net in_key[13]. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_722_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[24]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_385__2_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[20]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_912_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_858__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_768__1_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/plusOp_inferred__0/i__carry__1_n_7. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/O76[9]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 +Phase 4 Critical Path Optimization | Checksum: 17af5ebfb + +Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 +INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-16.012 | TNS=-6236.939 | + +Summary of Physical Synthesis Optimizations +============================================ + + +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Critical Path | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 2 | 00:00:31 | +| Total | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 3 | 00:00:31 | +------------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 +Ending Physical Synthesis Task | Checksum: 27673438e + +Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +INFO: [Common 17-83] Releasing license: Implementation +415 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:01:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 109 ; free virtual = 5273 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: a88baaee ConstDB: 0 ShapeSum: d8eec616 RouteDB: 0 +WARNING: [Route 35-197] Clock port "CLK" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. +WARNING: [Route 35-198] Port "CONFIG_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[94]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[94]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[116]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[116]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[114]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[114]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[102]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[102]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[98]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[98]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[96]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[96]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[86]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[86]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[84]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[84]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[70]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[70]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[103]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[103]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[57]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[57]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[66]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[66]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[64]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[64]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[90]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[90]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[89]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[89]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[76]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[76]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[50]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[50]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[88]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[88]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[44]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[44]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[48]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[48]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[72]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[72]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[54]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[54]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[46]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[46]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[82]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[82]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[77]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[77]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[52]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[52]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[69]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[69]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[47]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[47]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_WRITE" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_WRITE". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "RESET" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "RESET". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[78]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[78]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[75]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[75]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[74]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[74]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[68]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[68]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[126]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[126]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[53]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[53]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[73]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[73]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_DATA[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_EMPTY" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_EMPTY". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[97]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[97]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[55]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[55]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +INFO: [Common 17-14] Message 'Route 35-198' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. +Post Restoration Checksum: NetGraph: f5668f66 | NumContArr: ae2b9928 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 328e41dc8 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:35 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 97 ; free virtual = 5070 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 328e41dc8 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 117 ; free virtual = 5073 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 328e41dc8 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 119 ; free virtual = 5075 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 242e0954c + +Time (s): cpu = 00:00:58 ; elapsed = 00:00:38 . Memory (MB): peak = 2979.195 ; gain = 142.992 ; free physical = 163 ; free virtual = 5036 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-15.599| TNS=-6066.110| WHS=0.033 | THS=0.000 | + + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 5168 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 5168 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 1d6088a45 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 1d6088a45 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 + +Phase 3.2 Initial Net Routing +Phase 3.2 Initial Net Routing | Checksum: 2130f4a2f + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 +Phase 3 Initial Routing | Checksum: 2130f4a2f + +Time (s): cpu = 00:01:33 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 4441 + Number of Nodes with overlaps = 1719 + Number of Nodes with overlaps = 1028 + Number of Nodes with overlaps = 514 + Number of Nodes with overlaps = 269 + Number of Nodes with overlaps = 127 + Number of Nodes with overlaps = 70 + Number of Nodes with overlaps = 32 + Number of Nodes with overlaps = 19 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.774| TNS=-6851.693| WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 225940652 + +Time (s): cpu = 00:04:22 ; elapsed = 00:02:04 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 215 ; free virtual = 5156 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 231 + Number of Nodes with overlaps = 180 + Number of Nodes with overlaps = 152 + Number of Nodes with overlaps = 92 + Number of Nodes with overlaps = 84 + Number of Nodes with overlaps = 60 + Number of Nodes with overlaps = 44 + Number of Nodes with overlaps = 35 + Number of Nodes with overlaps = 37 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 20 + Number of Nodes with overlaps = 13 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.494| TNS=-6783.227| WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 2cd491a74 + +Time (s): cpu = 00:05:31 ; elapsed = 00:02:59 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 325 ; free virtual = 5054 + +Phase 4.3 Global Iteration 2 + Number of Nodes with overlaps = 141 + Number of Nodes with overlaps = 144 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 105 + Number of Nodes with overlaps = 121 + Number of Nodes with overlaps = 78 + Number of Nodes with overlaps = 57 + Number of Nodes with overlaps = 48 + Number of Nodes with overlaps = 27 + Number of Nodes with overlaps = 17 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 10 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | + +Phase 4.3 Global Iteration 2 | Checksum: 18900c83b + +Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 +Phase 4 Rip-up And Reroute | Checksum: 18900c83b + +Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp + +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 18900c83b + +Time (s): cpu = 00:06:36 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 183 ; free virtual = 5022 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | + + Number of Nodes with overlaps = 0 +Phase 5.1 Delay CleanUp | Checksum: 1a7ad13b4 + +Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 1a7ad13b4 + +Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 +Phase 5 Delay and Skew Optimization | Checksum: 1a7ad13b4 + +Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 +Phase 6 Post Hold Fix | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 1.77316 % + Global Horizontal Routing Utilization = 2.02251 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +--GLOBAL Congestion: +Utilization threshold used for congestion level computation: 0.85 +Congestion Report +North Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 80.1802%, No Congested Regions. +East Dir 2x2 Area, Max Cong = 91.5441%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): + INT_L_X32Y168 -> INT_R_X33Y169 +West Dir 1x1 Area, Max Cong = 94.1176%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): + INT_L_X28Y189 -> INT_L_X28Y189 + INT_L_X26Y188 -> INT_L_X26Y188 + INT_R_X27Y188 -> INT_R_X27Y188 + INT_L_X28Y187 -> INT_L_X28Y187 + INT_L_X14Y172 -> INT_L_X14Y172 + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 1 +Effective congestion level: 2 Aspect Ratio: 0.5 Sparse Ratio: 0.5 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 + +Phase 7 Route finalize | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 133 ; free virtual = 5020 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1e57763e0 + +Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 128 ; free virtual = 5019 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 26293a506 + +Time (s): cpu = 00:06:50 ; elapsed = 00:03:50 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 243 ; free virtual = 5043 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | + +WARNING: [Route 35-328] Router estimated timing not met. +Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. +Phase 10 Post Router Timing | Checksum: 26293a506 + +Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 224 ; free virtual = 5039 +INFO: [Route 35-16] Router Completed Successfully + +Phase 11 Post-Route Event Processing +Phase 11 Post-Route Event Processing | Checksum: 123c431d6 + +Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 +Ending Routing Task | Checksum: 123c431d6 + +Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +435 Infos, 109 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:06:55 ; elapsed = 00:03:53 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 137 ; free virtual = 5047 +INFO: [runtcl-4] Executing : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx +Command: report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx +Command: report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +INFO: [DRC 23-133] Running Methodology with 4 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx +Command: report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +445 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file filter_route_status.rpt -pb filter_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. +INFO: [runtcl-4] Executing : report_incremental_reuse -file filter_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file filter_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 154 ; free virtual = 4924 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 198 ; free virtual = 4894 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 199 ; free virtual = 4893 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_routed.dcp' has been generated. +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:58:43 2023... diff --git a/synth/filter_vivado.runs/impl_1/runme.sh b/synth/filter_vivado.runs/impl_1/runme.sh new file mode 100755 index 0000000..1fc79d7 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/runme.sh @@ -0,0 +1,44 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin +else + PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace + + diff --git a/synth/filter_vivado.runs/impl_1/vivado.jou b/synth/filter_vivado.runs/impl_1/vivado.jou new file mode 100644 index 0000000..2175164 --- /dev/null +++ b/synth/filter_vivado.runs/impl_1/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 18:51:36 2023 +# Process ID: 19329 +# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1 +# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace +# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi +# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +source filter.tcl -notrace diff --git a/synth/filter_vivado.runs/impl_1/vivado.pb b/synth/filter_vivado.runs/impl_1/vivado.pb new file mode 100644 index 0000000..00486df Binary files /dev/null and b/synth/filter_vivado.runs/impl_1/vivado.pb differ diff --git a/synth/filter_vivado.runs/synth_1/.Vivado_Synthesis.queue.rst b/synth/filter_vivado.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/synth_1/.vivado.begin.rst b/synth/filter_vivado.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..a9ba09a --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/synth/filter_vivado.runs/synth_1/.vivado.end.rst b/synth/filter_vivado.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/synth_1/ISEWrap.js b/synth/filter_vivado.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/synth/filter_vivado.runs/synth_1/ISEWrap.sh b/synth/filter_vivado.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..05d5381 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/synth/filter_vivado.runs/synth_1/__synthesis_is_complete__ b/synth/filter_vivado.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/synth/filter_vivado.runs/synth_1/filter.dcp b/synth/filter_vivado.runs/synth_1/filter.dcp new file mode 100644 index 0000000..e647b6e Binary files /dev/null and b/synth/filter_vivado.runs/synth_1/filter.dcp differ diff --git a/synth/filter_vivado.runs/synth_1/filter.tcl b/synth/filter_vivado.runs/synth_1/filter.tcl new file mode 100644 index 0000000..c31b414 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/filter.tcl @@ -0,0 +1,129 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "synth_1" START { ROLLUP_AUTO } +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7k160tffv676-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.cache/wt [current_project] +set_property parent.project_path /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language VHDL [current_project] +set_property ip_output_repo /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_vhdl -vhdl2008 -library xil_defaultlib { + /home/veronikaplevacova/Plocha/PCS2/comp/functions.vhd + /home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd + /home/veronikaplevacova/Plocha/PCS2/filter_ent.vhd + /home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd + /home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd + /home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd + /home/veronikaplevacova/Plocha/PCS2/filter.vhd +} +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc /home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc +set_property used_in_implementation false [get_files /home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef filter.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "synth_1_synth_report_utilization_0" "report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb" +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/synth/filter_vivado.runs/synth_1/filter.vds b/synth/filter_vivado.runs/synth_1/filter.vds new file mode 100644 index 0000000..e06791e --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/filter.vds @@ -0,0 +1,339 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 18:47:59 2023 +# Process ID: 18749 +# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1 +# Command line: vivado -log filter.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl +# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.vds +# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3075.336 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +source filter.tcl -notrace +create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1275.312 ; gain = 39.836 ; free physical = 248 ; free virtual = 8095 +Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 18803 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2039.840 ; gain = 404.684 ; free physical = 155 ; free virtual = 6867 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000001 +INFO: [Synth 8-638] synthesizing module 'jenkins_mix' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42] + Parameter LENGTH bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'jenkins_mix' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42] +INFO: [Synth 8-638] synthesizing module 'jenkins_final' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42] + Parameter LENGTH bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'jenkins_final' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized0' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000010 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized0' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized1' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000011 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized1' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized2' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000100 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized2' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] + Parameter ITEM_WIDTH bound to: 145 - type: integer + Parameter ITEMS bound to: 2048 - type: integer + Parameter OUTPUT_REGISTER bound to: 0 - type: bool +INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] +WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2119.777 ; gain = 484.621 ; free physical = 119 ; free virtual = 6746 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2137.590 ; gain = 0.000 ; free physical = 94 ; free virtual = 6678 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.324 ; gain = 0.000 ; free physical = 115 ; free virtual = 6314 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 108 ; free virtual = 6278 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 106 ; free virtual = 5475 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffv676-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 162 ; free virtual = 5460 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 125 ; free virtual = 5450 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 120 ; free virtual = 5337 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 52 + 4 Input 32 Bit Adders := 8 + 2 Input 32 Bit Adders := 24 ++---XORs : + 2 Input 32 Bit XORs := 52 ++---Registers : + 145 Bit Registers := 5 + 128 Bit Registers := 3 + 16 Bit Registers := 1 + 11 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 8 ++---RAMs : + 290K Bit (2048 X 145 bit) RAMs := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 8 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:59 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 131 ; free virtual = 5310 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|filter | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 175 ; free virtual = 5367 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:17 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 243 ; free virtual = 5327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|filter | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:07 ; elapsed = 00:01:21 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 381 ; free virtual = 5319 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 681| +|2 |LUT1 | 228| +|3 |LUT2 | 874| +|4 |LUT3 | 900| +|5 |LUT4 | 260| +|6 |LUT5 | 995| +|7 |LUT6 | 950| +|8 |RAMB18E1 | 4| +|9 |RAMB36E1 | 32| +|10 |FDRE | 563| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 164 ; free virtual = 5187 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:01:26 . Memory (MB): peak = 2252.359 ; gain = 502.434 ; free physical = 148 ; free virtual = 5185 +Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 145 ; free virtual = 5184 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 115 ; free virtual = 5167 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 313 ; free virtual = 5535 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: d74e1ad3 +INFO: [Common 17-83] Releasing license: Synthesis +66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:33 ; elapsed = 00:01:44 . Memory (MB): peak = 2252.359 ; gain = 977.047 ; free physical = 232 ; free virtual = 5481 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1724.537; main = 1326.676; forked = 397.861 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3235.051; main = 2252.328; forked = 982.723 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2276.336 ; gain = 0.000 ; free physical = 226 ; free virtual = 5482 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:50:06 2023... diff --git a/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb new file mode 100644 index 0000000..c2b972b Binary files /dev/null and b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb differ diff --git a/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt new file mode 100644 index 0000000..7bfe611 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt @@ -0,0 +1,186 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Sun Dec 3 18:50:06 2023 +| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux +| Command : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb +| Design : filter +| Device : xc7k160tffv676-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 3498 | 0 | 0 | 101400 | 3.45 | +| LUT as Logic | 3498 | 0 | 0 | 101400 | 3.45 | +| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | +| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 | +| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 563 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 34 | 0 | 0 | 325 | 10.46 | +| RAMB36/FIFO* | 32 | 0 | 0 | 325 | 9.85 | +| RAMB36E1 only | 32 | | | | | +| RAMB18 | 4 | 0 | 0 | 650 | 0.62 | +| RAMB18E1 only | 4 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 0 | 0 | 0 | 400 | 0.00 | +| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 384 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 0 | 32 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT5 | 995 | LUT | +| LUT6 | 950 | LUT | +| LUT3 | 900 | LUT | +| LUT2 | 874 | LUT | +| CARRY4 | 681 | CarryLogic | +| FDRE | 563 | Flop & Latch | +| LUT4 | 260 | LUT | +| LUT1 | 228 | LUT | +| RAMB36E1 | 32 | Block Memory | +| RAMB18E1 | 4 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/synth/filter_vivado.runs/synth_1/gen_run.xml b/synth/filter_vivado.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..69c862f --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/gen_run.xml @@ -0,0 +1,85 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/synth_1/htr.txt b/synth/filter_vivado.runs/synth_1/htr.txt new file mode 100644 index 0000000..3bf78f5 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log filter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl diff --git a/synth/filter_vivado.runs/synth_1/project.wdf b/synth/filter_vivado.runs/synth_1/project.wdf new file mode 100644 index 0000000..ca8c64f --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3566643632386632633138353432663961623136653661643866623536373363:506172656e742050412070726f6a656374204944:00 +eof:3523505476 diff --git a/synth/filter_vivado.runs/synth_1/rundef.js b/synth/filter_vivado.runs/synth_1/rundef.js new file mode 100644 index 0000000..2f2cb94 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;"; +} else { + PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log filter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/synth/filter_vivado.runs/synth_1/runme.bat b/synth/filter_vivado.runs/synth_1/runme.bat new file mode 100644 index 0000000..3a5f853 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/synth/filter_vivado.runs/synth_1/runme.log b/synth/filter_vivado.runs/synth_1/runme.log new file mode 100644 index 0000000..6b937f1 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/runme.log @@ -0,0 +1,338 @@ + +*** Running vivado + with args -log filter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl + + +****** Vivado v2023.2 (64-bit) + **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 + **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 + **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +source filter.tcl -notrace +create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1275.312 ; gain = 39.836 ; free physical = 248 ; free virtual = 8095 +Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 18803 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2039.840 ; gain = 404.684 ; free physical = 155 ; free virtual = 6867 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000001 +INFO: [Synth 8-638] synthesizing module 'jenkins_mix' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42] + Parameter LENGTH bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'jenkins_mix' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42] +INFO: [Synth 8-638] synthesizing module 'jenkins_final' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42] + Parameter LENGTH bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'jenkins_final' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized0' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000010 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized0' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized1' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000011 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized1' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized2' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000100 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized2' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] + Parameter ITEM_WIDTH bound to: 145 - type: integer + Parameter ITEMS bound to: 2048 - type: integer + Parameter OUTPUT_REGISTER bound to: 0 - type: bool +INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] +WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2119.777 ; gain = 484.621 ; free physical = 119 ; free virtual = 6746 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2137.590 ; gain = 0.000 ; free physical = 94 ; free virtual = 6678 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.324 ; gain = 0.000 ; free physical = 115 ; free virtual = 6314 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 108 ; free virtual = 6278 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 106 ; free virtual = 5475 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffv676-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 162 ; free virtual = 5460 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 125 ; free virtual = 5450 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 120 ; free virtual = 5337 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 52 + 4 Input 32 Bit Adders := 8 + 2 Input 32 Bit Adders := 24 ++---XORs : + 2 Input 32 Bit XORs := 52 ++---Registers : + 145 Bit Registers := 5 + 128 Bit Registers := 3 + 16 Bit Registers := 1 + 11 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 8 ++---RAMs : + 290K Bit (2048 X 145 bit) RAMs := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 8 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:59 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 131 ; free virtual = 5310 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|filter | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 175 ; free virtual = 5367 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:17 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 243 ; free virtual = 5327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|filter | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:07 ; elapsed = 00:01:21 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 381 ; free virtual = 5319 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 681| +|2 |LUT1 | 228| +|3 |LUT2 | 874| +|4 |LUT3 | 900| +|5 |LUT4 | 260| +|6 |LUT5 | 995| +|7 |LUT6 | 950| +|8 |RAMB18E1 | 4| +|9 |RAMB36E1 | 32| +|10 |FDRE | 563| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 164 ; free virtual = 5187 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:01:26 . Memory (MB): peak = 2252.359 ; gain = 502.434 ; free physical = 148 ; free virtual = 5185 +Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 145 ; free virtual = 5184 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 115 ; free virtual = 5167 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 313 ; free virtual = 5535 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: d74e1ad3 +INFO: [Common 17-83] Releasing license: Synthesis +66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:33 ; elapsed = 00:01:44 . Memory (MB): peak = 2252.359 ; gain = 977.047 ; free physical = 232 ; free virtual = 5481 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1724.537; main = 1326.676; forked = 397.861 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3235.051; main = 2252.328; forked = 982.723 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2276.336 ; gain = 0.000 ; free physical = 226 ; free virtual = 5482 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:50:06 2023... diff --git a/synth/filter_vivado.runs/synth_1/runme.sh b/synth/filter_vivado.runs/synth_1/runme.sh new file mode 100755 index 0000000..a1ea6eb --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin +else + PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log filter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl diff --git a/synth/filter_vivado.runs/synth_1/vivado.jou b/synth/filter_vivado.runs/synth_1/vivado.jou new file mode 100644 index 0000000..8ba0bf1 --- /dev/null +++ b/synth/filter_vivado.runs/synth_1/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 18:47:59 2023 +# Process ID: 18749 +# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1 +# Command line: vivado -log filter.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl +# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.vds +# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3075.336 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +source filter.tcl -notrace diff --git a/synth/filter_vivado.runs/synth_1/vivado.pb b/synth/filter_vivado.runs/synth_1/vivado.pb new file mode 100644 index 0000000..9a1c851 Binary files /dev/null and b/synth/filter_vivado.runs/synth_1/vivado.pb differ diff --git a/synth/filter_vivado.xpr b/synth/filter_vivado.xpr new file mode 100644 index 0000000..6410e57 --- /dev/null +++ b/synth/filter_vivado.xpr @@ -0,0 +1,372 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/synth/vivado.jou b/synth/vivado.jou new file mode 100644 index 0000000..b347384 --- /dev/null +++ b/synth/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 18:32:16 2023 +# Process ID: 16210 +# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth +# Command line: vivado -mode batch -source filter.tcl +# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/vivado.log +# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3084.199 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +source filter.tcl diff --git a/synth/vivado.log b/synth/vivado.log new file mode 100644 index 0000000..3a523c1 --- /dev/null +++ b/synth/vivado.log @@ -0,0 +1,406 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 18:32:16 2023 +# Process ID: 16210 +# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth +# Command line: vivado -mode batch -source filter.tcl +# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/vivado.log +# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3084.199 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +source filter.tcl +# create_project -part xc7k160tffv676-1 -force filter_vivado +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1265.738 ; gain = 8.930 ; free physical = 200 ; free virtual = 9141 +# set_param project.enableVHDL2008 1 +# set_property target_language VHDL [current_project] +# set_property enable_vhdl_2008 1 [current_project] +# add_files -norecurse \ +# ../comp/functions.vhd \ +# ../comp/block_memory.vhd \ +# ../comp/jenkins_mix.vhd \ +# ../comp/jenkins_final.vhd \ +# ../comp/jenkins_hash.vhd \ +# ../filter_ent.vhd \ +# ../filter.vhd +# set_property file_type {VHDL 2008} [get_files] +# set_property top filter [current_fileset] +# add_files -fileset constrs_1 filter.xdc +# set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value "-mode out_of_context" -objects [get_runs synth_1] +# launch_runs synth_1 +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Sun Dec 3 18:32:37 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +# wait_on_run synth_1 +[Sun Dec 3 18:32:37 2023] Waiting for synth_1 to finish... + +*** Running vivado + with args -log filter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl + + +****** Vivado v2023.2 (64-bit) + **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 + **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 + **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +source filter.tcl -notrace +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1267.738 ; gain = 10.930 ; free physical = 159 ; free virtual = 8771 +Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 16359 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2031.641 ; gain = 403.715 ; free physical = 146 ; free virtual = 7359 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000001 +INFO: [Synth 8-638] synthesizing module 'jenkins_mix' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42] + Parameter LENGTH bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'jenkins_mix' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42] +INFO: [Synth 8-638] synthesizing module 'jenkins_final' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42] + Parameter LENGTH bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'jenkins_final' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized0' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000010 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized0' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized1' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000011 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized1' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized2' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] + Parameter LENGTH bound to: 4 - type: integer + Parameter INITVAL bound to: 32'b00000000000000000000000000000100 +INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized2' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] +INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] + Parameter ITEM_WIDTH bound to: 145 - type: integer + Parameter ITEMS bound to: 2048 - type: integer + Parameter OUTPUT_REGISTER bound to: 0 - type: bool +INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] +WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2111.609 ; gain = 483.684 ; free physical = 206 ; free virtual = 7213 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2129.422 ; gain = 501.496 ; free physical = 195 ; free virtual = 7202 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2129.422 ; gain = 501.496 ; free physical = 195 ; free virtual = 7202 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2129.422 ; gain = 0.000 ; free physical = 177 ; free virtual = 7203 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2246.156 ; gain = 0.000 ; free physical = 201 ; free virtual = 7190 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2246.191 ; gain = 0.000 ; free physical = 207 ; free virtual = 7192 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 168 ; free virtual = 7165 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffv676-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 168 ; free virtual = 7165 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 168 ; free virtual = 7165 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 164 ; free virtual = 7159 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 52 + 4 Input 32 Bit Adders := 8 + 2 Input 32 Bit Adders := 24 ++---XORs : + 2 Input 32 Bit XORs := 52 ++---Registers : + 145 Bit Registers := 5 + 128 Bit Registers := 3 + 16 Bit Registers := 1 + 11 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 8 ++---RAMs : + 290K Bit (2048 X 145 bit) RAMs := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 8 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load +WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 224 ; free virtual = 7142 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|filter | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 138 ; free virtual = 7118 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 206 ; free virtual = 7105 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|filter | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | +|filter | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST) | W | | 2 K x 145(WRITE_FIRST) | | R | Port A and B | 1 | 8 | ++------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 200 ; free virtual = 7099 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 285 ; free virtual = 7253 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 285 ; free virtual = 7253 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 681| +|2 |LUT1 | 228| +|3 |LUT2 | 874| +|4 |LUT3 | 900| +|5 |LUT4 | 260| +|6 |LUT5 | 995| +|7 |LUT6 | 950| +|8 |RAMB18E1 | 4| +|9 |RAMB36E1 | 32| +|10 |FDRE | 563| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 259 ; free virtual = 7249 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:56 ; elapsed = 00:00:58 . Memory (MB): peak = 2246.191 ; gain = 501.496 ; free physical = 250 ; free virtual = 7251 +Synthesis Optimization Complete : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 234 ; free virtual = 7250 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2246.191 ; gain = 0.000 ; free physical = 481 ; free virtual = 7551 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2246.191 ; gain = 0.000 ; free physical = 437 ; free virtual = 7547 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: d74e1ad3 +INFO: [Common 17-83] Releasing license: Synthesis +66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:13 ; elapsed = 00:01:11 . Memory (MB): peak = 2246.191 ; gain = 978.453 ; free physical = 420 ; free virtual = 7545 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1749.225; main = 1390.368; forked = 381.263 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3237.242; main = 2246.160; forked = 991.082 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2270.168 ; gain = 0.000 ; free physical = 416 ; free virtual = 7543 +INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:34:13 2023... +[Sun Dec 3 18:34:24 2023] synth_1 finished +wait_on_runs: Time (s): cpu = 00:01:39 ; elapsed = 00:01:47 . Memory (MB): peak = 1272.676 ; gain = 0.000 ; free physical = 1438 ; free virtual = 8857 +# open_run synth_1 +Design is defaulting to impl run constrset: constrs_1 +Design is defaulting to synth run part: xc7k160tffv676-1 +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.395 ; gain = 0.000 ; free physical = 817 ; free virtual = 8421 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1768.781 ; gain = 0.000 ; free physical = 700 ; free virtual = 8308 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +open_run: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1771.785 ; gain = 499.109 ; free physical = 698 ; free virtual = 8307 +# report_timing_summary -delay_type min_max -report_unconstrained -max_paths 64 -input_pins -name timing_1 -file filter_synthesis_timing.log +WARNING: [Common 17-708] report_timing_summary: The '-name' option will be ignored because it is only relevant in GUI mode. +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +report_timing_summary: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2340.652 ; gain = 568.867 ; free physical = 212 ; free virtual = 7861 +# report_utilization -file filter_synthesis_utilization.log +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:34:48 2023... diff --git a/ver/comp/exact_match.sv b/ver/comp/exact_match.sv new file mode 100644 index 0000000..1687af2 --- /dev/null +++ b/ver/comp/exact_match.sv @@ -0,0 +1,98 @@ +// exact_match.sv: Model of exact match filtering +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + + + +package match_package; + + class ExactMatch #(KEY, DATA); + + protected bit [KEY-1 : 0] keys[$]; + protected bit [DATA-1 : 0] data[$]; + + function new(); + keys = {}; + data = {}; + endfunction + + function int size(); + return keys.size(); + endfunction + + function bit match(bit [KEY-1 : 0] k, ref bit [DATA-1 : 0] d); + return match_precise(k, d) != keys.size(); + endfunction + + function int match_precise(bit [KEY-1 : 0] k, ref bit [DATA-1 : 0] d); + for(int i=0; i +// +// SPDX-License-Identifier: BSD-3-Clause + + + +class SignalDriver #(WIDTH); + + protected bit enabled; + protected virtual InputSignal #(WIDTH).test vif; + protected mailbox #(bit [WIDTH-1 : 0]) mbox; + + protected rand integer Delay; + protected rand bit DelayEnable; + int DelayLow = 1; + int DelayHigh = 5; + int DelayEnableRatio = 2; + int DelayDisableRatio = 8; + + constraint Delays { + DelayEnable dist { 1'b1 := DelayEnableRatio, 1'b0 := DelayDisableRatio }; + Delay inside { [DelayLow : DelayHigh] }; + } + + function new(virtual InputSignal #(WIDTH).test v); + enabled = 0; + vif = v; + mbox = new(1); + endfunction + + function void start(); + enabled = 1; + fork + run(); + join_none; + endfunction + + function void stop(); + enabled = 0; + endfunction + + task run(); + bit [WIDTH-1 : 0] data; + vif.cb.VALUE <= 0; + vif.cb.VALID <= 0; + @(vif.cb); // initial sync + while(enabled) begin + if(mbox.try_get(data) == 0) begin + vif.cb.VALUE <= 'X; + vif.cb.VALID <= 0; + end else begin + DELAY_RANDOMIZE : assert(randomize()); + if(DelayEnable) begin + vif.cb.VALUE <= 'X; + vif.cb.VALID <= 0; + repeat(Delay) + @(vif.cb); + end + vif.cb.VALUE <= data; + vif.cb.VALID <= 1; + end + @(vif.cb); + end + endtask + + task put(bit [WIDTH-1 : 0] value); + mbox.put(value); + endtask + +endclass diff --git a/ver/comp/signal_interface.sv b/ver/comp/signal_interface.sv new file mode 100644 index 0000000..6a0e44f --- /dev/null +++ b/ver/comp/signal_interface.sv @@ -0,0 +1,40 @@ +// signal_interface.sv: Specification of general data signal interface +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + + + +interface InputSignal #(WIDTH = 32) (input logic CLK, RESET); + + logic [WIDTH-1:0] VALUE; + logic VALID; + + clocking cb @(posedge CLK); + default input #1step output #500ps; + input RESET; + output VALUE, VALID; + endclocking; + + modport dut (input VALUE, VALID); + modport test (clocking cb); + +endinterface + + + +interface OutputSignal #(WIDTH = 32) (input logic CLK, RESET); + + logic [WIDTH-1:0] VALUE; + logic VALID; + + clocking cb @(posedge CLK); + default input #1step output #500ps; + input VALUE, VALID, RESET; + endclocking; + + modport dut (output VALUE, VALID); + modport test (clocking cb); + +endinterface diff --git a/ver/comp/signal_monitor.sv b/ver/comp/signal_monitor.sv new file mode 100644 index 0000000..412157c --- /dev/null +++ b/ver/comp/signal_monitor.sv @@ -0,0 +1,54 @@ +// signal_monitor.sv: Monitor of signal interface +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + + + +class SignalMonitor #(WIDTH); + + protected bit enabled; + protected virtual OutputSignal #(WIDTH).test vif; + protected mailbox #(bit [WIDTH-1 : 0]) mbox; + + function new(virtual OutputSignal #(WIDTH).test v); + enabled = 0; + vif = v; + mbox = new(0); + endfunction + + function void start(); + enabled = 1; + fork + run(); + join_none; + endfunction + + function void stop(); + enabled = 0; + endfunction + + task run(); + @(vif.cb); // initial sync + while(enabled) begin + if(vif.cb.VALID === 1'bX && vif.cb.RESET == 0) begin + $write("ERROR: Signal monitor detected an unitialized value on connected VALID flag! (time %0t ps)\n", $time); + $write("ERROR: Simulation behaviour may be different compared to actual hardware! Stopping ...\n"); + $stop(); + end + if(vif.cb.VALID) + mbox.put(vif.cb.VALUE); + @(vif.cb); + end + endtask + + task get(ref bit [WIDTH-1 : 0] value); + mbox.get(value); + endtask + + function num(); + return mbox.num(); + endfunction + +endclass diff --git a/ver/comp/signal_package.sv b/ver/comp/signal_package.sv new file mode 100644 index 0000000..5453254 --- /dev/null +++ b/ver/comp/signal_package.sv @@ -0,0 +1,14 @@ +// signal_package.sv: Package with signal related verification components +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + +`include "signal_interface.sv" + + + +package signal_package; + `include "signal_driver.sv" + `include "signal_monitor.sv" +endpackage diff --git a/ver/filter.tcl b/ver/filter.tcl new file mode 100644 index 0000000..9a90b0b --- /dev/null +++ b/ver/filter.tcl @@ -0,0 +1,38 @@ +# filter.tcl: Verification execution script for ModelSim +# Copyright (C) 2019 FIT BUT +# Author(s): Lukas Kekely +# +# SPDX-License-Identifier: BSD-3-Clause + + + +# Compile VHDL sources +eval vlib work +vcom -2008 -explicit -work work ../comp/functions.vhd +vcom -2008 -explicit -work work ../comp/block_memory.vhd +vcom -2008 -explicit -work work ../comp/jenkins_mix.vhd +vcom -2008 -explicit -work work ../comp/jenkins_final.vhd +vcom -2008 -explicit -work work ../comp/jenkins_hash.vhd +vcom -2008 -explicit -work work ../filter_ent.vhd +vcom -2008 -explicit -work work ../filter.vhd + +# Compile verification sources +vlog -sv -work work +incdir+comp comp/signal_package.sv +vlog -sv -work work comp/exact_match.sv +vlog -sv -work work test_package.sv +vlog -sv -work work test.sv +vlog -sv -work work testbench.sv + +# Run verification +quit -sim +vsim -t 1ps -lib work testbench +set StdArithNoWarnings 1 + +view wave +delete wave * + +add wave -noupdate -hex /testbench/VHDL_DUT/* +config wave -signalnamewidth 1 + +restart -f +run -all \ No newline at end of file diff --git a/ver/scoreboard.sv b/ver/scoreboard.sv new file mode 100644 index 0000000..b74bd20 --- /dev/null +++ b/ver/scoreboard.sv @@ -0,0 +1,195 @@ +// signal_driver.sv: Driver of signal interface +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + + + +// Exact match filtering model extended for hashing tables using Jenkins hash +class JenkinsHashExactMatch extends ExactMatch #(KEY_WIDTH, DATA_WIDTH); + + `define rot(x,k) (((x)<<(k)) | ((x)>>(32-(k)))) + + `define mix(a,b,c) \ + a = a-c; a = a^`rot(c, 4); c = c+b; \ + b = b-a; b = b^`rot(a, 6); a = a+c; \ + c = c-b; c = c^`rot(b, 8); b = b+a; \ + a = a-c; a = a^`rot(c,16); c = c+b; \ + b = b-a; b = b^`rot(a,19); a = a+c; \ + c = c-b; c = c^`rot(b, 4); b = b+a; + + `define final(a,b,c) \ + c = c^b; c = c-`rot(b,14); \ + a = a^c; a = a-`rot(c,11); \ + b = b^a; b = b-`rot(a,25); \ + c = c^b; c = c-`rot(b,16); \ + a = a^c; a = a-`rot(c,4); \ + b = b^a; b = b-`rot(a,14); \ + c = c^b; c = c-`rot(b,24); + + function int unsigned jenkins_hash_base(int unsigned k[], int unsigned length, int unsigned initval); + int unsigned a,b,c,kk; + /* Set up the internal state */ + a = 32'hdeadbeef + (length<<2) + initval; b = a; c = a; + /*------------------------------------------------- handle most of the key */ + kk = 0; + while (length > 3) begin + a += k[kk+0]; + b += k[kk+1]; + c += k[kk+2]; + `mix(a,b,c) + length = length - 3; + kk = kk + 3; + end + /*------------------------------------------- handle the last 3 uint32_t's */ + /* all the case statements fall through */ + if(length >= 3) c = c + k[kk+2]; + if(length >= 2) b = b + k[kk+1]; + if(length >= 1) a = a + k[kk+0]; + /* case 0: nothing left to add */ + `final(a,b,c) + /*------------------------------------------------------ report the result */ + return c; + endfunction + + function int unsigned jenkins_hash(bit [RULE_WIDTH-1 : 0] r, int unsigned initval); + int unsigned k[KEY_WORDS]; + for(int i = 0; i +// +// SPDX-License-Identifier: BSD-3-Clause + +import test_package::*; +import signal_package::*; +import match_package::*; + +`include "scoreboard.sv" + + + +program TEST ( + input logic CLK, + output logic RESET, + InputSignal.test RX, + OutputSignal.test TX, + InputSignal.test CFG +); + + + + SignalDriver #(KEY_WIDTH) driver; + SignalMonitor #(RULE_WIDTH) monitor; + SignalDriver #(CONFIG_WIDTH) configuration; + JenkinsHashExactMatch model; + Scoreboard score; + + task create(); + driver = new(RX); + monitor = new(TX); + configuration = new(CFG); + configuration.DelayEnableRatio = 0; + model = new(); + score = new(driver, monitor, model); + endtask + + task start(); + driver.start(); + monitor.start(); + configuration.start(); + endtask + + task stop(); + wait(!score.running()); + driver.stop(); + monitor.stop(); + configuration.stop(); + endtask + + task reset(); + RESET = 1; + #RESET_TIME RESET = 0; + endtask + + task configureFilter(); + int rules; + $write("\n\n============================================================\n"); + $write("= Filter Configuration\n"); + $write("============================================================\n"); + model.random_fill(TABLES*TABLE_SIZE, configuration, rules); + $write("%0d random rules generated and configured into DUT\n", rules); + endtask + + task test1(); + $write("\n\n============================================================\n"); + $write("= TEST1: Matching rules only\n"); + $write("============================================================\n"); + for(int i=0; i=0; i--) + score.put(model.get_key(i)); + wait(!score.running()); + $write("Test finished successfully!\n"); + endtask + + task test2(); + bit [KEY_WIDTH-1 : 0] random_key; + $write("\n\n============================================================\n"); + $write("= TEST2: Random rules only\n"); + $write("============================================================\n"); + repeat(TRANSACTIONS) begin + TEST2_RANDOMIZE : assert(std::randomize(random_key)); + score.put(random_key); + end + wait(!score.running()); + $write("Test finished successfully!\n"); + endtask + + task test3(); + bit [KEY_WIDTH-1 : 0] key; + $write("\n\n============================================================\n"); + $write("= TEST3: Mixed rules\n"); + $write("============================================================\n"); + repeat(TRANSACTIONS) begin + if($urandom_range(1024) < 1024*TEST3_FORCE_RATIO) + key = model.get_random_key(); + else + TEST3_RANDOMIZE : assert(std::randomize(key)); + score.put(key); + end + wait(!score.running()); + $write("Test finished successfully!\n"); + endtask + + initial begin + create(); + start(); + reset(); + configureFilter(); + test1(); + test2(); + test3(); + stop(); + score.display(); + $write("\n\nVerification finished successfully!\n"); + $stop(); + end + +endprogram + diff --git a/ver/test_package.sv b/ver/test_package.sv new file mode 100644 index 0000000..205e8f3 --- /dev/null +++ b/ver/test_package.sv @@ -0,0 +1,25 @@ +// test_package.sv: Parameters of the verification run +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + + + +package test_package; + + parameter KEY_WIDTH = 128; + parameter DATA_WIDTH = 32; + parameter TABLES = 4; + parameter TABLE_SIZE = 2048; + + parameter TRANSACTIONS = 20000; + parameter TEST3_FORCE_RATIO = 0.2; + parameter CLK_PERIOD = 5ns; + parameter RESET_TIME = 2 * CLK_PERIOD; + + parameter KEY_WORDS = (KEY_WIDTH-1) / 32 + 1; + parameter RULE_WIDTH = KEY_WIDTH + DATA_WIDTH + 1; + parameter CONFIG_WIDTH = RULE_WIDTH + $clog2(TABLES) + $clog2(TABLE_SIZE); + +endpackage diff --git a/ver/testbench.sv b/ver/testbench.sv new file mode 100644 index 0000000..19a597c --- /dev/null +++ b/ver/testbench.sv @@ -0,0 +1,56 @@ +// testbench.sv: Verification top-level connection of specific DUT +// Copyright (C) 2019 FIT BUT +// Author(s): Lukas Kekely +// +// SPDX-License-Identifier: BSD-3-Clause + +import test_package::*; + + + +module testbench; + + logic clk = 0; + logic reset; + InputSignal #(KEY_WIDTH) rx (clk, reset); + OutputSignal #(RULE_WIDTH) tx (clk, reset); + InputSignal #(CONFIG_WIDTH) cfg (clk, reset); + + + always #(CLK_PERIOD/2) clk = ~clk; + + + filter #( + .KEY_WIDTH (KEY_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .TABLES (TABLES), + .TABLE_SIZE (TABLE_SIZE), + .INPUT_REGISTER (1), + .OUTPUT_REGISTER (1), + .CONFIG_REGISTER (1) + ) VHDL_DUT ( + .CLK (clk), + .RESET (reset), + .INPUT_KEY (rx.VALUE), + .INPUT_VALID (rx.VALID), + .OUTPUT_KEY (tx.VALUE[KEY_WIDTH+DATA_WIDTH : DATA_WIDTH+1]), + .OUTPUT_KEY_FOUND (tx.VALUE[0]), + .OUTPUT_DATA (tx.VALUE[DATA_WIDTH : 1]), + .OUTPUT_VALID (tx.VALID), + .CONFIG_KEY (cfg.VALUE[KEY_WIDTH+DATA_WIDTH : DATA_WIDTH+1]), + .CONFIG_DATA (cfg.VALUE[DATA_WIDTH : 1]), + .CONFIG_EMPTY (cfg.VALUE[0]), + .CONFIG_ADDRESS_TABLE (cfg.VALUE[CONFIG_WIDTH-1 : CONFIG_WIDTH-$clog2(TABLES)]), + .CONFIG_ADDRESS_ITEM (cfg.VALUE[CONFIG_WIDTH-$clog2(TABLES)-1 : CONFIG_WIDTH-$clog2(TABLES)-$clog2(TABLE_SIZE)]), + .CONFIG_WRITE (cfg.VALID) + ); + + TEST TEST_PROGRAM ( + .CLK (clk), + .RESET (reset), + .RX (rx), + .TX (tx), + .CFG (cfg) + ); + +endmodule diff --git a/zadani.pdf b/zadani.pdf new file mode 100644 index 0000000..c0647f7 Binary files /dev/null and b/zadani.pdf differ