#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Dec  3 18:32:16 2023
# Process ID: 16210
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth
# Command line: vivado -mode batch -source filter.tcl
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/vivado.log
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3084.199 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
source filter.tcl
# create_project -part xc7k160tffv676-1 -force filter_vivado
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1265.738 ; gain = 8.930 ; free physical = 200 ; free virtual = 9141
# set_param project.enableVHDL2008 1
# set_property target_language VHDL [current_project]
# set_property enable_vhdl_2008 1 [current_project]
# add_files -norecurse \
#   ../comp/functions.vhd \
#   ../comp/block_memory.vhd \
#   ../comp/jenkins_mix.vhd \
#   ../comp/jenkins_final.vhd \
#   ../comp/jenkins_hash.vhd \
#   ../filter_ent.vhd \
#   ../filter.vhd
# set_property file_type {VHDL 2008} [get_files]
# set_property top filter [current_fileset]
# add_files -fileset constrs_1 filter.xdc
# set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value "-mode out_of_context" -objects [get_runs synth_1]
# launch_runs synth_1
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Sun Dec  3 18:32:37 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
# wait_on_run synth_1
[Sun Dec  3 18:32:37 2023] Waiting for synth_1 to finish...

*** Running vivado
    with args -log filter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl


****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source filter.tcl -notrace
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1267.738 ; gain = 10.930 ; free physical = 159 ; free virtual = 8771
Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t'
INFO: [Device 21-403] Loading part xc7k160tffv676-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 16359
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2031.641 ; gain = 403.715 ; free physical = 146 ; free virtual = 7359
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17]
INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
	Parameter LENGTH bound to: 4 - type: integer 
	Parameter INITVAL bound to: 32'b00000000000000000000000000000001 
INFO: [Synth 8-638] synthesizing module 'jenkins_mix' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42]
	Parameter LENGTH bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'jenkins_mix' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:42]
INFO: [Synth 8-638] synthesizing module 'jenkins_final' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42]
	Parameter LENGTH bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'jenkins_final' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'jenkins_hash' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized0' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
	Parameter LENGTH bound to: 4 - type: integer 
	Parameter INITVAL bound to: 32'b00000000000000000000000000000010 
INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized0' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized1' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
	Parameter LENGTH bound to: 4 - type: integer 
	Parameter INITVAL bound to: 32'b00000000000000000000000000000011 
INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized1' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
INFO: [Synth 8-638] synthesizing module 'jenkins_hash__parameterized2' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
	Parameter LENGTH bound to: 4 - type: integer 
	Parameter INITVAL bound to: 32'b00000000000000000000000000000100 
INFO: [Synth 8-256] done synthesizing module 'jenkins_hash__parameterized2' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45]
	Parameter ITEM_WIDTH bound to: 145 - type: integer 
	Parameter ITEMS bound to: 2048 - type: integer 
	Parameter OUTPUT_REGISTER bound to: 0 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17]
WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2111.609 ; gain = 483.684 ; free physical = 206 ; free virtual = 7213
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2129.422 ; gain = 501.496 ; free physical = 195 ; free virtual = 7202
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2129.422 ; gain = 501.496 ; free physical = 195 ; free virtual = 7202
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2129.422 ; gain = 0.000 ; free physical = 177 ; free virtual = 7203
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2246.156 ; gain = 0.000 ; free physical = 201 ; free virtual = 7190
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2246.191 ; gain = 0.000 ; free physical = 207 ; free virtual = 7192
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 168 ; free virtual = 7165
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tffv676-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 168 ; free virtual = 7165
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 168 ; free virtual = 7165
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 164 ; free virtual = 7159
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   3 Input   32 Bit       Adders := 52    
	   4 Input   32 Bit       Adders := 8     
	   2 Input   32 Bit       Adders := 24    
+---XORs : 
	   2 Input     32 Bit         XORs := 52    
+---Registers : 
	              145 Bit    Registers := 5     
	              128 Bit    Registers := 3     
	               16 Bit    Registers := 1     
	               11 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---RAMs : 
	             290K Bit	(2048 X 145 bit)          RAMs := 4     
+---Muxes : 
	   2 Input   16 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 8     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 600 (col length:100)
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 224 ; free virtual = 7142
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Preliminary Mapping Report (see note below)
+------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object                             | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|filter      | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
|filter      | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
|filter      | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
|filter      | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
+------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 138 ; free virtual = 7118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 206 ; free virtual = 7105
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Final Mapping Report
+------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object                             | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|filter      | storage_generate[0].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
|filter      | storage_generate[1].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
|filter      | storage_generate[2].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
|filter      | storage_generate[3].storage/memory_reg | 2 K x 145(READ_FIRST)  | W |   | 2 K x 145(WRITE_FIRST) |   | R | Port A and B     | 1      | 8      | 
+------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[0].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[1].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[2].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 200 ; free virtual = 7099
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 285 ; free virtual = 7253
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 285 ; free virtual = 7253
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 264 ; free virtual = 7251
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+---------+------+
|      |Cell     |Count |
+------+---------+------+
|1     |CARRY4   |   681|
|2     |LUT1     |   228|
|3     |LUT2     |   874|
|4     |LUT3     |   900|
|5     |LUT4     |   260|
|6     |LUT5     |   995|
|7     |LUT6     |   950|
|8     |RAMB18E1 |     4|
|9     |RAMB36E1 |    32|
|10    |FDRE     |   563|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 259 ; free virtual = 7249
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:56 ; elapsed = 00:00:58 . Memory (MB): peak = 2246.191 ; gain = 501.496 ; free physical = 250 ; free virtual = 7251
Synthesis Optimization Complete : Time (s): cpu = 00:01:00 ; elapsed = 00:01:02 . Memory (MB): peak = 2246.191 ; gain = 618.266 ; free physical = 234 ; free virtual = 7250
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2246.191 ; gain = 0.000 ; free physical = 481 ; free virtual = 7551
INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2246.191 ; gain = 0.000 ; free physical = 437 ; free virtual = 7547
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Synth Design complete | Checksum: d74e1ad3
INFO: [Common 17-83] Releasing license: Synthesis
66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:13 ; elapsed = 00:01:11 . Memory (MB): peak = 2246.191 ; gain = 978.453 ; free physical = 420 ; free virtual = 7545
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1749.225; main = 1390.368; forked = 381.263
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3237.242; main = 2246.160; forked = 991.082
Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2270.168 ; gain = 0.000 ; free physical = 416 ; free virtual = 7543
INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Dec  3 18:34:13 2023...
[Sun Dec  3 18:34:24 2023] synth_1 finished
wait_on_runs: Time (s): cpu = 00:01:39 ; elapsed = 00:01:47 . Memory (MB): peak = 1272.676 ; gain = 0.000 ; free physical = 1438 ; free virtual = 8857
# open_run synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7k160tffv676-1
INFO: [Device 21-403] Loading part xc7k160tffv676-1
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.395 ; gain = 0.000 ; free physical = 817 ; free virtual = 8421
INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1768.781 ; gain = 0.000 ; free physical = 700 ; free virtual = 8308
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1771.785 ; gain = 499.109 ; free physical = 698 ; free virtual = 8307
# report_timing_summary -delay_type min_max -report_unconstrained -max_paths 64 -input_pins -name timing_1 -file filter_synthesis_timing.log
WARNING: [Common 17-708] report_timing_summary: The '-name' option will be ignored because it is only relevant in GUI mode.
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
report_timing_summary: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2340.652 ; gain = 568.867 ; free physical = 212 ; free virtual = 7861
# report_utilization -file filter_synthesis_utilization.log
INFO: [Common 17-206] Exiting Vivado at Sun Dec  3 18:34:48 2023...
