#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Mon Dec  4 22:37:41 2023
# Process ID: 147960
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1
# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
source filter.tcl -notrace
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1309.508 ; gain = 0.023 ; free physical = 428 ; free virtual = 5957
Command: link_design -top filter -part xc7k160tffv676-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7k160tffv676-1
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.383 ; gain = 0.000 ; free physical = 119 ; free virtual = 5562
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1748.727 ; gain = 0.000 ; free physical = 123 ; free virtual = 5292
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1751.730 ; gain = 442.223 ; free physical = 167 ; free virtual = 5285
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1802.523 ; gain = 50.793 ; free physical = 135 ; free virtual = 5244

Starting Cache Timing Information Task
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: c501db34

Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2321.430 ; gain = 518.906 ; free physical = 188 ; free virtual = 4846

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: c501db34

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 124 ; free virtual = 4604

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: c501db34

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 152 ; free virtual = 4603
Phase 1 Initialization | Checksum: c501db34

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 164 ; free virtual = 4604

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: c501db34

Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 199 ; free virtual = 4603

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: c501db34

Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 185 ; free virtual = 4599
Phase 2 Timer Update And Timing Data Collection | Checksum: c501db34

Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 185 ; free virtual = 4599

Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: a3d35512

Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.68 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 133 ; free virtual = 4583
Retarget | Checksum: a3d35512
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: e34d5785

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 151 ; free virtual = 4576
Constant propagation | Checksum: e34d5785
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: e123e2a4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 137 ; free virtual = 4575
Sweep | Checksum: e123e2a4
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: e123e2a4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 127 ; free virtual = 4574
BUFG optimization | Checksum: e123e2a4
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: e123e2a4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 127 ; free virtual = 4574
Shift Register Optimization | Checksum: e123e2a4
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: e123e2a4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 126 ; free virtual = 4578
Post Processing Netlist | Checksum: e123e2a4
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 198845eae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 232 ; free virtual = 4593

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2658.195 ; gain = 0.000 ; free physical = 230 ; free virtual = 4592
Phase 9.2 Verifying Netlist Connectivity | Checksum: 198845eae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 230 ; free virtual = 4592
Phase 9 Finalization | Checksum: 198845eae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 230 ; free virtual = 4592
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 198845eae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 230 ; free virtual = 4592
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2658.195 ; gain = 0.000 ; free physical = 230 ; free virtual = 4592

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 36 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 72
Ending PowerOpt Patch Enables Task | Checksum: 198845eae

Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 174 ; free virtual = 4483
Ending Power Optimization Task | Checksum: 198845eae

Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 140.875 ; free physical = 165 ; free virtual = 4482

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 198845eae

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 165 ; free virtual = 4482

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 154 ; free virtual = 4480
Ending Netlist Obfuscation Task | Checksum: 198845eae

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 154 ; free virtual = 4480
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:46 . Memory (MB): peak = 2799.070 ; gain = 1047.340 ; free physical = 144 ; free virtual = 4480
INFO: [runtcl-4] Executing : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx
Command: report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 161 ; free virtual = 4498
INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 135 ; free virtual = 4509
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d8cd780a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 136 ; free virtual = 4509
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 135 ; free virtual = 4509

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8ad34538

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 186 ; free virtual = 4538

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 148eef814

Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 188 ; free virtual = 4547

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 148eef814

Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 188 ; free virtual = 4547
Phase 1 Placer Initialization | Checksum: 148eef814

Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 188 ; free virtual = 4546

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1133dee1f

Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 182 ; free virtual = 4545

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1708a7738

Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 182 ; free virtual = 4545

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1708a7738

Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 182 ; free virtual = 4545

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 127fd4737

Time (s): cpu = 00:00:27 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 156 ; free virtual = 4535

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 4 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 2 nets or LUTs. Breaked 0 LUT, combined 2 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1402] Pass 1: Identified 59 candidate cells for Shift Register optimization.
INFO: [Physopt 32-775] End 1 Pass. Optimized 37 nets or cells. Created 73 new cells, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |              2  |                     2  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |           73  |              0  |                    37  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           73  |              2  |                    39  |           0  |           9  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 182366011

Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
Phase 2.4 Global Placement Core | Checksum: 1bced18a5

Time (s): cpu = 00:00:31 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
Phase 2 Global Placement | Checksum: 1bced18a5

Time (s): cpu = 00:00:31 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a3664554

Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 139 ; free virtual = 4533

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a922434a

Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 138 ; free virtual = 4533

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 17277ad37

Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 138 ; free virtual = 4533

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 210ee07c3

Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 138 ; free virtual = 4533

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 174a33b00

Time (s): cpu = 00:00:41 ; elapsed = 00:00:18 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 136 ; free virtual = 4531

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1963521b5

Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 123 ; free virtual = 4526

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 11690d3e7

Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 123 ; free virtual = 4525

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 193172d63

Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 123 ; free virtual = 4526

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 143f97dd6

Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 122 ; free virtual = 4525
Phase 3 Detail Placement | Checksum: 143f97dd6

Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 122 ; free virtual = 4525

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1cb7827e6

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.576 | TNS=-25.567 |
Phase 1 Physical Synthesis Initialization | Checksum: 11da6909f

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 120 ; free virtual = 4525
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 11da6909f

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 120 ; free virtual = 4525
Phase 4.1.1.1 BUFG Insertion | Checksum: 1cb7827e6

Time (s): cpu = 00:00:58 ; elapsed = 00:00:26 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 120 ; free virtual = 4525

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1fb5672e7

Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 104 ; free virtual = 4784

Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 102 ; free virtual = 4784
Phase 4.1 Post Commit Optimization | Checksum: 1fb5672e7

Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 109 ; free virtual = 4782
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1fb5672e7

Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 116 ; free virtual = 4781
INFO: [Place 30-491] Placement has been cancelled by the user.
Ending Placer Task | Checksum: 10e3da2ff

Time (s): cpu = 00:01:50 ; elapsed = 00:01:23 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 110 ; free virtual = 4780
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
78 Infos, 6 Warnings, 0 Critical Warnings and 1 Errors encountered.
place_design failed
INFO: [Common 17-344] 'place_design' was cancelled
INFO: [Common 17-344] 'source' was cancelled
INFO: [Common 17-206] Exiting Vivado at Mon Dec  4 22:40:30 2023...
