mirror of
https://github.com/ehw-fit/ariths-gen.git
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102 lines
3.8 KiB
Python
102 lines
3.8 KiB
Python
from wire_components import wire, bus
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from logic_gates import logic_gate, and_gate, nand_gate, or_gate, nor_gate, xor_gate, xnor_gate, not_gate
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from one_bit_circuits import constant_wire_value_1, constant_wire_value_0, half_adder, full_adder
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from multi_bit_circuits import unsigned_ripple_carry_adder, signed_ripple_carry_adder, unsigned_pg_ripple_carry_adder, signed_pg_ripple_carry_adder, unsigned_array_multiplier, signed_array_multiplier, unsigned_dadda_multiplier, signed_dadda_multiplier, unsigned_wallace_multiplier, signed_wallace_multiplier, unsigned_carry_lookahead_adder, signed_carry_lookahead_adder
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import sys
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""" TESTING """
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if __name__ == "__main__":
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N = 4
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a = bus(N=N, prefix="a")
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b = bus(N=1, prefix="b")
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"""
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# RCA
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name = f"u_rca{N}"
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circuit = unsigned_ripple_carry_adder(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_rca{N}"
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circuit = unsigned_ripple_carry_adder(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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#RCA with PG
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name = f"u_pg_rca{N}"
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circuit = unsigned_pg_ripple_carry_adder(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_pg_rca{N}"
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circuit = signed_pg_ripple_carry_adder(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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#CLA with PG
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name = f"u_cla{N}"
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circuit = unsigned_carry_lookahead_adder(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_cla{N}"
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circuit = signed_carry_lookahead_adder(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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# Arrmul
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name = f"u_arrmul{N}"
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circuit = unsigned_array_multiplier(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_arrmul{N}"
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circuit = signed_array_multiplier(a, b, prefix=name)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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# Wallace
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name = f"u_wallace_rca{N}"
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circuit = unsigned_wallace_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_wallace_rca{N}"
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circuit = signed_wallace_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"u_wallace_pg_rca{N}"
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circuit = unsigned_wallace_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_pg_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_wallace_pg_rca{N}"
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circuit = signed_wallace_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_pg_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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# Dadda
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name = f"u_dadda_rca{N}"
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circuit = unsigned_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_dadda_rca{N}"
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circuit = signed_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"u_dadda_pg_rca{N}"
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circuit = unsigned_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_pg_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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name = f"s_dadda_pg_rca{N}"
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circuit = signed_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_pg_ripple_carry_adder)
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circuit.get_cgp_code_flat(open(f"{name}.chr", "w"))
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"""
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w1 = wire(name="a")
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w2 = wire(name="b")
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w3 = wire(name="cin")
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"""
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ha = half_adder(w1, w2, prefix="h_ha")
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ha.get_c_code_hier(open(f"h_ha.c", "w"))
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fa = full_adder(w1, w2, w3, prefix="f_fa")
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fa.get_c_code_hier(open(f"h_fa.c", "w"))
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gate = and_gate(w1, w2)
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""" |