mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-20 05:41:25 +01:00
3 lines
68 B
Verilog
3 lines
68 B
Verilog
module not_gate(input _a, output _y0);
|
|
assign _y0 = ~_a;
|
|
endmodule |