mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-21 22:31:22 +01:00
344 lines
18 KiB
C
344 lines
18 KiB
C
#include <stdio.h>
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#include <stdint.h>
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uint64_t f_u_cla4(uint64_t a, uint64_t b){
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uint8_t out = 0;
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uint8_t a_0 = 0;
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uint8_t a_1 = 0;
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uint8_t a_2 = 0;
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uint8_t a_3 = 0;
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uint8_t b_0 = 0;
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uint8_t b_1 = 0;
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uint8_t b_2 = 0;
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uint8_t b_3 = 0;
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uint8_t constant_wire_value_0_a_0 = 0;
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uint8_t constant_wire_value_0_b_0 = 0;
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uint8_t constant_wire_value_0_y0 = 0;
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uint8_t constant_wire_value_0_y1 = 0;
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uint8_t constant_wire_0 = 0;
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uint8_t f_u_cla4_pg_logic0_a_0 = 0;
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uint8_t f_u_cla4_pg_logic0_b_0 = 0;
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uint8_t f_u_cla4_pg_logic0_y0 = 0;
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uint8_t f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_pg_logic0_y2 = 0;
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uint8_t f_u_cla4_xor0_f_u_cla4_pg_logic0_y2 = 0;
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uint8_t f_u_cla4_xor0_constant_wire_0 = 0;
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uint8_t f_u_cla4_xor0_y0 = 0;
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uint8_t f_u_cla4_and0_f_u_cla4_pg_logic0_y0 = 0;
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uint8_t f_u_cla4_and0_constant_wire_0 = 0;
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uint8_t f_u_cla4_and0_y0 = 0;
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uint8_t f_u_cla4_or0_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_or0_f_u_cla4_and0_y0 = 0;
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uint8_t f_u_cla4_or0_y0 = 0;
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uint8_t f_u_cla4_pg_logic1_a_1 = 0;
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uint8_t f_u_cla4_pg_logic1_b_1 = 0;
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uint8_t f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_pg_logic1_y1 = 0;
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uint8_t f_u_cla4_pg_logic1_y2 = 0;
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uint8_t f_u_cla4_xor1_f_u_cla4_pg_logic1_y2 = 0;
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uint8_t f_u_cla4_xor1_f_u_cla4_or0_y0 = 0;
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uint8_t f_u_cla4_xor1_y0 = 0;
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uint8_t f_u_cla4_and1_f_u_cla4_pg_logic0_y0 = 0;
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uint8_t f_u_cla4_and1_constant_wire_0 = 0;
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uint8_t f_u_cla4_and1_y0 = 0;
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uint8_t f_u_cla4_and2_f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_and2_constant_wire_0 = 0;
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uint8_t f_u_cla4_and2_y0 = 0;
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uint8_t f_u_cla4_and3_f_u_cla4_and2_y0 = 0;
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uint8_t f_u_cla4_and3_f_u_cla4_and1_y0 = 0;
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uint8_t f_u_cla4_and3_y0 = 0;
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uint8_t f_u_cla4_and4_f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_and4_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_and4_y0 = 0;
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uint8_t f_u_cla4_or1_f_u_cla4_and4_y0 = 0;
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uint8_t f_u_cla4_or1_f_u_cla4_and3_y0 = 0;
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uint8_t f_u_cla4_or1_y0 = 0;
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uint8_t f_u_cla4_or2_f_u_cla4_pg_logic1_y1 = 0;
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uint8_t f_u_cla4_or2_f_u_cla4_or1_y0 = 0;
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uint8_t f_u_cla4_or2_y0 = 0;
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uint8_t f_u_cla4_pg_logic2_a_2 = 0;
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uint8_t f_u_cla4_pg_logic2_b_2 = 0;
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uint8_t f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_pg_logic2_y1 = 0;
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uint8_t f_u_cla4_pg_logic2_y2 = 0;
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uint8_t f_u_cla4_xor2_f_u_cla4_pg_logic2_y2 = 0;
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uint8_t f_u_cla4_xor2_f_u_cla4_or2_y0 = 0;
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uint8_t f_u_cla4_xor2_y0 = 0;
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uint8_t f_u_cla4_and5_f_u_cla4_pg_logic0_y0 = 0;
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uint8_t f_u_cla4_and5_constant_wire_0 = 0;
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uint8_t f_u_cla4_and5_y0 = 0;
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uint8_t f_u_cla4_and6_f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_and6_constant_wire_0 = 0;
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uint8_t f_u_cla4_and6_y0 = 0;
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uint8_t f_u_cla4_and7_f_u_cla4_and6_y0 = 0;
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uint8_t f_u_cla4_and7_f_u_cla4_and5_y0 = 0;
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uint8_t f_u_cla4_and7_y0 = 0;
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uint8_t f_u_cla4_and8_f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_and8_constant_wire_0 = 0;
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uint8_t f_u_cla4_and8_y0 = 0;
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uint8_t f_u_cla4_and9_f_u_cla4_and8_y0 = 0;
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uint8_t f_u_cla4_and9_f_u_cla4_and7_y0 = 0;
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uint8_t f_u_cla4_and9_y0 = 0;
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uint8_t f_u_cla4_and10_f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_and10_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_and10_y0 = 0;
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uint8_t f_u_cla4_and11_f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_and11_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_and11_y0 = 0;
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uint8_t f_u_cla4_and12_f_u_cla4_and11_y0 = 0;
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uint8_t f_u_cla4_and12_f_u_cla4_and10_y0 = 0;
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uint8_t f_u_cla4_and12_y0 = 0;
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uint8_t f_u_cla4_and13_f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_and13_f_u_cla4_pg_logic1_y1 = 0;
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uint8_t f_u_cla4_and13_y0 = 0;
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uint8_t f_u_cla4_or3_f_u_cla4_and13_y0 = 0;
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uint8_t f_u_cla4_or3_f_u_cla4_and9_y0 = 0;
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uint8_t f_u_cla4_or3_y0 = 0;
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uint8_t f_u_cla4_or4_f_u_cla4_or3_y0 = 0;
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uint8_t f_u_cla4_or4_f_u_cla4_and12_y0 = 0;
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uint8_t f_u_cla4_or4_y0 = 0;
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uint8_t f_u_cla4_or5_f_u_cla4_pg_logic2_y1 = 0;
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uint8_t f_u_cla4_or5_f_u_cla4_or4_y0 = 0;
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uint8_t f_u_cla4_or5_y0 = 0;
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uint8_t f_u_cla4_pg_logic3_a_3 = 0;
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uint8_t f_u_cla4_pg_logic3_b_3 = 0;
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uint8_t f_u_cla4_pg_logic3_y0 = 0;
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uint8_t f_u_cla4_pg_logic3_y1 = 0;
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uint8_t f_u_cla4_pg_logic3_y2 = 0;
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uint8_t f_u_cla4_xor3_f_u_cla4_pg_logic3_y2 = 0;
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uint8_t f_u_cla4_xor3_f_u_cla4_or5_y0 = 0;
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uint8_t f_u_cla4_xor3_y0 = 0;
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uint8_t f_u_cla4_and14_f_u_cla4_pg_logic0_y0 = 0;
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uint8_t f_u_cla4_and14_constant_wire_0 = 0;
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uint8_t f_u_cla4_and14_y0 = 0;
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uint8_t f_u_cla4_and15_f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_and15_constant_wire_0 = 0;
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uint8_t f_u_cla4_and15_y0 = 0;
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uint8_t f_u_cla4_and16_f_u_cla4_and15_y0 = 0;
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uint8_t f_u_cla4_and16_f_u_cla4_and14_y0 = 0;
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uint8_t f_u_cla4_and16_y0 = 0;
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uint8_t f_u_cla4_and17_f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_and17_constant_wire_0 = 0;
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uint8_t f_u_cla4_and17_y0 = 0;
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uint8_t f_u_cla4_and18_f_u_cla4_and17_y0 = 0;
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uint8_t f_u_cla4_and18_f_u_cla4_and16_y0 = 0;
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uint8_t f_u_cla4_and18_y0 = 0;
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uint8_t f_u_cla4_and19_f_u_cla4_pg_logic3_y0 = 0;
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uint8_t f_u_cla4_and19_constant_wire_0 = 0;
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uint8_t f_u_cla4_and19_y0 = 0;
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uint8_t f_u_cla4_and20_f_u_cla4_and19_y0 = 0;
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uint8_t f_u_cla4_and20_f_u_cla4_and18_y0 = 0;
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uint8_t f_u_cla4_and20_y0 = 0;
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uint8_t f_u_cla4_and21_f_u_cla4_pg_logic1_y0 = 0;
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uint8_t f_u_cla4_and21_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_and21_y0 = 0;
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uint8_t f_u_cla4_and22_f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_and22_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_and22_y0 = 0;
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uint8_t f_u_cla4_and23_f_u_cla4_and22_y0 = 0;
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uint8_t f_u_cla4_and23_f_u_cla4_and21_y0 = 0;
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uint8_t f_u_cla4_and23_y0 = 0;
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uint8_t f_u_cla4_and24_f_u_cla4_pg_logic3_y0 = 0;
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uint8_t f_u_cla4_and24_f_u_cla4_pg_logic0_y1 = 0;
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uint8_t f_u_cla4_and24_y0 = 0;
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uint8_t f_u_cla4_and25_f_u_cla4_and24_y0 = 0;
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uint8_t f_u_cla4_and25_f_u_cla4_and23_y0 = 0;
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uint8_t f_u_cla4_and25_y0 = 0;
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uint8_t f_u_cla4_and26_f_u_cla4_pg_logic2_y0 = 0;
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uint8_t f_u_cla4_and26_f_u_cla4_pg_logic1_y1 = 0;
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uint8_t f_u_cla4_and26_y0 = 0;
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uint8_t f_u_cla4_and27_f_u_cla4_pg_logic3_y0 = 0;
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uint8_t f_u_cla4_and27_f_u_cla4_pg_logic1_y1 = 0;
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uint8_t f_u_cla4_and27_y0 = 0;
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uint8_t f_u_cla4_and28_f_u_cla4_and27_y0 = 0;
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uint8_t f_u_cla4_and28_f_u_cla4_and26_y0 = 0;
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uint8_t f_u_cla4_and28_y0 = 0;
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uint8_t f_u_cla4_and29_f_u_cla4_pg_logic3_y0 = 0;
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uint8_t f_u_cla4_and29_f_u_cla4_pg_logic2_y1 = 0;
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uint8_t f_u_cla4_and29_y0 = 0;
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uint8_t f_u_cla4_or6_f_u_cla4_and29_y0 = 0;
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uint8_t f_u_cla4_or6_f_u_cla4_and20_y0 = 0;
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uint8_t f_u_cla4_or6_y0 = 0;
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uint8_t f_u_cla4_or7_f_u_cla4_or6_y0 = 0;
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uint8_t f_u_cla4_or7_f_u_cla4_and25_y0 = 0;
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uint8_t f_u_cla4_or7_y0 = 0;
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uint8_t f_u_cla4_or8_f_u_cla4_or7_y0 = 0;
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uint8_t f_u_cla4_or8_f_u_cla4_and28_y0 = 0;
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uint8_t f_u_cla4_or8_y0 = 0;
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uint8_t f_u_cla4_or9_f_u_cla4_pg_logic3_y1 = 0;
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uint8_t f_u_cla4_or9_f_u_cla4_or8_y0 = 0;
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uint8_t f_u_cla4_or9_y0 = 0;
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a_0 = ((a >> 0) & 0x01);
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a_1 = ((a >> 1) & 0x01);
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a_2 = ((a >> 2) & 0x01);
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a_3 = ((a >> 3) & 0x01);
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b_0 = ((b >> 0) & 0x01);
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b_1 = ((b >> 1) & 0x01);
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b_2 = ((b >> 2) & 0x01);
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b_3 = ((b >> 3) & 0x01);
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constant_wire_value_0_a_0 = ((a_0 >> 0) & 0x01);
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constant_wire_value_0_b_0 = ((b_0 >> 0) & 0x01);
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constant_wire_value_0_y0 = constant_wire_value_0_a_0 ^ constant_wire_value_0_b_0;
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constant_wire_value_0_y1 = ~(constant_wire_value_0_a_0 ^ constant_wire_value_0_b_0);
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constant_wire_0 = ~(constant_wire_value_0_y0 | constant_wire_value_0_y1);
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f_u_cla4_pg_logic0_a_0 = ((a_0 >> 0) & 0x01);
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f_u_cla4_pg_logic0_b_0 = ((b_0 >> 0) & 0x01);
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f_u_cla4_pg_logic0_y0 = f_u_cla4_pg_logic0_a_0 | f_u_cla4_pg_logic0_b_0;
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f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_a_0 & f_u_cla4_pg_logic0_b_0;
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f_u_cla4_pg_logic0_y2 = f_u_cla4_pg_logic0_a_0 ^ f_u_cla4_pg_logic0_b_0;
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f_u_cla4_xor0_f_u_cla4_pg_logic0_y2 = f_u_cla4_pg_logic0_y2;
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f_u_cla4_xor0_constant_wire_0 = constant_wire_0;
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f_u_cla4_xor0_y0 = f_u_cla4_xor0_f_u_cla4_pg_logic0_y2 ^ f_u_cla4_xor0_constant_wire_0;
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f_u_cla4_and0_f_u_cla4_pg_logic0_y0 = f_u_cla4_pg_logic0_y0;
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f_u_cla4_and0_constant_wire_0 = constant_wire_0;
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f_u_cla4_and0_y0 = f_u_cla4_and0_f_u_cla4_pg_logic0_y0 & f_u_cla4_and0_constant_wire_0;
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f_u_cla4_or0_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_or0_f_u_cla4_and0_y0 = f_u_cla4_and0_y0;
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f_u_cla4_or0_y0 = f_u_cla4_or0_f_u_cla4_pg_logic0_y1 | f_u_cla4_or0_f_u_cla4_and0_y0;
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f_u_cla4_pg_logic1_a_1 = ((a_1 >> 0) & 0x01);
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f_u_cla4_pg_logic1_b_1 = ((b_1 >> 0) & 0x01);
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f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_a_1 | f_u_cla4_pg_logic1_b_1;
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f_u_cla4_pg_logic1_y1 = f_u_cla4_pg_logic1_a_1 & f_u_cla4_pg_logic1_b_1;
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f_u_cla4_pg_logic1_y2 = f_u_cla4_pg_logic1_a_1 ^ f_u_cla4_pg_logic1_b_1;
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f_u_cla4_xor1_f_u_cla4_pg_logic1_y2 = f_u_cla4_pg_logic1_y2;
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f_u_cla4_xor1_f_u_cla4_or0_y0 = f_u_cla4_or0_y0;
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f_u_cla4_xor1_y0 = f_u_cla4_xor1_f_u_cla4_pg_logic1_y2 ^ f_u_cla4_xor1_f_u_cla4_or0_y0;
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f_u_cla4_and1_f_u_cla4_pg_logic0_y0 = f_u_cla4_pg_logic0_y0;
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f_u_cla4_and1_constant_wire_0 = constant_wire_0;
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f_u_cla4_and1_y0 = f_u_cla4_and1_f_u_cla4_pg_logic0_y0 & f_u_cla4_and1_constant_wire_0;
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f_u_cla4_and2_f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_y0;
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f_u_cla4_and2_constant_wire_0 = constant_wire_0;
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f_u_cla4_and2_y0 = f_u_cla4_and2_f_u_cla4_pg_logic1_y0 & f_u_cla4_and2_constant_wire_0;
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f_u_cla4_and3_f_u_cla4_and2_y0 = f_u_cla4_and2_y0;
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f_u_cla4_and3_f_u_cla4_and1_y0 = f_u_cla4_and1_y0;
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f_u_cla4_and3_y0 = f_u_cla4_and3_f_u_cla4_and2_y0 & f_u_cla4_and3_f_u_cla4_and1_y0;
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f_u_cla4_and4_f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_y0;
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f_u_cla4_and4_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_and4_y0 = f_u_cla4_and4_f_u_cla4_pg_logic1_y0 & f_u_cla4_and4_f_u_cla4_pg_logic0_y1;
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f_u_cla4_or1_f_u_cla4_and4_y0 = f_u_cla4_and4_y0;
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f_u_cla4_or1_f_u_cla4_and3_y0 = f_u_cla4_and3_y0;
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f_u_cla4_or1_y0 = f_u_cla4_or1_f_u_cla4_and4_y0 | f_u_cla4_or1_f_u_cla4_and3_y0;
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f_u_cla4_or2_f_u_cla4_pg_logic1_y1 = f_u_cla4_pg_logic1_y1;
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f_u_cla4_or2_f_u_cla4_or1_y0 = f_u_cla4_or1_y0;
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f_u_cla4_or2_y0 = f_u_cla4_or2_f_u_cla4_pg_logic1_y1 | f_u_cla4_or2_f_u_cla4_or1_y0;
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f_u_cla4_pg_logic2_a_2 = ((a_2 >> 0) & 0x01);
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f_u_cla4_pg_logic2_b_2 = ((b_2 >> 0) & 0x01);
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f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_a_2 | f_u_cla4_pg_logic2_b_2;
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f_u_cla4_pg_logic2_y1 = f_u_cla4_pg_logic2_a_2 & f_u_cla4_pg_logic2_b_2;
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f_u_cla4_pg_logic2_y2 = f_u_cla4_pg_logic2_a_2 ^ f_u_cla4_pg_logic2_b_2;
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f_u_cla4_xor2_f_u_cla4_pg_logic2_y2 = f_u_cla4_pg_logic2_y2;
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f_u_cla4_xor2_f_u_cla4_or2_y0 = f_u_cla4_or2_y0;
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f_u_cla4_xor2_y0 = f_u_cla4_xor2_f_u_cla4_pg_logic2_y2 ^ f_u_cla4_xor2_f_u_cla4_or2_y0;
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f_u_cla4_and5_f_u_cla4_pg_logic0_y0 = f_u_cla4_pg_logic0_y0;
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f_u_cla4_and5_constant_wire_0 = constant_wire_0;
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f_u_cla4_and5_y0 = f_u_cla4_and5_f_u_cla4_pg_logic0_y0 & f_u_cla4_and5_constant_wire_0;
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f_u_cla4_and6_f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_y0;
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f_u_cla4_and6_constant_wire_0 = constant_wire_0;
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f_u_cla4_and6_y0 = f_u_cla4_and6_f_u_cla4_pg_logic1_y0 & f_u_cla4_and6_constant_wire_0;
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f_u_cla4_and7_f_u_cla4_and6_y0 = f_u_cla4_and6_y0;
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f_u_cla4_and7_f_u_cla4_and5_y0 = f_u_cla4_and5_y0;
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f_u_cla4_and7_y0 = f_u_cla4_and7_f_u_cla4_and6_y0 & f_u_cla4_and7_f_u_cla4_and5_y0;
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f_u_cla4_and8_f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_y0;
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f_u_cla4_and8_constant_wire_0 = constant_wire_0;
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f_u_cla4_and8_y0 = f_u_cla4_and8_f_u_cla4_pg_logic2_y0 & f_u_cla4_and8_constant_wire_0;
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f_u_cla4_and9_f_u_cla4_and8_y0 = f_u_cla4_and8_y0;
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f_u_cla4_and9_f_u_cla4_and7_y0 = f_u_cla4_and7_y0;
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f_u_cla4_and9_y0 = f_u_cla4_and9_f_u_cla4_and8_y0 & f_u_cla4_and9_f_u_cla4_and7_y0;
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f_u_cla4_and10_f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_y0;
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f_u_cla4_and10_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_and10_y0 = f_u_cla4_and10_f_u_cla4_pg_logic1_y0 & f_u_cla4_and10_f_u_cla4_pg_logic0_y1;
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f_u_cla4_and11_f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_y0;
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f_u_cla4_and11_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_and11_y0 = f_u_cla4_and11_f_u_cla4_pg_logic2_y0 & f_u_cla4_and11_f_u_cla4_pg_logic0_y1;
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f_u_cla4_and12_f_u_cla4_and11_y0 = f_u_cla4_and11_y0;
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f_u_cla4_and12_f_u_cla4_and10_y0 = f_u_cla4_and10_y0;
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f_u_cla4_and12_y0 = f_u_cla4_and12_f_u_cla4_and11_y0 & f_u_cla4_and12_f_u_cla4_and10_y0;
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f_u_cla4_and13_f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_y0;
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f_u_cla4_and13_f_u_cla4_pg_logic1_y1 = f_u_cla4_pg_logic1_y1;
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f_u_cla4_and13_y0 = f_u_cla4_and13_f_u_cla4_pg_logic2_y0 & f_u_cla4_and13_f_u_cla4_pg_logic1_y1;
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f_u_cla4_or3_f_u_cla4_and13_y0 = f_u_cla4_and13_y0;
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f_u_cla4_or3_f_u_cla4_and9_y0 = f_u_cla4_and9_y0;
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f_u_cla4_or3_y0 = f_u_cla4_or3_f_u_cla4_and13_y0 | f_u_cla4_or3_f_u_cla4_and9_y0;
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f_u_cla4_or4_f_u_cla4_or3_y0 = f_u_cla4_or3_y0;
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f_u_cla4_or4_f_u_cla4_and12_y0 = f_u_cla4_and12_y0;
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f_u_cla4_or4_y0 = f_u_cla4_or4_f_u_cla4_or3_y0 | f_u_cla4_or4_f_u_cla4_and12_y0;
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f_u_cla4_or5_f_u_cla4_pg_logic2_y1 = f_u_cla4_pg_logic2_y1;
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f_u_cla4_or5_f_u_cla4_or4_y0 = f_u_cla4_or4_y0;
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f_u_cla4_or5_y0 = f_u_cla4_or5_f_u_cla4_pg_logic2_y1 | f_u_cla4_or5_f_u_cla4_or4_y0;
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f_u_cla4_pg_logic3_a_3 = ((a_3 >> 0) & 0x01);
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f_u_cla4_pg_logic3_b_3 = ((b_3 >> 0) & 0x01);
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f_u_cla4_pg_logic3_y0 = f_u_cla4_pg_logic3_a_3 | f_u_cla4_pg_logic3_b_3;
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f_u_cla4_pg_logic3_y1 = f_u_cla4_pg_logic3_a_3 & f_u_cla4_pg_logic3_b_3;
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f_u_cla4_pg_logic3_y2 = f_u_cla4_pg_logic3_a_3 ^ f_u_cla4_pg_logic3_b_3;
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f_u_cla4_xor3_f_u_cla4_pg_logic3_y2 = f_u_cla4_pg_logic3_y2;
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f_u_cla4_xor3_f_u_cla4_or5_y0 = f_u_cla4_or5_y0;
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f_u_cla4_xor3_y0 = f_u_cla4_xor3_f_u_cla4_pg_logic3_y2 ^ f_u_cla4_xor3_f_u_cla4_or5_y0;
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f_u_cla4_and14_f_u_cla4_pg_logic0_y0 = f_u_cla4_pg_logic0_y0;
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f_u_cla4_and14_constant_wire_0 = constant_wire_0;
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f_u_cla4_and14_y0 = f_u_cla4_and14_f_u_cla4_pg_logic0_y0 & f_u_cla4_and14_constant_wire_0;
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f_u_cla4_and15_f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_y0;
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f_u_cla4_and15_constant_wire_0 = constant_wire_0;
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f_u_cla4_and15_y0 = f_u_cla4_and15_f_u_cla4_pg_logic1_y0 & f_u_cla4_and15_constant_wire_0;
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f_u_cla4_and16_f_u_cla4_and15_y0 = f_u_cla4_and15_y0;
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f_u_cla4_and16_f_u_cla4_and14_y0 = f_u_cla4_and14_y0;
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f_u_cla4_and16_y0 = f_u_cla4_and16_f_u_cla4_and15_y0 & f_u_cla4_and16_f_u_cla4_and14_y0;
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f_u_cla4_and17_f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_y0;
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f_u_cla4_and17_constant_wire_0 = constant_wire_0;
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f_u_cla4_and17_y0 = f_u_cla4_and17_f_u_cla4_pg_logic2_y0 & f_u_cla4_and17_constant_wire_0;
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f_u_cla4_and18_f_u_cla4_and17_y0 = f_u_cla4_and17_y0;
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f_u_cla4_and18_f_u_cla4_and16_y0 = f_u_cla4_and16_y0;
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f_u_cla4_and18_y0 = f_u_cla4_and18_f_u_cla4_and17_y0 & f_u_cla4_and18_f_u_cla4_and16_y0;
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f_u_cla4_and19_f_u_cla4_pg_logic3_y0 = f_u_cla4_pg_logic3_y0;
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f_u_cla4_and19_constant_wire_0 = constant_wire_0;
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f_u_cla4_and19_y0 = f_u_cla4_and19_f_u_cla4_pg_logic3_y0 & f_u_cla4_and19_constant_wire_0;
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f_u_cla4_and20_f_u_cla4_and19_y0 = f_u_cla4_and19_y0;
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f_u_cla4_and20_f_u_cla4_and18_y0 = f_u_cla4_and18_y0;
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f_u_cla4_and20_y0 = f_u_cla4_and20_f_u_cla4_and19_y0 & f_u_cla4_and20_f_u_cla4_and18_y0;
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f_u_cla4_and21_f_u_cla4_pg_logic1_y0 = f_u_cla4_pg_logic1_y0;
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f_u_cla4_and21_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_and21_y0 = f_u_cla4_and21_f_u_cla4_pg_logic1_y0 & f_u_cla4_and21_f_u_cla4_pg_logic0_y1;
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f_u_cla4_and22_f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_y0;
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f_u_cla4_and22_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_and22_y0 = f_u_cla4_and22_f_u_cla4_pg_logic2_y0 & f_u_cla4_and22_f_u_cla4_pg_logic0_y1;
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f_u_cla4_and23_f_u_cla4_and22_y0 = f_u_cla4_and22_y0;
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f_u_cla4_and23_f_u_cla4_and21_y0 = f_u_cla4_and21_y0;
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f_u_cla4_and23_y0 = f_u_cla4_and23_f_u_cla4_and22_y0 & f_u_cla4_and23_f_u_cla4_and21_y0;
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f_u_cla4_and24_f_u_cla4_pg_logic3_y0 = f_u_cla4_pg_logic3_y0;
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f_u_cla4_and24_f_u_cla4_pg_logic0_y1 = f_u_cla4_pg_logic0_y1;
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f_u_cla4_and24_y0 = f_u_cla4_and24_f_u_cla4_pg_logic3_y0 & f_u_cla4_and24_f_u_cla4_pg_logic0_y1;
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f_u_cla4_and25_f_u_cla4_and24_y0 = f_u_cla4_and24_y0;
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f_u_cla4_and25_f_u_cla4_and23_y0 = f_u_cla4_and23_y0;
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f_u_cla4_and25_y0 = f_u_cla4_and25_f_u_cla4_and24_y0 & f_u_cla4_and25_f_u_cla4_and23_y0;
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f_u_cla4_and26_f_u_cla4_pg_logic2_y0 = f_u_cla4_pg_logic2_y0;
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f_u_cla4_and26_f_u_cla4_pg_logic1_y1 = f_u_cla4_pg_logic1_y1;
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f_u_cla4_and26_y0 = f_u_cla4_and26_f_u_cla4_pg_logic2_y0 & f_u_cla4_and26_f_u_cla4_pg_logic1_y1;
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f_u_cla4_and27_f_u_cla4_pg_logic3_y0 = f_u_cla4_pg_logic3_y0;
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f_u_cla4_and27_f_u_cla4_pg_logic1_y1 = f_u_cla4_pg_logic1_y1;
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f_u_cla4_and27_y0 = f_u_cla4_and27_f_u_cla4_pg_logic3_y0 & f_u_cla4_and27_f_u_cla4_pg_logic1_y1;
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f_u_cla4_and28_f_u_cla4_and27_y0 = f_u_cla4_and27_y0;
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f_u_cla4_and28_f_u_cla4_and26_y0 = f_u_cla4_and26_y0;
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f_u_cla4_and28_y0 = f_u_cla4_and28_f_u_cla4_and27_y0 & f_u_cla4_and28_f_u_cla4_and26_y0;
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f_u_cla4_and29_f_u_cla4_pg_logic3_y0 = f_u_cla4_pg_logic3_y0;
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f_u_cla4_and29_f_u_cla4_pg_logic2_y1 = f_u_cla4_pg_logic2_y1;
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f_u_cla4_and29_y0 = f_u_cla4_and29_f_u_cla4_pg_logic3_y0 & f_u_cla4_and29_f_u_cla4_pg_logic2_y1;
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f_u_cla4_or6_f_u_cla4_and29_y0 = f_u_cla4_and29_y0;
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f_u_cla4_or6_f_u_cla4_and20_y0 = f_u_cla4_and20_y0;
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f_u_cla4_or6_y0 = f_u_cla4_or6_f_u_cla4_and29_y0 | f_u_cla4_or6_f_u_cla4_and20_y0;
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f_u_cla4_or7_f_u_cla4_or6_y0 = f_u_cla4_or6_y0;
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f_u_cla4_or7_f_u_cla4_and25_y0 = f_u_cla4_and25_y0;
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f_u_cla4_or7_y0 = f_u_cla4_or7_f_u_cla4_or6_y0 | f_u_cla4_or7_f_u_cla4_and25_y0;
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f_u_cla4_or8_f_u_cla4_or7_y0 = f_u_cla4_or7_y0;
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f_u_cla4_or8_f_u_cla4_and28_y0 = f_u_cla4_and28_y0;
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f_u_cla4_or8_y0 = f_u_cla4_or8_f_u_cla4_or7_y0 | f_u_cla4_or8_f_u_cla4_and28_y0;
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f_u_cla4_or9_f_u_cla4_pg_logic3_y1 = f_u_cla4_pg_logic3_y1;
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|
f_u_cla4_or9_f_u_cla4_or8_y0 = f_u_cla4_or8_y0;
|
|
f_u_cla4_or9_y0 = f_u_cla4_or9_f_u_cla4_pg_logic3_y1 | f_u_cla4_or9_f_u_cla4_or8_y0;
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out |= (f_u_cla4_xor0_y0 & 0x01) << 0;
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out |= (f_u_cla4_xor1_y0 & 0x01) << 1;
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|
out |= (f_u_cla4_xor2_y0 & 0x01) << 2;
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|
out |= (f_u_cla4_xor3_y0 & 0x01) << 3;
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|
out |= (f_u_cla4_or9_y0 & 0x01) << 4;
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return out;
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} |