2021-04-22 20:56:38 +02:00

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.model h_u_rca12
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11]
.outputs out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] out[10] out[11] out[12]
.names a[0] a_0
1 1
.names a[1] a_1
1 1
.names a[2] a_2
1 1
.names a[3] a_3
1 1
.names a[4] a_4
1 1
.names a[5] a_5
1 1
.names a[6] a_6
1 1
.names a[7] a_7
1 1
.names a[8] a_8
1 1
.names a[9] a_9
1 1
.names a[10] a_10
1 1
.names a[11] a_11
1 1
.names b[0] b_0
1 1
.names b[1] b_1
1 1
.names b[2] b_2
1 1
.names b[3] b_3
1 1
.names b[4] b_4
1 1
.names b[5] b_5
1 1
.names b[6] b_6
1 1
.names b[7] b_7
1 1
.names b[8] b_8
1 1
.names b[9] b_9
1 1
.names b[10] b_10
1 1
.names b[11] b_11
1 1
.names a_0 h_u_rca12_ha_a_0
1 1
.names b_0 h_u_rca12_ha_b_0
1 1
.subckt ha a=h_u_rca12_ha_a_0 b=h_u_rca12_ha_b_0 ha_y0=h_u_rca12_ha_y0 ha_y1=h_u_rca12_ha_y1
.names a_1 h_u_rca12_fa1_a_1
1 1
.names b_1 h_u_rca12_fa1_b_1
1 1
.names h_u_rca12_ha_y1 h_u_rca12_fa1_h_u_rca12_ha_y1
1 1
.subckt fa a=h_u_rca12_fa1_a_1 b=h_u_rca12_fa1_b_1 cin=h_u_rca12_fa1_h_u_rca12_ha_y1 fa_y2=h_u_rca12_fa1_y2 fa_y4=h_u_rca12_fa1_y4
.names a_2 h_u_rca12_fa2_a_2
1 1
.names b_2 h_u_rca12_fa2_b_2
1 1
.names h_u_rca12_fa1_y4 h_u_rca12_fa2_h_u_rca12_fa1_y4
1 1
.subckt fa a=h_u_rca12_fa2_a_2 b=h_u_rca12_fa2_b_2 cin=h_u_rca12_fa2_h_u_rca12_fa1_y4 fa_y2=h_u_rca12_fa2_y2 fa_y4=h_u_rca12_fa2_y4
.names a_3 h_u_rca12_fa3_a_3
1 1
.names b_3 h_u_rca12_fa3_b_3
1 1
.names h_u_rca12_fa2_y4 h_u_rca12_fa3_h_u_rca12_fa2_y4
1 1
.subckt fa a=h_u_rca12_fa3_a_3 b=h_u_rca12_fa3_b_3 cin=h_u_rca12_fa3_h_u_rca12_fa2_y4 fa_y2=h_u_rca12_fa3_y2 fa_y4=h_u_rca12_fa3_y4
.names a_4 h_u_rca12_fa4_a_4
1 1
.names b_4 h_u_rca12_fa4_b_4
1 1
.names h_u_rca12_fa3_y4 h_u_rca12_fa4_h_u_rca12_fa3_y4
1 1
.subckt fa a=h_u_rca12_fa4_a_4 b=h_u_rca12_fa4_b_4 cin=h_u_rca12_fa4_h_u_rca12_fa3_y4 fa_y2=h_u_rca12_fa4_y2 fa_y4=h_u_rca12_fa4_y4
.names a_5 h_u_rca12_fa5_a_5
1 1
.names b_5 h_u_rca12_fa5_b_5
1 1
.names h_u_rca12_fa4_y4 h_u_rca12_fa5_h_u_rca12_fa4_y4
1 1
.subckt fa a=h_u_rca12_fa5_a_5 b=h_u_rca12_fa5_b_5 cin=h_u_rca12_fa5_h_u_rca12_fa4_y4 fa_y2=h_u_rca12_fa5_y2 fa_y4=h_u_rca12_fa5_y4
.names a_6 h_u_rca12_fa6_a_6
1 1
.names b_6 h_u_rca12_fa6_b_6
1 1
.names h_u_rca12_fa5_y4 h_u_rca12_fa6_h_u_rca12_fa5_y4
1 1
.subckt fa a=h_u_rca12_fa6_a_6 b=h_u_rca12_fa6_b_6 cin=h_u_rca12_fa6_h_u_rca12_fa5_y4 fa_y2=h_u_rca12_fa6_y2 fa_y4=h_u_rca12_fa6_y4
.names a_7 h_u_rca12_fa7_a_7
1 1
.names b_7 h_u_rca12_fa7_b_7
1 1
.names h_u_rca12_fa6_y4 h_u_rca12_fa7_h_u_rca12_fa6_y4
1 1
.subckt fa a=h_u_rca12_fa7_a_7 b=h_u_rca12_fa7_b_7 cin=h_u_rca12_fa7_h_u_rca12_fa6_y4 fa_y2=h_u_rca12_fa7_y2 fa_y4=h_u_rca12_fa7_y4
.names a_8 h_u_rca12_fa8_a_8
1 1
.names b_8 h_u_rca12_fa8_b_8
1 1
.names h_u_rca12_fa7_y4 h_u_rca12_fa8_h_u_rca12_fa7_y4
1 1
.subckt fa a=h_u_rca12_fa8_a_8 b=h_u_rca12_fa8_b_8 cin=h_u_rca12_fa8_h_u_rca12_fa7_y4 fa_y2=h_u_rca12_fa8_y2 fa_y4=h_u_rca12_fa8_y4
.names a_9 h_u_rca12_fa9_a_9
1 1
.names b_9 h_u_rca12_fa9_b_9
1 1
.names h_u_rca12_fa8_y4 h_u_rca12_fa9_h_u_rca12_fa8_y4
1 1
.subckt fa a=h_u_rca12_fa9_a_9 b=h_u_rca12_fa9_b_9 cin=h_u_rca12_fa9_h_u_rca12_fa8_y4 fa_y2=h_u_rca12_fa9_y2 fa_y4=h_u_rca12_fa9_y4
.names a_10 h_u_rca12_fa10_a_10
1 1
.names b_10 h_u_rca12_fa10_b_10
1 1
.names h_u_rca12_fa9_y4 h_u_rca12_fa10_h_u_rca12_fa9_y4
1 1
.subckt fa a=h_u_rca12_fa10_a_10 b=h_u_rca12_fa10_b_10 cin=h_u_rca12_fa10_h_u_rca12_fa9_y4 fa_y2=h_u_rca12_fa10_y2 fa_y4=h_u_rca12_fa10_y4
.names a_11 h_u_rca12_fa11_a_11
1 1
.names b_11 h_u_rca12_fa11_b_11
1 1
.names h_u_rca12_fa10_y4 h_u_rca12_fa11_h_u_rca12_fa10_y4
1 1
.subckt fa a=h_u_rca12_fa11_a_11 b=h_u_rca12_fa11_b_11 cin=h_u_rca12_fa11_h_u_rca12_fa10_y4 fa_y2=h_u_rca12_fa11_y2 fa_y4=h_u_rca12_fa11_y4
.names h_u_rca12_ha_y0 out[0]
1 1
.names h_u_rca12_fa1_y2 out[1]
1 1
.names h_u_rca12_fa2_y2 out[2]
1 1
.names h_u_rca12_fa3_y2 out[3]
1 1
.names h_u_rca12_fa4_y2 out[4]
1 1
.names h_u_rca12_fa5_y2 out[5]
1 1
.names h_u_rca12_fa6_y2 out[6]
1 1
.names h_u_rca12_fa7_y2 out[7]
1 1
.names h_u_rca12_fa8_y2 out[8]
1 1
.names h_u_rca12_fa9_y2 out[9]
1 1
.names h_u_rca12_fa10_y2 out[10]
1 1
.names h_u_rca12_fa11_y2 out[11]
1 1
.names h_u_rca12_fa11_y4 out[12]
1 1
.end
.model fa
.inputs a b cin
.outputs fa_y2 fa_y4
.names a fa_a
1 1
.names b fa_b
1 1
.names cin fa_cin
1 1
.subckt xor_gate _a=fa_a _b=fa_b _y0=fa_y0
.subckt and_gate _a=fa_a _b=fa_b _y0=fa_y1
.subckt xor_gate _a=fa_y0 _b=fa_cin _y0=fa_y2
.subckt and_gate _a=fa_y0 _b=fa_cin _y0=fa_y3
.subckt or_gate _a=fa_y1 _b=fa_y3 _y0=fa_y4
.end
.model ha
.inputs a b
.outputs ha_y0 ha_y1
.names a ha_a
1 1
.names b ha_b
1 1
.subckt xor_gate _a=ha_a _b=ha_b _y0=ha_y0
.subckt and_gate _a=ha_a _b=ha_b _y0=ha_y1
.end
.model or_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
1- 1
-1 1
.end
.model and_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
11 1
.end
.model xor_gate
.inputs _a _b
.outputs _y0
.names _a _b _y0
01 1
10 1
.end