mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-23 23:31:33 +01:00
283 lines
9.5 KiB
Plaintext
283 lines
9.5 KiB
Plaintext
.model h_s_arrmul4
|
|
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
|
|
.outputs out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7]
|
|
.names a[0] a_0
|
|
1 1
|
|
.names a[1] a_1
|
|
1 1
|
|
.names a[2] a_2
|
|
1 1
|
|
.names a[3] a_3
|
|
1 1
|
|
.names b[0] b_0
|
|
1 1
|
|
.names b[1] b_1
|
|
1 1
|
|
.names b[2] b_2
|
|
1 1
|
|
.names b[3] b_3
|
|
1 1
|
|
.names a_0 constant_wire_value_1_a_0
|
|
1 1
|
|
.names b_0 constant_wire_value_1_b_0
|
|
1 1
|
|
.subckt constant_wire_value_1 a=constant_wire_value_1_a_0 b=constant_wire_value_1_b_0 constant_wire_1=constant_wire_1
|
|
.names a_0 h_s_arrmul4_and0_0_a_0
|
|
1 1
|
|
.names b_0 h_s_arrmul4_and0_0_b_0
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and0_0_a_0 _b=h_s_arrmul4_and0_0_b_0 _y0=h_s_arrmul4_and0_0_y0
|
|
.names a_1 h_s_arrmul4_and1_0_a_1
|
|
1 1
|
|
.names b_0 h_s_arrmul4_and1_0_b_0
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and1_0_a_1 _b=h_s_arrmul4_and1_0_b_0 _y0=h_s_arrmul4_and1_0_y0
|
|
.names a_2 h_s_arrmul4_and2_0_a_2
|
|
1 1
|
|
.names b_0 h_s_arrmul4_and2_0_b_0
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and2_0_a_2 _b=h_s_arrmul4_and2_0_b_0 _y0=h_s_arrmul4_and2_0_y0
|
|
.names a_3 h_s_arrmul4_nand3_0_a_3
|
|
1 1
|
|
.names b_0 h_s_arrmul4_nand3_0_b_0
|
|
1 1
|
|
.subckt nand_gate _a=h_s_arrmul4_nand3_0_a_3 _b=h_s_arrmul4_nand3_0_b_0 _y0=h_s_arrmul4_nand3_0_y0
|
|
.names a_0 h_s_arrmul4_and0_1_a_0
|
|
1 1
|
|
.names b_1 h_s_arrmul4_and0_1_b_1
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and0_1_a_0 _b=h_s_arrmul4_and0_1_b_1 _y0=h_s_arrmul4_and0_1_y0
|
|
.names h_s_arrmul4_and0_1_y0 h_s_arrmul4_ha0_1_h_s_arrmul4_and0_1_y0
|
|
1 1
|
|
.names h_s_arrmul4_and1_0_y0 h_s_arrmul4_ha0_1_h_s_arrmul4_and1_0_y0
|
|
1 1
|
|
.subckt ha a=h_s_arrmul4_ha0_1_h_s_arrmul4_and0_1_y0 b=h_s_arrmul4_ha0_1_h_s_arrmul4_and1_0_y0 ha_y0=h_s_arrmul4_ha0_1_y0 ha_y1=h_s_arrmul4_ha0_1_y1
|
|
.names a_1 h_s_arrmul4_and1_1_a_1
|
|
1 1
|
|
.names b_1 h_s_arrmul4_and1_1_b_1
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and1_1_a_1 _b=h_s_arrmul4_and1_1_b_1 _y0=h_s_arrmul4_and1_1_y0
|
|
.names h_s_arrmul4_and1_1_y0 h_s_arrmul4_fa1_1_h_s_arrmul4_and1_1_y0
|
|
1 1
|
|
.names h_s_arrmul4_and2_0_y0 h_s_arrmul4_fa1_1_h_s_arrmul4_and2_0_y0
|
|
1 1
|
|
.names h_s_arrmul4_ha0_1_y1 h_s_arrmul4_fa1_1_h_s_arrmul4_ha0_1_y1
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa1_1_h_s_arrmul4_and1_1_y0 b=h_s_arrmul4_fa1_1_h_s_arrmul4_and2_0_y0 cin=h_s_arrmul4_fa1_1_h_s_arrmul4_ha0_1_y1 fa_y2=h_s_arrmul4_fa1_1_y2 fa_y4=h_s_arrmul4_fa1_1_y4
|
|
.names a_2 h_s_arrmul4_and2_1_a_2
|
|
1 1
|
|
.names b_1 h_s_arrmul4_and2_1_b_1
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and2_1_a_2 _b=h_s_arrmul4_and2_1_b_1 _y0=h_s_arrmul4_and2_1_y0
|
|
.names h_s_arrmul4_and2_1_y0 h_s_arrmul4_fa2_1_h_s_arrmul4_and2_1_y0
|
|
1 1
|
|
.names h_s_arrmul4_nand3_0_y0 h_s_arrmul4_fa2_1_h_s_arrmul4_nand3_0_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa1_1_y4 h_s_arrmul4_fa2_1_h_s_arrmul4_fa1_1_y4
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa2_1_h_s_arrmul4_and2_1_y0 b=h_s_arrmul4_fa2_1_h_s_arrmul4_nand3_0_y0 cin=h_s_arrmul4_fa2_1_h_s_arrmul4_fa1_1_y4 fa_y2=h_s_arrmul4_fa2_1_y2 fa_y4=h_s_arrmul4_fa2_1_y4
|
|
.names a_3 h_s_arrmul4_nand3_1_a_3
|
|
1 1
|
|
.names b_1 h_s_arrmul4_nand3_1_b_1
|
|
1 1
|
|
.subckt nand_gate _a=h_s_arrmul4_nand3_1_a_3 _b=h_s_arrmul4_nand3_1_b_1 _y0=h_s_arrmul4_nand3_1_y0
|
|
.names h_s_arrmul4_nand3_1_y0 h_s_arrmul4_fa3_1_h_s_arrmul4_nand3_1_y0
|
|
1 1
|
|
.names constant_wire_1 h_s_arrmul4_fa3_1_constant_wire_1
|
|
1 1
|
|
.names h_s_arrmul4_fa2_1_y4 h_s_arrmul4_fa3_1_h_s_arrmul4_fa2_1_y4
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa3_1_h_s_arrmul4_nand3_1_y0 b=h_s_arrmul4_fa3_1_constant_wire_1 cin=h_s_arrmul4_fa3_1_h_s_arrmul4_fa2_1_y4 fa_y2=h_s_arrmul4_fa3_1_y2 fa_y4=h_s_arrmul4_fa3_1_y4
|
|
.names a_0 h_s_arrmul4_and0_2_a_0
|
|
1 1
|
|
.names b_2 h_s_arrmul4_and0_2_b_2
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and0_2_a_0 _b=h_s_arrmul4_and0_2_b_2 _y0=h_s_arrmul4_and0_2_y0
|
|
.names h_s_arrmul4_and0_2_y0 h_s_arrmul4_ha0_2_h_s_arrmul4_and0_2_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa1_1_y2 h_s_arrmul4_ha0_2_h_s_arrmul4_fa1_1_y2
|
|
1 1
|
|
.subckt ha a=h_s_arrmul4_ha0_2_h_s_arrmul4_and0_2_y0 b=h_s_arrmul4_ha0_2_h_s_arrmul4_fa1_1_y2 ha_y0=h_s_arrmul4_ha0_2_y0 ha_y1=h_s_arrmul4_ha0_2_y1
|
|
.names a_1 h_s_arrmul4_and1_2_a_1
|
|
1 1
|
|
.names b_2 h_s_arrmul4_and1_2_b_2
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and1_2_a_1 _b=h_s_arrmul4_and1_2_b_2 _y0=h_s_arrmul4_and1_2_y0
|
|
.names h_s_arrmul4_and1_2_y0 h_s_arrmul4_fa1_2_h_s_arrmul4_and1_2_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa2_1_y2 h_s_arrmul4_fa1_2_h_s_arrmul4_fa2_1_y2
|
|
1 1
|
|
.names h_s_arrmul4_ha0_2_y1 h_s_arrmul4_fa1_2_h_s_arrmul4_ha0_2_y1
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa1_2_h_s_arrmul4_and1_2_y0 b=h_s_arrmul4_fa1_2_h_s_arrmul4_fa2_1_y2 cin=h_s_arrmul4_fa1_2_h_s_arrmul4_ha0_2_y1 fa_y2=h_s_arrmul4_fa1_2_y2 fa_y4=h_s_arrmul4_fa1_2_y4
|
|
.names a_2 h_s_arrmul4_and2_2_a_2
|
|
1 1
|
|
.names b_2 h_s_arrmul4_and2_2_b_2
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and2_2_a_2 _b=h_s_arrmul4_and2_2_b_2 _y0=h_s_arrmul4_and2_2_y0
|
|
.names h_s_arrmul4_and2_2_y0 h_s_arrmul4_fa2_2_h_s_arrmul4_and2_2_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa3_1_y2 h_s_arrmul4_fa2_2_h_s_arrmul4_fa3_1_y2
|
|
1 1
|
|
.names h_s_arrmul4_fa1_2_y4 h_s_arrmul4_fa2_2_h_s_arrmul4_fa1_2_y4
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa2_2_h_s_arrmul4_and2_2_y0 b=h_s_arrmul4_fa2_2_h_s_arrmul4_fa3_1_y2 cin=h_s_arrmul4_fa2_2_h_s_arrmul4_fa1_2_y4 fa_y2=h_s_arrmul4_fa2_2_y2 fa_y4=h_s_arrmul4_fa2_2_y4
|
|
.names a_3 h_s_arrmul4_nand3_2_a_3
|
|
1 1
|
|
.names b_2 h_s_arrmul4_nand3_2_b_2
|
|
1 1
|
|
.subckt nand_gate _a=h_s_arrmul4_nand3_2_a_3 _b=h_s_arrmul4_nand3_2_b_2 _y0=h_s_arrmul4_nand3_2_y0
|
|
.names h_s_arrmul4_nand3_2_y0 h_s_arrmul4_fa3_2_h_s_arrmul4_nand3_2_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa3_1_y4 h_s_arrmul4_fa3_2_h_s_arrmul4_fa3_1_y4
|
|
1 1
|
|
.names h_s_arrmul4_fa2_2_y4 h_s_arrmul4_fa3_2_h_s_arrmul4_fa2_2_y4
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa3_2_h_s_arrmul4_nand3_2_y0 b=h_s_arrmul4_fa3_2_h_s_arrmul4_fa3_1_y4 cin=h_s_arrmul4_fa3_2_h_s_arrmul4_fa2_2_y4 fa_y2=h_s_arrmul4_fa3_2_y2 fa_y4=h_s_arrmul4_fa3_2_y4
|
|
.names a_0 h_s_arrmul4_nand0_3_a_0
|
|
1 1
|
|
.names b_3 h_s_arrmul4_nand0_3_b_3
|
|
1 1
|
|
.subckt nand_gate _a=h_s_arrmul4_nand0_3_a_0 _b=h_s_arrmul4_nand0_3_b_3 _y0=h_s_arrmul4_nand0_3_y0
|
|
.names h_s_arrmul4_nand0_3_y0 h_s_arrmul4_ha0_3_h_s_arrmul4_nand0_3_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa1_2_y2 h_s_arrmul4_ha0_3_h_s_arrmul4_fa1_2_y2
|
|
1 1
|
|
.subckt ha a=h_s_arrmul4_ha0_3_h_s_arrmul4_nand0_3_y0 b=h_s_arrmul4_ha0_3_h_s_arrmul4_fa1_2_y2 ha_y0=h_s_arrmul4_ha0_3_y0 ha_y1=h_s_arrmul4_ha0_3_y1
|
|
.names a_1 h_s_arrmul4_nand1_3_a_1
|
|
1 1
|
|
.names b_3 h_s_arrmul4_nand1_3_b_3
|
|
1 1
|
|
.subckt nand_gate _a=h_s_arrmul4_nand1_3_a_1 _b=h_s_arrmul4_nand1_3_b_3 _y0=h_s_arrmul4_nand1_3_y0
|
|
.names h_s_arrmul4_nand1_3_y0 h_s_arrmul4_fa1_3_h_s_arrmul4_nand1_3_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa2_2_y2 h_s_arrmul4_fa1_3_h_s_arrmul4_fa2_2_y2
|
|
1 1
|
|
.names h_s_arrmul4_ha0_3_y1 h_s_arrmul4_fa1_3_h_s_arrmul4_ha0_3_y1
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa1_3_h_s_arrmul4_nand1_3_y0 b=h_s_arrmul4_fa1_3_h_s_arrmul4_fa2_2_y2 cin=h_s_arrmul4_fa1_3_h_s_arrmul4_ha0_3_y1 fa_y2=h_s_arrmul4_fa1_3_y2 fa_y4=h_s_arrmul4_fa1_3_y4
|
|
.names a_2 h_s_arrmul4_nand2_3_a_2
|
|
1 1
|
|
.names b_3 h_s_arrmul4_nand2_3_b_3
|
|
1 1
|
|
.subckt nand_gate _a=h_s_arrmul4_nand2_3_a_2 _b=h_s_arrmul4_nand2_3_b_3 _y0=h_s_arrmul4_nand2_3_y0
|
|
.names h_s_arrmul4_nand2_3_y0 h_s_arrmul4_fa2_3_h_s_arrmul4_nand2_3_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa3_2_y2 h_s_arrmul4_fa2_3_h_s_arrmul4_fa3_2_y2
|
|
1 1
|
|
.names h_s_arrmul4_fa1_3_y4 h_s_arrmul4_fa2_3_h_s_arrmul4_fa1_3_y4
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa2_3_h_s_arrmul4_nand2_3_y0 b=h_s_arrmul4_fa2_3_h_s_arrmul4_fa3_2_y2 cin=h_s_arrmul4_fa2_3_h_s_arrmul4_fa1_3_y4 fa_y2=h_s_arrmul4_fa2_3_y2 fa_y4=h_s_arrmul4_fa2_3_y4
|
|
.names a_3 h_s_arrmul4_and3_3_a_3
|
|
1 1
|
|
.names b_3 h_s_arrmul4_and3_3_b_3
|
|
1 1
|
|
.subckt and_gate _a=h_s_arrmul4_and3_3_a_3 _b=h_s_arrmul4_and3_3_b_3 _y0=h_s_arrmul4_and3_3_y0
|
|
.names h_s_arrmul4_and3_3_y0 h_s_arrmul4_fa3_3_h_s_arrmul4_and3_3_y0
|
|
1 1
|
|
.names h_s_arrmul4_fa3_2_y4 h_s_arrmul4_fa3_3_h_s_arrmul4_fa3_2_y4
|
|
1 1
|
|
.names h_s_arrmul4_fa2_3_y4 h_s_arrmul4_fa3_3_h_s_arrmul4_fa2_3_y4
|
|
1 1
|
|
.subckt fa a=h_s_arrmul4_fa3_3_h_s_arrmul4_and3_3_y0 b=h_s_arrmul4_fa3_3_h_s_arrmul4_fa3_2_y4 cin=h_s_arrmul4_fa3_3_h_s_arrmul4_fa2_3_y4 fa_y2=h_s_arrmul4_fa3_3_y2 fa_y4=h_s_arrmul4_fa3_3_y4
|
|
.names h_s_arrmul4_fa3_3_y4 h_s_arrmul4_xor4_3_h_s_arrmul4_fa3_3_y4
|
|
1 1
|
|
.names constant_wire_1 h_s_arrmul4_xor4_3_constant_wire_1
|
|
1 1
|
|
.subckt xor_gate _a=h_s_arrmul4_xor4_3_h_s_arrmul4_fa3_3_y4 _b=h_s_arrmul4_xor4_3_constant_wire_1 _y0=h_s_arrmul4_xor4_3_y0
|
|
.names h_s_arrmul4_and0_0_y0 out[0]
|
|
1 1
|
|
.names h_s_arrmul4_ha0_1_y0 out[1]
|
|
1 1
|
|
.names h_s_arrmul4_ha0_2_y0 out[2]
|
|
1 1
|
|
.names h_s_arrmul4_ha0_3_y0 out[3]
|
|
1 1
|
|
.names h_s_arrmul4_fa1_3_y2 out[4]
|
|
1 1
|
|
.names h_s_arrmul4_fa2_3_y2 out[5]
|
|
1 1
|
|
.names h_s_arrmul4_fa3_3_y2 out[6]
|
|
1 1
|
|
.names h_s_arrmul4_xor4_3_y0 out[7]
|
|
1 1
|
|
.end
|
|
|
|
.model fa
|
|
.inputs a b cin
|
|
.outputs fa_y2 fa_y4
|
|
.names a fa_a
|
|
1 1
|
|
.names b fa_b
|
|
1 1
|
|
.names cin fa_cin
|
|
1 1
|
|
.subckt xor_gate _a=fa_a _b=fa_b _y0=fa_y0
|
|
.subckt and_gate _a=fa_a _b=fa_b _y0=fa_y1
|
|
.subckt xor_gate _a=fa_y0 _b=fa_cin _y0=fa_y2
|
|
.subckt and_gate _a=fa_y0 _b=fa_cin _y0=fa_y3
|
|
.subckt or_gate _a=fa_y1 _b=fa_y3 _y0=fa_y4
|
|
.end
|
|
|
|
.model ha
|
|
.inputs a b
|
|
.outputs ha_y0 ha_y1
|
|
.names a ha_a
|
|
1 1
|
|
.names b ha_b
|
|
1 1
|
|
.subckt xor_gate _a=ha_a _b=ha_b _y0=ha_y0
|
|
.subckt and_gate _a=ha_a _b=ha_b _y0=ha_y1
|
|
.end
|
|
|
|
.model constant_wire_value_1
|
|
.inputs a b
|
|
.outputs constant_wire_1
|
|
.names a constant_wire_value_1_a
|
|
1 1
|
|
.names b constant_wire_value_1_b
|
|
1 1
|
|
.subckt xor_gate _a=constant_wire_value_1_a _b=constant_wire_value_1_b _y0=constant_wire_value_1_y0
|
|
.subckt xnor_gate _a=constant_wire_value_1_a _b=constant_wire_value_1_b _y0=constant_wire_value_1_y1
|
|
.subckt or_gate _a=constant_wire_value_1_y0 _b=constant_wire_value_1_y1 _y0=constant_wire_1
|
|
.end
|
|
|
|
.model nand_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
0- 1
|
|
-0 1
|
|
.end
|
|
|
|
.model and_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
11 1
|
|
.end
|
|
|
|
.model or_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
1- 1
|
|
-1 1
|
|
.end
|
|
|
|
.model xnor_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
00 1
|
|
11 1
|
|
.end
|
|
|
|
.model xor_gate
|
|
.inputs _a _b
|
|
.outputs _y0
|
|
.names _a _b _y0
|
|
01 1
|
|
10 1
|
|
.end
|