mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-19 13:30:56 +01:00
258 lines
12 KiB
Python
258 lines
12 KiB
Python
from logic_gates import logic_gate, and_gate, nand_gate, or_gate, nor_gate, xor_gate, xnor_gate, not_gate
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from wire_components import wire, bus
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import itertools
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""" ARITHMETIC CIRCUITS """
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class arithmetic_circuit():
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def __init__(self):
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self.components = []
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self.circuit_wires = []
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self.circuit_gates = []
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self.c_data_type = "uint64_t"
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self.N = 1
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def add_component(self, component):
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self.components.append(component)
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def get_previous_component(self, number: int = 1):
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return self.components[-number]
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def get_component_types(self):
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return list({type(c): c for c in self.components}.values())
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def get_unique_types(self):
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hier_components = self.components_gates + self.component_types
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return list({type(c): c for c in hier_components}.values())
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def get_gate_types(self):
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return list({type(g): g for g in self.components_gates}.values())
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def get_sum_wire(self):
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return self.out.get_wire(0)
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def get_carry_wire(self):
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return self.out.get_wire(1)
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def get_circuit_wires(self):
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self.circuit_wires = []
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if item[1] == component.out.name]:
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self.circuit_wires.append((component.out, component.out.name, len(self.circuit_wires)))
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# Search for circuit's wire unique index for cgp chromosome generation
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def get_circuit_wire_index(self, wire: wire):
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for w in self.circuit_wires:
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if wire.name.endswith(w[1]):
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return w[2]
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# Get list of all gates present in circuit
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def get_circuit_gates(self):
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gates = []
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for c in self.components:
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if isinstance(c, logic_gate):
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gates.append(c)
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else:
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gates.extend((c.get_circuit_gates()))
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return gates
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# Get list of all wires in circuit along with their index position for cgp chromosome generation
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def get_cgp_wires(self):
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self.circuit_wires = []
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if isinstance(self.a, bus):
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[self.circuit_wires.append((w, f"_{w.name}", len(self.circuit_wires))) for w in self.a.bus]
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[self.circuit_wires.append((w, f"_{w.name}", len(self.circuit_wires))) for w in self.b.bus]
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else:
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self.circuit_wires.append((self.a, f"_{self.a.name}", len(self.circuit_wires)))
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self.circuit_wires.append((self.b, f"_{self.b.name}", len(self.circuit_wires)))
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if hasattr(self, 'c'):
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self.circuit_wires.append((self.c, f"_{self.c.name}", len(self.circuit_wires)))
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for gate in self.circuit_gates:
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if not [item for item in self.circuit_wires if gate.a.name.endswith(item[1])]:
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self.circuit_wires.append((gate.a, gate.a.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if gate.b.name.endswith(item[1])]:
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self.circuit_wires.append((gate.b, gate.b.name, len(self.circuit_wires)))
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if not [item for item in self.circuit_wires if gate.out.name.endswith(item[1])]:
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self.circuit_wires.append((gate.out, gate.out.name, len(self.circuit_wires)))
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + "\n"
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def get_declaration_c_flat(self):
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return f"{self.a.get_wire_declaration_c()}" + \
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f"{self.b.get_wire_declaration_c()}" + \
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f"".join([c.get_declaration_c_flat() for c in self.components])
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def get_init_c_flat(self):
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return f"{self.a.get_wire_assign_c()}" + \
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f"{self.b.get_wire_assign_c()}" + \
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"".join([c.get_assign_c_flat() if isinstance(c, logic_gate) else c.get_init_c_flat() for c in self.components])
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def get_function_out_c_flat(self):
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return "".join([f" {self.out.prefix} |= {o.return_wire_value_c(offset=self.out.bus.index(o))};\n" for o in self.out.bus])
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# Generating flat C code representation of circuit
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def get_c_code_flat(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(self.out.get_declaration_c())
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file_object.write(self.get_declaration_c_flat()+"\n")
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file_object.write(self.get_init_c_flat()+"\n")
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file_object.write(self.get_function_out_c_flat())
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C #
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def get_function_blocks_c(self):
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# Add unique 1-bit adder components (ha, fa)
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self.component_types = self.get_component_types()
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# Add unique logic gates composing subcomponents
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self.components_gates = list(itertools.chain.from_iterable([c.get_component_types() for c in self.component_types]))
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self.component_types = self.get_unique_types()
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return "".join([c.get_function_block_c() for c in self.component_types])
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def get_declaration_c_hier(self):
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return "".join(self.a.get_wire_declaration_c()) + \
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"".join(self.b.get_wire_declaration_c()) + \
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"".join([c.out.get_declaration_c() if isinstance(c, logic_gate) else c.out.get_wire_declaration_c() for c in self.components])
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def get_init_c_hier(self):
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return f"{self.a.get_wire_assign_c()}" + \
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f"{self.b.get_wire_assign_c()}" + \
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"".join([f" {c.out.name} = {c.get_gate_invocation_c()}" if isinstance(c, logic_gate) else c.get_out_invocation_c() for c in self.components])
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def get_function_out_c_hier(self):
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return "".join([f" {self.out.prefix} |= {o.return_wire_value_c(offset=self.out.bus.index(o))};\n" for o in self.out.bus])
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def get_circuit_c(self):
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return f"{self.get_prototype_c()}" + \
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f"{self.out.get_declaration_c()}" + \
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f"{self.get_declaration_c_hier()}\n" + \
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f"{self.get_init_c_hier()}\n" + \
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f"{self.get_function_out_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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# Generating hierarchical C code representation of circuit
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def get_c_code_hier(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_function_blocks_c())
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file_object.write(self.get_circuit_c())
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file_object.close()
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.out.N-1}:0] {self.out.prefix});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_wire_declaration_v()}" + \
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f"{self.b.get_wire_declaration_v()}" + \
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f"".join([c.get_declaration_v_flat() for c in self.components])
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def get_init_v_flat(self):
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return f"{self.a.get_wire_assign_v()}" + \
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f"{self.b.get_wire_assign_v()}" + \
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"".join([c.get_assign_v_flat() if isinstance(c, logic_gate) else c.get_init_v_flat() for c in self.components]) + "\n"
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def get_function_out_v_flat(self):
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return "".join([f" assign {self.out.prefix}[{self.out.bus.index(o)}] = {o.prefix};\n" for o in self.out.bus])
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# Generating flat V code representation of circuit
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def get_v_code_flat(self, file_object):
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file_object.write(self.get_prototype_v())
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file_object.write(self.get_declaration_v_flat()+"\n")
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file_object.write(self.get_init_v_flat())
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file_object.write(self.get_function_out_v_flat())
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file_object.write(f"endmodule")
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file_object.close()
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# HIERARCHICAL VERILOG #
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def get_function_blocks_v(self):
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# Add unique 1-bit adder components (ha, fa)
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self.component_types = self.get_component_types()
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# Add unique logic gates composing subcomponents
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self.components_gates = list(itertools.chain.from_iterable([c.get_component_types() for c in self.component_types]))
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self.component_types = self.get_unique_types()
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return "".join([c.get_function_block_v() for c in self.component_types])
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def get_declaration_v_hier(self):
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return "".join(self.a.get_wire_declaration_v()) + \
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"".join(self.b.get_wire_declaration_v()) + \
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"".join([c.out.get_declaration_v() if isinstance(c, logic_gate) else c.out.get_wire_declaration_v() for c in self.components])
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def get_init_v_hier(self):
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return f"{self.a.get_wire_assign_v()}" + \
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f"{self.b.get_wire_assign_v()}" + \
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"".join([f"{c.get_gate_invocation_v()}" if isinstance(c, logic_gate) else c.get_invocation_v() for c in self.components])
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def get_function_out_v_hier(self):
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return "".join([f" assign {self.out.prefix}[{self.out.bus.index(o)}] = {o.name};\n" for o in self.out.bus])
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def get_circuit_v(self):
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return f"{self.get_prototype_v()}" + \
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f"{self.get_declaration_v_hier()}\n" + \
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f"{self.get_init_v_hier()}\n" + \
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f"{self.get_function_out_v_hier()}" + \
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f"endmodule"
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# Generating hierarchical C code representation of circuit
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def get_v_code_hier(self, file_object):
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file_object.write(self.get_function_blocks_v())
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file_object.write(self.get_circuit_v())
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file_object.close()
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""" CGP CODE GENERATION """
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# FLAT CGP #
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def get_parameters_cgp(self):
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self.circuit_gates = self.get_circuit_gates()
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return f"{{1,{len(self.circuit_gates)},2,1,0}}"
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def get_triplet_cgp(self):
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self.get_cgp_wires()
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return "".join([g.get_triplet_cgp(a_index=self.get_circuit_wire_index(g.a), b_index=self.get_circuit_wire_index(g.b)) for g in self.circuit_gates])
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def get_output_cgp(self):
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return "(" + ",".join([str(self.get_circuit_wire_index(o)) for o in self.out.bus[::-1]]) + ")"
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def get_cgp_code(self, file_object):
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file_object.write(self.get_parameters_cgp())
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file_object.write(self.get_triplet_cgp())
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file_object.write(self.get_output_cgp())
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file_object.close()
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""" MULTIPLIER CIRCUITS """
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class multiplier_circuit(arithmetic_circuit):
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def __init__(self):
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super().__init__()
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def get_previous_partial_product(self, a_index: int, b_index: int, offset: int = 0):
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# To get the index of previous row's connecting adder and its generated pp
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index = ((b_index-2) * (self.N*2)) + ((self.N-1)+2*(a_index+2)) + offset
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# Get carry wire as input for the last adder in current row
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if a_index == self.N-1:
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index = index-2
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return self.components[index].get_carry_wire()
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# Get sum wire as input for current adder
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else:
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return self.components[index].get_sum_wire()
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