mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-21 22:31:22 +01:00
201 lines
12 KiB
Verilog
201 lines
12 KiB
Verilog
module and_gate(input a, input b, output out);
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assign out = a & b;
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endmodule
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module nand_gate(input a, input b, output out);
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assign out = ~(a & b);
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endmodule
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module xor_gate(input a, input b, output out);
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assign out = a ^ b;
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endmodule
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module not_gate(input a, output out);
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assign out = ~a;
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endmodule
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module or_gate(input a, input b, output out);
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assign out = a | b;
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endmodule
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module ha(input [0:0] a, input [0:0] b, output [0:0] ha_xor0, output [0:0] ha_and0);
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xor_gate xor_gate_ha_xor0(.a(a[0]), .b(b[0]), .out(ha_xor0));
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and_gate and_gate_ha_and0(.a(a[0]), .b(b[0]), .out(ha_and0));
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endmodule
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module fa(input [0:0] a, input [0:0] b, input [0:0] cin, output [0:0] fa_xor1, output [0:0] fa_or0);
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wire [0:0] fa_xor0;
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wire [0:0] fa_and0;
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wire [0:0] fa_and1;
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xor_gate xor_gate_fa_xor0(.a(a[0]), .b(b[0]), .out(fa_xor0));
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and_gate and_gate_fa_and0(.a(a[0]), .b(b[0]), .out(fa_and0));
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xor_gate xor_gate_fa_xor1(.a(fa_xor0[0]), .b(cin[0]), .out(fa_xor1));
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and_gate and_gate_fa_and1(.a(fa_xor0[0]), .b(cin[0]), .out(fa_and1));
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or_gate or_gate_fa_or0(.a(fa_and0[0]), .b(fa_and1[0]), .out(fa_or0));
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endmodule
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module pg_logic(input [0:0] a, input [0:0] b, output [0:0] pg_logic_or0, output [0:0] pg_logic_and0, output [0:0] pg_logic_xor0);
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or_gate or_gate_pg_logic_or0(.a(a[0]), .b(b[0]), .out(pg_logic_or0));
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and_gate and_gate_pg_logic_and0(.a(a[0]), .b(b[0]), .out(pg_logic_and0));
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xor_gate xor_gate_pg_logic_xor0(.a(a[0]), .b(b[0]), .out(pg_logic_xor0));
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endmodule
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module u_cla4(input [3:0] a, input [3:0] b, output [4:0] u_cla4_out);
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wire [0:0] u_cla4_pg_logic0_or0;
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wire [0:0] u_cla4_pg_logic0_and0;
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wire [0:0] u_cla4_pg_logic0_xor0;
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wire [0:0] u_cla4_pg_logic1_or0;
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wire [0:0] u_cla4_pg_logic1_and0;
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wire [0:0] u_cla4_pg_logic1_xor0;
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wire [0:0] u_cla4_xor1;
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wire [0:0] u_cla4_and0;
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wire [0:0] u_cla4_or0;
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wire [0:0] u_cla4_pg_logic2_or0;
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wire [0:0] u_cla4_pg_logic2_and0;
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wire [0:0] u_cla4_pg_logic2_xor0;
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wire [0:0] u_cla4_xor2;
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wire [0:0] u_cla4_and1;
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wire [0:0] u_cla4_and2;
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wire [0:0] u_cla4_and3;
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wire [0:0] u_cla4_and4;
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wire [0:0] u_cla4_or1;
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wire [0:0] u_cla4_or2;
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wire [0:0] u_cla4_pg_logic3_or0;
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wire [0:0] u_cla4_pg_logic3_and0;
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wire [0:0] u_cla4_pg_logic3_xor0;
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wire [0:0] u_cla4_xor3;
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wire [0:0] u_cla4_and5;
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wire [0:0] u_cla4_and6;
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wire [0:0] u_cla4_and7;
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wire [0:0] u_cla4_and8;
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wire [0:0] u_cla4_and9;
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wire [0:0] u_cla4_and10;
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wire [0:0] u_cla4_and11;
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wire [0:0] u_cla4_or3;
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wire [0:0] u_cla4_or4;
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wire [0:0] u_cla4_or5;
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pg_logic pg_logic_u_cla4_pg_logic0_out(.a(a[0]), .b(b[0]), .pg_logic_or0(u_cla4_pg_logic0_or0), .pg_logic_and0(u_cla4_pg_logic0_and0), .pg_logic_xor0(u_cla4_pg_logic0_xor0));
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pg_logic pg_logic_u_cla4_pg_logic1_out(.a(a[1]), .b(b[1]), .pg_logic_or0(u_cla4_pg_logic1_or0), .pg_logic_and0(u_cla4_pg_logic1_and0), .pg_logic_xor0(u_cla4_pg_logic1_xor0));
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xor_gate xor_gate_u_cla4_xor1(.a(u_cla4_pg_logic1_xor0[0]), .b(u_cla4_pg_logic0_and0[0]), .out(u_cla4_xor1));
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and_gate and_gate_u_cla4_and0(.a(u_cla4_pg_logic0_and0[0]), .b(u_cla4_pg_logic1_or0[0]), .out(u_cla4_and0));
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or_gate or_gate_u_cla4_or0(.a(u_cla4_pg_logic1_and0[0]), .b(u_cla4_and0[0]), .out(u_cla4_or0));
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pg_logic pg_logic_u_cla4_pg_logic2_out(.a(a[2]), .b(b[2]), .pg_logic_or0(u_cla4_pg_logic2_or0), .pg_logic_and0(u_cla4_pg_logic2_and0), .pg_logic_xor0(u_cla4_pg_logic2_xor0));
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xor_gate xor_gate_u_cla4_xor2(.a(u_cla4_pg_logic2_xor0[0]), .b(u_cla4_or0[0]), .out(u_cla4_xor2));
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and_gate and_gate_u_cla4_and1(.a(u_cla4_pg_logic2_or0[0]), .b(u_cla4_pg_logic0_or0[0]), .out(u_cla4_and1));
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and_gate and_gate_u_cla4_and2(.a(u_cla4_pg_logic0_and0[0]), .b(u_cla4_pg_logic2_or0[0]), .out(u_cla4_and2));
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and_gate and_gate_u_cla4_and3(.a(u_cla4_and2[0]), .b(u_cla4_pg_logic1_or0[0]), .out(u_cla4_and3));
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and_gate and_gate_u_cla4_and4(.a(u_cla4_pg_logic1_and0[0]), .b(u_cla4_pg_logic2_or0[0]), .out(u_cla4_and4));
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or_gate or_gate_u_cla4_or1(.a(u_cla4_and3[0]), .b(u_cla4_and4[0]), .out(u_cla4_or1));
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or_gate or_gate_u_cla4_or2(.a(u_cla4_pg_logic2_and0[0]), .b(u_cla4_or1[0]), .out(u_cla4_or2));
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pg_logic pg_logic_u_cla4_pg_logic3_out(.a(a[3]), .b(b[3]), .pg_logic_or0(u_cla4_pg_logic3_or0), .pg_logic_and0(u_cla4_pg_logic3_and0), .pg_logic_xor0(u_cla4_pg_logic3_xor0));
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xor_gate xor_gate_u_cla4_xor3(.a(u_cla4_pg_logic3_xor0[0]), .b(u_cla4_or2[0]), .out(u_cla4_xor3));
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and_gate and_gate_u_cla4_and5(.a(u_cla4_pg_logic3_or0[0]), .b(u_cla4_pg_logic1_or0[0]), .out(u_cla4_and5));
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and_gate and_gate_u_cla4_and6(.a(u_cla4_pg_logic0_and0[0]), .b(u_cla4_pg_logic2_or0[0]), .out(u_cla4_and6));
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and_gate and_gate_u_cla4_and7(.a(u_cla4_pg_logic3_or0[0]), .b(u_cla4_pg_logic1_or0[0]), .out(u_cla4_and7));
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and_gate and_gate_u_cla4_and8(.a(u_cla4_and6[0]), .b(u_cla4_and7[0]), .out(u_cla4_and8));
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and_gate and_gate_u_cla4_and9(.a(u_cla4_pg_logic1_and0[0]), .b(u_cla4_pg_logic3_or0[0]), .out(u_cla4_and9));
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and_gate and_gate_u_cla4_and10(.a(u_cla4_and9[0]), .b(u_cla4_pg_logic2_or0[0]), .out(u_cla4_and10));
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and_gate and_gate_u_cla4_and11(.a(u_cla4_pg_logic2_and0[0]), .b(u_cla4_pg_logic3_or0[0]), .out(u_cla4_and11));
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or_gate or_gate_u_cla4_or3(.a(u_cla4_and8[0]), .b(u_cla4_and11[0]), .out(u_cla4_or3));
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or_gate or_gate_u_cla4_or4(.a(u_cla4_and10[0]), .b(u_cla4_or3[0]), .out(u_cla4_or4));
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or_gate or_gate_u_cla4_or5(.a(u_cla4_pg_logic3_and0[0]), .b(u_cla4_or4[0]), .out(u_cla4_or5));
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assign u_cla4_out[0] = u_cla4_pg_logic0_xor0[0];
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assign u_cla4_out[1] = u_cla4_xor1[0];
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assign u_cla4_out[2] = u_cla4_xor2[0];
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assign u_cla4_out[3] = u_cla4_xor3[0];
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assign u_cla4_out[4] = u_cla4_or5[0];
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endmodule
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module s_csamul_cla4(input [3:0] a, input [3:0] b, output [7:0] s_csamul_cla4_out);
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wire [0:0] s_csamul_cla4_and0_0;
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wire [0:0] s_csamul_cla4_and1_0;
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wire [0:0] s_csamul_cla4_and2_0;
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wire [0:0] s_csamul_cla4_nand3_0;
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wire [0:0] s_csamul_cla4_and0_1;
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wire [0:0] s_csamul_cla4_ha0_1_xor0;
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wire [0:0] s_csamul_cla4_ha0_1_and0;
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wire [0:0] s_csamul_cla4_and1_1;
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wire [0:0] s_csamul_cla4_ha1_1_xor0;
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wire [0:0] s_csamul_cla4_ha1_1_and0;
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wire [0:0] s_csamul_cla4_and2_1;
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wire [0:0] s_csamul_cla4_ha2_1_xor0;
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wire [0:0] s_csamul_cla4_ha2_1_and0;
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wire [0:0] s_csamul_cla4_nand3_1;
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wire [0:0] s_csamul_cla4_ha3_1_xor0;
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wire [0:0] s_csamul_cla4_and0_2;
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wire [0:0] s_csamul_cla4_fa0_2_xor1;
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wire [0:0] s_csamul_cla4_fa0_2_or0;
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wire [0:0] s_csamul_cla4_and1_2;
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wire [0:0] s_csamul_cla4_fa1_2_xor1;
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wire [0:0] s_csamul_cla4_fa1_2_or0;
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wire [0:0] s_csamul_cla4_and2_2;
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wire [0:0] s_csamul_cla4_fa2_2_xor1;
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wire [0:0] s_csamul_cla4_fa2_2_or0;
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wire [0:0] s_csamul_cla4_nand3_2;
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wire [0:0] s_csamul_cla4_ha3_2_xor0;
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wire [0:0] s_csamul_cla4_ha3_2_and0;
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wire [0:0] s_csamul_cla4_nand0_3;
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wire [0:0] s_csamul_cla4_fa0_3_xor1;
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wire [0:0] s_csamul_cla4_fa0_3_or0;
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wire [0:0] s_csamul_cla4_nand1_3;
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wire [0:0] s_csamul_cla4_fa1_3_xor1;
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wire [0:0] s_csamul_cla4_fa1_3_or0;
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wire [0:0] s_csamul_cla4_nand2_3;
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wire [0:0] s_csamul_cla4_fa2_3_xor1;
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wire [0:0] s_csamul_cla4_fa2_3_or0;
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wire [0:0] s_csamul_cla4_and3_3;
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wire [0:0] s_csamul_cla4_ha3_3_xor0;
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wire [0:0] s_csamul_cla4_ha3_3_and0;
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wire [3:0] s_csamul_cla4_u_cla4_a;
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wire [3:0] s_csamul_cla4_u_cla4_b;
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wire [4:0] s_csamul_cla4_u_cla4_out;
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and_gate and_gate_s_csamul_cla4_and0_0(.a(a[0]), .b(b[0]), .out(s_csamul_cla4_and0_0));
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and_gate and_gate_s_csamul_cla4_and1_0(.a(a[1]), .b(b[0]), .out(s_csamul_cla4_and1_0));
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and_gate and_gate_s_csamul_cla4_and2_0(.a(a[2]), .b(b[0]), .out(s_csamul_cla4_and2_0));
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nand_gate nand_gate_s_csamul_cla4_nand3_0(.a(a[3]), .b(b[0]), .out(s_csamul_cla4_nand3_0));
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and_gate and_gate_s_csamul_cla4_and0_1(.a(a[0]), .b(b[1]), .out(s_csamul_cla4_and0_1));
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ha ha_s_csamul_cla4_ha0_1_out(.a(s_csamul_cla4_and0_1[0]), .b(s_csamul_cla4_and1_0[0]), .ha_xor0(s_csamul_cla4_ha0_1_xor0), .ha_and0(s_csamul_cla4_ha0_1_and0));
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and_gate and_gate_s_csamul_cla4_and1_1(.a(a[1]), .b(b[1]), .out(s_csamul_cla4_and1_1));
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ha ha_s_csamul_cla4_ha1_1_out(.a(s_csamul_cla4_and1_1[0]), .b(s_csamul_cla4_and2_0[0]), .ha_xor0(s_csamul_cla4_ha1_1_xor0), .ha_and0(s_csamul_cla4_ha1_1_and0));
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and_gate and_gate_s_csamul_cla4_and2_1(.a(a[2]), .b(b[1]), .out(s_csamul_cla4_and2_1));
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ha ha_s_csamul_cla4_ha2_1_out(.a(s_csamul_cla4_and2_1[0]), .b(s_csamul_cla4_nand3_0[0]), .ha_xor0(s_csamul_cla4_ha2_1_xor0), .ha_and0(s_csamul_cla4_ha2_1_and0));
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nand_gate nand_gate_s_csamul_cla4_nand3_1(.a(a[3]), .b(b[1]), .out(s_csamul_cla4_nand3_1));
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ha ha_s_csamul_cla4_ha3_1_out(.a(s_csamul_cla4_nand3_1[0]), .b(1'b1), .ha_xor0(s_csamul_cla4_ha3_1_xor0), .ha_and0(s_csamul_cla4_nand3_1));
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and_gate and_gate_s_csamul_cla4_and0_2(.a(a[0]), .b(b[2]), .out(s_csamul_cla4_and0_2));
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fa fa_s_csamul_cla4_fa0_2_out(.a(s_csamul_cla4_and0_2[0]), .b(s_csamul_cla4_ha1_1_xor0[0]), .cin(s_csamul_cla4_ha0_1_and0[0]), .fa_xor1(s_csamul_cla4_fa0_2_xor1), .fa_or0(s_csamul_cla4_fa0_2_or0));
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and_gate and_gate_s_csamul_cla4_and1_2(.a(a[1]), .b(b[2]), .out(s_csamul_cla4_and1_2));
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fa fa_s_csamul_cla4_fa1_2_out(.a(s_csamul_cla4_and1_2[0]), .b(s_csamul_cla4_ha2_1_xor0[0]), .cin(s_csamul_cla4_ha1_1_and0[0]), .fa_xor1(s_csamul_cla4_fa1_2_xor1), .fa_or0(s_csamul_cla4_fa1_2_or0));
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and_gate and_gate_s_csamul_cla4_and2_2(.a(a[2]), .b(b[2]), .out(s_csamul_cla4_and2_2));
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fa fa_s_csamul_cla4_fa2_2_out(.a(s_csamul_cla4_and2_2[0]), .b(s_csamul_cla4_ha3_1_xor0[0]), .cin(s_csamul_cla4_ha2_1_and0[0]), .fa_xor1(s_csamul_cla4_fa2_2_xor1), .fa_or0(s_csamul_cla4_fa2_2_or0));
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nand_gate nand_gate_s_csamul_cla4_nand3_2(.a(a[3]), .b(b[2]), .out(s_csamul_cla4_nand3_2));
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ha ha_s_csamul_cla4_ha3_2_out(.a(s_csamul_cla4_nand3_2[0]), .b(s_csamul_cla4_nand3_1[0]), .ha_xor0(s_csamul_cla4_ha3_2_xor0), .ha_and0(s_csamul_cla4_ha3_2_and0));
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nand_gate nand_gate_s_csamul_cla4_nand0_3(.a(a[0]), .b(b[3]), .out(s_csamul_cla4_nand0_3));
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fa fa_s_csamul_cla4_fa0_3_out(.a(s_csamul_cla4_nand0_3[0]), .b(s_csamul_cla4_fa1_2_xor1[0]), .cin(s_csamul_cla4_fa0_2_or0[0]), .fa_xor1(s_csamul_cla4_fa0_3_xor1), .fa_or0(s_csamul_cla4_fa0_3_or0));
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nand_gate nand_gate_s_csamul_cla4_nand1_3(.a(a[1]), .b(b[3]), .out(s_csamul_cla4_nand1_3));
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fa fa_s_csamul_cla4_fa1_3_out(.a(s_csamul_cla4_nand1_3[0]), .b(s_csamul_cla4_fa2_2_xor1[0]), .cin(s_csamul_cla4_fa1_2_or0[0]), .fa_xor1(s_csamul_cla4_fa1_3_xor1), .fa_or0(s_csamul_cla4_fa1_3_or0));
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nand_gate nand_gate_s_csamul_cla4_nand2_3(.a(a[2]), .b(b[3]), .out(s_csamul_cla4_nand2_3));
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fa fa_s_csamul_cla4_fa2_3_out(.a(s_csamul_cla4_nand2_3[0]), .b(s_csamul_cla4_ha3_2_xor0[0]), .cin(s_csamul_cla4_fa2_2_or0[0]), .fa_xor1(s_csamul_cla4_fa2_3_xor1), .fa_or0(s_csamul_cla4_fa2_3_or0));
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and_gate and_gate_s_csamul_cla4_and3_3(.a(a[3]), .b(b[3]), .out(s_csamul_cla4_and3_3));
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ha ha_s_csamul_cla4_ha3_3_out(.a(s_csamul_cla4_and3_3[0]), .b(s_csamul_cla4_ha3_2_and0[0]), .ha_xor0(s_csamul_cla4_ha3_3_xor0), .ha_and0(s_csamul_cla4_ha3_3_and0));
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assign s_csamul_cla4_u_cla4_a[0] = s_csamul_cla4_fa1_3_xor1[0];
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assign s_csamul_cla4_u_cla4_a[1] = s_csamul_cla4_fa2_3_xor1[0];
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assign s_csamul_cla4_u_cla4_a[2] = s_csamul_cla4_ha3_3_xor0[0];
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assign s_csamul_cla4_u_cla4_a[3] = 1'b1;
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assign s_csamul_cla4_u_cla4_b[0] = s_csamul_cla4_fa0_3_or0[0];
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assign s_csamul_cla4_u_cla4_b[1] = s_csamul_cla4_fa1_3_or0[0];
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assign s_csamul_cla4_u_cla4_b[2] = s_csamul_cla4_fa2_3_or0[0];
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assign s_csamul_cla4_u_cla4_b[3] = s_csamul_cla4_ha3_3_and0[0];
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u_cla4 u_cla4_s_csamul_cla4_u_cla4_out(.a(s_csamul_cla4_u_cla4_a), .b(s_csamul_cla4_u_cla4_b), .u_cla4_out(s_csamul_cla4_u_cla4_out));
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assign s_csamul_cla4_out[0] = s_csamul_cla4_and0_0[0];
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assign s_csamul_cla4_out[1] = s_csamul_cla4_ha0_1_xor0[0];
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assign s_csamul_cla4_out[2] = s_csamul_cla4_fa0_2_xor1[0];
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assign s_csamul_cla4_out[3] = s_csamul_cla4_fa0_3_xor1[0];
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assign s_csamul_cla4_out[4] = s_csamul_cla4_u_cla4_out[0];
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assign s_csamul_cla4_out[5] = s_csamul_cla4_u_cla4_out[1];
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assign s_csamul_cla4_out[6] = s_csamul_cla4_u_cla4_out[2];
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assign s_csamul_cla4_out[7] = s_csamul_cla4_u_cla4_out[3];
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endmodule |