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https://github.com/ehw-fit/ariths-gen.git
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45 lines
1.5 KiB
Python
45 lines
1.5 KiB
Python
from wire_components import wire, bus
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from logic_gates import logic_gate, and_gate, nand_gate, or_gate, nor_gate, xor_gate, xnor_gate, not_gate
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from one_bit_circuits import half_adder, full_adder
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from multi_bit_circuits import unsigned_ripple_carry_adder, signed_ripple_carry_adder, unsigned_array_multiplier, signed_array_multiplier
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import sys
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""" TESTING """
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if __name__ == "__main__":
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a = bus(N=10, prefix="a")
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b = bus(N=1, prefix="b")
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rca = unsigned_ripple_carry_adder(a, b, prefix="h_u_rca8")
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# rca.get_v_code_hier(open("h_u_rca8.v", "w"))
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# rca.get_c_code_hier(open("h_u_rca8.c", "w"))
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arrmul = unsigned_array_multiplier(a, b, prefix="f_u_arr_mul10")
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arrmul.get_c_code_flat(open("f_u_arr_mul10.c", "w"))
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arrmul.get_v_code_flat(open("f_u_arr_mul10.v", "w"))
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# arrmul.get_cgp_code_hier(open("s_arr_mul5.chr", "w"))
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# rca.get_cgp_code_hier(open("s_rca5.chr", "w"))
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w1 = wire(name="a")
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w2 = wire(name="b")
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w3 = wire(name="cin")
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ha = half_adder(w1, w2, prefix="f_ha")
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fa = full_adder(w1, w2, w3, prefix="f_fa")
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"""
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ha.get_v_code_hier(open("h_ha.v","w"))
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ha.get_v_code_flat(open("f_ha.v","w"))
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ha.get_c_code_hier(open("h_ha.c","w"))
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ha.get_c_code_flat(open("f_ha.c","w"))
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ha.get_cgp_code(open("ha.chr","w"))
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"""
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gate = and_gate(w1, w2)
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"""
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#gate.get_c_code(open("and_gate.c","w"))
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#gate.get_v_code(open("and_gate.v","w"))
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#gate.get_cgp_code(open("and_gate.chr","w"))
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"""
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