mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-21 22:31:22 +01:00
90 lines
5.3 KiB
Verilog
90 lines
5.3 KiB
Verilog
module xor_gate(input a, input b, output out);
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assign out = a ^ b;
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endmodule
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module and_gate(input a, input b, output out);
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assign out = a & b;
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endmodule
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module or_gate(input a, input b, output out);
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assign out = a | b;
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endmodule
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module pg_fa(input [0:0] a, input [0:0] b, input [0:0] cin, output [0:0] pg_fa_xor0, output [0:0] pg_fa_and0, output [0:0] pg_fa_xor1);
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xor_gate xor_gate_pg_fa_xor0(.a(a[0]), .b(b[0]), .out(pg_fa_xor0));
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and_gate and_gate_pg_fa_and0(.a(a[0]), .b(b[0]), .out(pg_fa_and0));
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xor_gate xor_gate_pg_fa_xor1(.a(pg_fa_xor0[0]), .b(cin[0]), .out(pg_fa_xor1));
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endmodule
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module u_pg_rca8(input [7:0] a, input [7:0] b, output [8:0] u_pg_rca8_out);
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wire [0:0] u_pg_rca8_pg_fa0_xor0;
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wire [0:0] u_pg_rca8_pg_fa0_and0;
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wire [0:0] u_pg_rca8_pg_fa1_xor0;
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wire [0:0] u_pg_rca8_pg_fa1_and0;
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wire [0:0] u_pg_rca8_pg_fa1_xor1;
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wire [0:0] u_pg_rca8_and1;
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wire [0:0] u_pg_rca8_or1;
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wire [0:0] u_pg_rca8_pg_fa2_xor0;
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wire [0:0] u_pg_rca8_pg_fa2_and0;
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wire [0:0] u_pg_rca8_pg_fa2_xor1;
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wire [0:0] u_pg_rca8_and2;
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wire [0:0] u_pg_rca8_or2;
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wire [0:0] u_pg_rca8_pg_fa3_xor0;
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wire [0:0] u_pg_rca8_pg_fa3_and0;
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wire [0:0] u_pg_rca8_pg_fa3_xor1;
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wire [0:0] u_pg_rca8_and3;
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wire [0:0] u_pg_rca8_or3;
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wire [0:0] u_pg_rca8_pg_fa4_xor0;
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wire [0:0] u_pg_rca8_pg_fa4_and0;
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wire [0:0] u_pg_rca8_pg_fa4_xor1;
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wire [0:0] u_pg_rca8_and4;
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wire [0:0] u_pg_rca8_or4;
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wire [0:0] u_pg_rca8_pg_fa5_xor0;
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wire [0:0] u_pg_rca8_pg_fa5_and0;
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wire [0:0] u_pg_rca8_pg_fa5_xor1;
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wire [0:0] u_pg_rca8_and5;
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wire [0:0] u_pg_rca8_or5;
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wire [0:0] u_pg_rca8_pg_fa6_xor0;
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wire [0:0] u_pg_rca8_pg_fa6_and0;
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wire [0:0] u_pg_rca8_pg_fa6_xor1;
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wire [0:0] u_pg_rca8_and6;
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wire [0:0] u_pg_rca8_or6;
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wire [0:0] u_pg_rca8_pg_fa7_xor0;
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wire [0:0] u_pg_rca8_pg_fa7_and0;
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wire [0:0] u_pg_rca8_pg_fa7_xor1;
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wire [0:0] u_pg_rca8_and7;
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wire [0:0] u_pg_rca8_or7;
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pg_fa pg_fa_u_pg_rca8_pg_fa0_out(.a(a[0]), .b(b[0]), .cin(1'b0), .pg_fa_xor0(u_pg_rca8_pg_fa0_xor0), .pg_fa_and0(u_pg_rca8_pg_fa0_and0), .pg_fa_xor1());
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pg_fa pg_fa_u_pg_rca8_pg_fa1_out(.a(a[1]), .b(b[1]), .cin(u_pg_rca8_pg_fa0_and0[0]), .pg_fa_xor0(u_pg_rca8_pg_fa1_xor0), .pg_fa_and0(u_pg_rca8_pg_fa1_and0), .pg_fa_xor1(u_pg_rca8_pg_fa1_xor1));
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and_gate and_gate_u_pg_rca8_and1(.a(u_pg_rca8_pg_fa0_and0[0]), .b(u_pg_rca8_pg_fa1_xor0[0]), .out(u_pg_rca8_and1));
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or_gate or_gate_u_pg_rca8_or1(.a(u_pg_rca8_and1[0]), .b(u_pg_rca8_pg_fa1_and0[0]), .out(u_pg_rca8_or1));
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pg_fa pg_fa_u_pg_rca8_pg_fa2_out(.a(a[2]), .b(b[2]), .cin(u_pg_rca8_or1[0]), .pg_fa_xor0(u_pg_rca8_pg_fa2_xor0), .pg_fa_and0(u_pg_rca8_pg_fa2_and0), .pg_fa_xor1(u_pg_rca8_pg_fa2_xor1));
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and_gate and_gate_u_pg_rca8_and2(.a(u_pg_rca8_or1[0]), .b(u_pg_rca8_pg_fa2_xor0[0]), .out(u_pg_rca8_and2));
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or_gate or_gate_u_pg_rca8_or2(.a(u_pg_rca8_and2[0]), .b(u_pg_rca8_pg_fa2_and0[0]), .out(u_pg_rca8_or2));
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pg_fa pg_fa_u_pg_rca8_pg_fa3_out(.a(a[3]), .b(b[3]), .cin(u_pg_rca8_or2[0]), .pg_fa_xor0(u_pg_rca8_pg_fa3_xor0), .pg_fa_and0(u_pg_rca8_pg_fa3_and0), .pg_fa_xor1(u_pg_rca8_pg_fa3_xor1));
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and_gate and_gate_u_pg_rca8_and3(.a(u_pg_rca8_or2[0]), .b(u_pg_rca8_pg_fa3_xor0[0]), .out(u_pg_rca8_and3));
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or_gate or_gate_u_pg_rca8_or3(.a(u_pg_rca8_and3[0]), .b(u_pg_rca8_pg_fa3_and0[0]), .out(u_pg_rca8_or3));
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pg_fa pg_fa_u_pg_rca8_pg_fa4_out(.a(a[4]), .b(b[4]), .cin(u_pg_rca8_or3[0]), .pg_fa_xor0(u_pg_rca8_pg_fa4_xor0), .pg_fa_and0(u_pg_rca8_pg_fa4_and0), .pg_fa_xor1(u_pg_rca8_pg_fa4_xor1));
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and_gate and_gate_u_pg_rca8_and4(.a(u_pg_rca8_or3[0]), .b(u_pg_rca8_pg_fa4_xor0[0]), .out(u_pg_rca8_and4));
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or_gate or_gate_u_pg_rca8_or4(.a(u_pg_rca8_and4[0]), .b(u_pg_rca8_pg_fa4_and0[0]), .out(u_pg_rca8_or4));
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pg_fa pg_fa_u_pg_rca8_pg_fa5_out(.a(a[5]), .b(b[5]), .cin(u_pg_rca8_or4[0]), .pg_fa_xor0(u_pg_rca8_pg_fa5_xor0), .pg_fa_and0(u_pg_rca8_pg_fa5_and0), .pg_fa_xor1(u_pg_rca8_pg_fa5_xor1));
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and_gate and_gate_u_pg_rca8_and5(.a(u_pg_rca8_or4[0]), .b(u_pg_rca8_pg_fa5_xor0[0]), .out(u_pg_rca8_and5));
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or_gate or_gate_u_pg_rca8_or5(.a(u_pg_rca8_and5[0]), .b(u_pg_rca8_pg_fa5_and0[0]), .out(u_pg_rca8_or5));
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pg_fa pg_fa_u_pg_rca8_pg_fa6_out(.a(a[6]), .b(b[6]), .cin(u_pg_rca8_or5[0]), .pg_fa_xor0(u_pg_rca8_pg_fa6_xor0), .pg_fa_and0(u_pg_rca8_pg_fa6_and0), .pg_fa_xor1(u_pg_rca8_pg_fa6_xor1));
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and_gate and_gate_u_pg_rca8_and6(.a(u_pg_rca8_or5[0]), .b(u_pg_rca8_pg_fa6_xor0[0]), .out(u_pg_rca8_and6));
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or_gate or_gate_u_pg_rca8_or6(.a(u_pg_rca8_and6[0]), .b(u_pg_rca8_pg_fa6_and0[0]), .out(u_pg_rca8_or6));
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pg_fa pg_fa_u_pg_rca8_pg_fa7_out(.a(a[7]), .b(b[7]), .cin(u_pg_rca8_or6[0]), .pg_fa_xor0(u_pg_rca8_pg_fa7_xor0), .pg_fa_and0(u_pg_rca8_pg_fa7_and0), .pg_fa_xor1(u_pg_rca8_pg_fa7_xor1));
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and_gate and_gate_u_pg_rca8_and7(.a(u_pg_rca8_or6[0]), .b(u_pg_rca8_pg_fa7_xor0[0]), .out(u_pg_rca8_and7));
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or_gate or_gate_u_pg_rca8_or7(.a(u_pg_rca8_and7[0]), .b(u_pg_rca8_pg_fa7_and0[0]), .out(u_pg_rca8_or7));
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assign u_pg_rca8_out[0] = u_pg_rca8_pg_fa0_xor0[0];
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assign u_pg_rca8_out[1] = u_pg_rca8_pg_fa1_xor1[0];
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assign u_pg_rca8_out[2] = u_pg_rca8_pg_fa2_xor1[0];
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assign u_pg_rca8_out[3] = u_pg_rca8_pg_fa3_xor1[0];
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assign u_pg_rca8_out[4] = u_pg_rca8_pg_fa4_xor1[0];
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assign u_pg_rca8_out[5] = u_pg_rca8_pg_fa5_xor1[0];
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assign u_pg_rca8_out[6] = u_pg_rca8_pg_fa6_xor1[0];
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assign u_pg_rca8_out[7] = u_pg_rca8_pg_fa7_xor1[0];
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assign u_pg_rca8_out[8] = u_pg_rca8_or7[0];
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endmodule |