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dissertation_thesis
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ariths-gen
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ariths-gen
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ariths_gen
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core
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honzastor
d52e67bb25
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
..
arithmetic_circuits
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
logic_gate_circuits
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
one_bit_circuits
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
__init__.py
Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
2021-04-21 11:33:07 +02:00
cgp_circuit.py
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
