mirror of
https://github.com/ehw-fit/ariths-gen.git
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58 lines
1.1 KiB
Python
58 lines
1.1 KiB
Python
import os
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import sys
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# Add the parent directory to the system path
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DIR_PATH = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, os.path.join(DIR_PATH, '..'))
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import numpy as np
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import math
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from io import StringIO
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.multi_bit_circuits.others import (
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UnsignedCompareLT
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)
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def test_compare():
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""" Test unsigned comparator """
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N = 8
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a = Bus(N=N, prefix="a")
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b = Bus(N=N, prefix="b")
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av = np.arange(2**N).reshape(1, -1)
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bv = np.arange(2**N).reshape(-1, 1)
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cmp = UnsignedCompareLT(a=a, b=b)
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o = StringIO()
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cmp.get_v_code_hier(open("tmp.verilog", "w"))
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print(o.getvalue())
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# av = 0
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# bv = 5
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v = cmp(av, bv)
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print("ret = ", v)
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expected = np.array(av < bv).astype(int)
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print("expected = ", expected)
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#expected = np.sum(r, axis=1)
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np.testing.assert_array_equal(v, expected)
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if __name__ == "__main__":
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test_compare()
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print("Python compare tests were successful!") |