ariths-gen/generated_circuits/blif_circuits/hier/u_pg_rca24.blif

.model u_pg_rca24
.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] b[21] b[22] b[23]
.outputs u_pg_rca24_out[0] u_pg_rca24_out[1] u_pg_rca24_out[2] u_pg_rca24_out[3] u_pg_rca24_out[4] u_pg_rca24_out[5] u_pg_rca24_out[6] u_pg_rca24_out[7] u_pg_rca24_out[8] u_pg_rca24_out[9] u_pg_rca24_out[10] u_pg_rca24_out[11] u_pg_rca24_out[12] u_pg_rca24_out[13] u_pg_rca24_out[14] u_pg_rca24_out[15] u_pg_rca24_out[16] u_pg_rca24_out[17] u_pg_rca24_out[18] u_pg_rca24_out[19] u_pg_rca24_out[20] u_pg_rca24_out[21] u_pg_rca24_out[22] u_pg_rca24_out[23] u_pg_rca24_out[24]
.names vdd
1
.names gnd
0
.subckt pg_fa a=a[0] b=b[0] cin=gnd pg_fa_xor0=u_pg_rca24_pg_fa0_xor0 pg_fa_and0=u_pg_rca24_pg_fa0_and0
.subckt pg_fa a=a[1] b=b[1] cin=u_pg_rca24_pg_fa0_and0 pg_fa_xor0=u_pg_rca24_pg_fa1_xor0 pg_fa_and0=u_pg_rca24_pg_fa1_and0 pg_fa_xor1=u_pg_rca24_pg_fa1_xor1
.subckt and_gate a=u_pg_rca24_pg_fa0_and0 b=u_pg_rca24_pg_fa1_xor0 out=u_pg_rca24_and1
.subckt or_gate a=u_pg_rca24_and1 b=u_pg_rca24_pg_fa1_and0 out=u_pg_rca24_or1
.subckt pg_fa a=a[2] b=b[2] cin=u_pg_rca24_or1 pg_fa_xor0=u_pg_rca24_pg_fa2_xor0 pg_fa_and0=u_pg_rca24_pg_fa2_and0 pg_fa_xor1=u_pg_rca24_pg_fa2_xor1
.subckt and_gate a=u_pg_rca24_or1 b=u_pg_rca24_pg_fa2_xor0 out=u_pg_rca24_and2
.subckt or_gate a=u_pg_rca24_and2 b=u_pg_rca24_pg_fa2_and0 out=u_pg_rca24_or2
.subckt pg_fa a=a[3] b=b[3] cin=u_pg_rca24_or2 pg_fa_xor0=u_pg_rca24_pg_fa3_xor0 pg_fa_and0=u_pg_rca24_pg_fa3_and0 pg_fa_xor1=u_pg_rca24_pg_fa3_xor1
.subckt and_gate a=u_pg_rca24_or2 b=u_pg_rca24_pg_fa3_xor0 out=u_pg_rca24_and3
.subckt or_gate a=u_pg_rca24_and3 b=u_pg_rca24_pg_fa3_and0 out=u_pg_rca24_or3
.subckt pg_fa a=a[4] b=b[4] cin=u_pg_rca24_or3 pg_fa_xor0=u_pg_rca24_pg_fa4_xor0 pg_fa_and0=u_pg_rca24_pg_fa4_and0 pg_fa_xor1=u_pg_rca24_pg_fa4_xor1
.subckt and_gate a=u_pg_rca24_or3 b=u_pg_rca24_pg_fa4_xor0 out=u_pg_rca24_and4
.subckt or_gate a=u_pg_rca24_and4 b=u_pg_rca24_pg_fa4_and0 out=u_pg_rca24_or4
.subckt pg_fa a=a[5] b=b[5] cin=u_pg_rca24_or4 pg_fa_xor0=u_pg_rca24_pg_fa5_xor0 pg_fa_and0=u_pg_rca24_pg_fa5_and0 pg_fa_xor1=u_pg_rca24_pg_fa5_xor1
.subckt and_gate a=u_pg_rca24_or4 b=u_pg_rca24_pg_fa5_xor0 out=u_pg_rca24_and5
.subckt or_gate a=u_pg_rca24_and5 b=u_pg_rca24_pg_fa5_and0 out=u_pg_rca24_or5
.subckt pg_fa a=a[6] b=b[6] cin=u_pg_rca24_or5 pg_fa_xor0=u_pg_rca24_pg_fa6_xor0 pg_fa_and0=u_pg_rca24_pg_fa6_and0 pg_fa_xor1=u_pg_rca24_pg_fa6_xor1
.subckt and_gate a=u_pg_rca24_or5 b=u_pg_rca24_pg_fa6_xor0 out=u_pg_rca24_and6
.subckt or_gate a=u_pg_rca24_and6 b=u_pg_rca24_pg_fa6_and0 out=u_pg_rca24_or6
.subckt pg_fa a=a[7] b=b[7] cin=u_pg_rca24_or6 pg_fa_xor0=u_pg_rca24_pg_fa7_xor0 pg_fa_and0=u_pg_rca24_pg_fa7_and0 pg_fa_xor1=u_pg_rca24_pg_fa7_xor1
.subckt and_gate a=u_pg_rca24_or6 b=u_pg_rca24_pg_fa7_xor0 out=u_pg_rca24_and7
.subckt or_gate a=u_pg_rca24_and7 b=u_pg_rca24_pg_fa7_and0 out=u_pg_rca24_or7
.subckt pg_fa a=a[8] b=b[8] cin=u_pg_rca24_or7 pg_fa_xor0=u_pg_rca24_pg_fa8_xor0 pg_fa_and0=u_pg_rca24_pg_fa8_and0 pg_fa_xor1=u_pg_rca24_pg_fa8_xor1
.subckt and_gate a=u_pg_rca24_or7 b=u_pg_rca24_pg_fa8_xor0 out=u_pg_rca24_and8
.subckt or_gate a=u_pg_rca24_and8 b=u_pg_rca24_pg_fa8_and0 out=u_pg_rca24_or8
.subckt pg_fa a=a[9] b=b[9] cin=u_pg_rca24_or8 pg_fa_xor0=u_pg_rca24_pg_fa9_xor0 pg_fa_and0=u_pg_rca24_pg_fa9_and0 pg_fa_xor1=u_pg_rca24_pg_fa9_xor1
.subckt and_gate a=u_pg_rca24_or8 b=u_pg_rca24_pg_fa9_xor0 out=u_pg_rca24_and9
.subckt or_gate a=u_pg_rca24_and9 b=u_pg_rca24_pg_fa9_and0 out=u_pg_rca24_or9
.subckt pg_fa a=a[10] b=b[10] cin=u_pg_rca24_or9 pg_fa_xor0=u_pg_rca24_pg_fa10_xor0 pg_fa_and0=u_pg_rca24_pg_fa10_and0 pg_fa_xor1=u_pg_rca24_pg_fa10_xor1
.subckt and_gate a=u_pg_rca24_or9 b=u_pg_rca24_pg_fa10_xor0 out=u_pg_rca24_and10
.subckt or_gate a=u_pg_rca24_and10 b=u_pg_rca24_pg_fa10_and0 out=u_pg_rca24_or10
.subckt pg_fa a=a[11] b=b[11] cin=u_pg_rca24_or10 pg_fa_xor0=u_pg_rca24_pg_fa11_xor0 pg_fa_and0=u_pg_rca24_pg_fa11_and0 pg_fa_xor1=u_pg_rca24_pg_fa11_xor1
.subckt and_gate a=u_pg_rca24_or10 b=u_pg_rca24_pg_fa11_xor0 out=u_pg_rca24_and11
.subckt or_gate a=u_pg_rca24_and11 b=u_pg_rca24_pg_fa11_and0 out=u_pg_rca24_or11
.subckt pg_fa a=a[12] b=b[12] cin=u_pg_rca24_or11 pg_fa_xor0=u_pg_rca24_pg_fa12_xor0 pg_fa_and0=u_pg_rca24_pg_fa12_and0 pg_fa_xor1=u_pg_rca24_pg_fa12_xor1
.subckt and_gate a=u_pg_rca24_or11 b=u_pg_rca24_pg_fa12_xor0 out=u_pg_rca24_and12
.subckt or_gate a=u_pg_rca24_and12 b=u_pg_rca24_pg_fa12_and0 out=u_pg_rca24_or12
.subckt pg_fa a=a[13] b=b[13] cin=u_pg_rca24_or12 pg_fa_xor0=u_pg_rca24_pg_fa13_xor0 pg_fa_and0=u_pg_rca24_pg_fa13_and0 pg_fa_xor1=u_pg_rca24_pg_fa13_xor1
.subckt and_gate a=u_pg_rca24_or12 b=u_pg_rca24_pg_fa13_xor0 out=u_pg_rca24_and13
.subckt or_gate a=u_pg_rca24_and13 b=u_pg_rca24_pg_fa13_and0 out=u_pg_rca24_or13
.subckt pg_fa a=a[14] b=b[14] cin=u_pg_rca24_or13 pg_fa_xor0=u_pg_rca24_pg_fa14_xor0 pg_fa_and0=u_pg_rca24_pg_fa14_and0 pg_fa_xor1=u_pg_rca24_pg_fa14_xor1
.subckt and_gate a=u_pg_rca24_or13 b=u_pg_rca24_pg_fa14_xor0 out=u_pg_rca24_and14
.subckt or_gate a=u_pg_rca24_and14 b=u_pg_rca24_pg_fa14_and0 out=u_pg_rca24_or14
.subckt pg_fa a=a[15] b=b[15] cin=u_pg_rca24_or14 pg_fa_xor0=u_pg_rca24_pg_fa15_xor0 pg_fa_and0=u_pg_rca24_pg_fa15_and0 pg_fa_xor1=u_pg_rca24_pg_fa15_xor1
.subckt and_gate a=u_pg_rca24_or14 b=u_pg_rca24_pg_fa15_xor0 out=u_pg_rca24_and15
.subckt or_gate a=u_pg_rca24_and15 b=u_pg_rca24_pg_fa15_and0 out=u_pg_rca24_or15
.subckt pg_fa a=a[16] b=b[16] cin=u_pg_rca24_or15 pg_fa_xor0=u_pg_rca24_pg_fa16_xor0 pg_fa_and0=u_pg_rca24_pg_fa16_and0 pg_fa_xor1=u_pg_rca24_pg_fa16_xor1
.subckt and_gate a=u_pg_rca24_or15 b=u_pg_rca24_pg_fa16_xor0 out=u_pg_rca24_and16
.subckt or_gate a=u_pg_rca24_and16 b=u_pg_rca24_pg_fa16_and0 out=u_pg_rca24_or16
.subckt pg_fa a=a[17] b=b[17] cin=u_pg_rca24_or16 pg_fa_xor0=u_pg_rca24_pg_fa17_xor0 pg_fa_and0=u_pg_rca24_pg_fa17_and0 pg_fa_xor1=u_pg_rca24_pg_fa17_xor1
.subckt and_gate a=u_pg_rca24_or16 b=u_pg_rca24_pg_fa17_xor0 out=u_pg_rca24_and17
.subckt or_gate a=u_pg_rca24_and17 b=u_pg_rca24_pg_fa17_and0 out=u_pg_rca24_or17
.subckt pg_fa a=a[18] b=b[18] cin=u_pg_rca24_or17 pg_fa_xor0=u_pg_rca24_pg_fa18_xor0 pg_fa_and0=u_pg_rca24_pg_fa18_and0 pg_fa_xor1=u_pg_rca24_pg_fa18_xor1
.subckt and_gate a=u_pg_rca24_or17 b=u_pg_rca24_pg_fa18_xor0 out=u_pg_rca24_and18
.subckt or_gate a=u_pg_rca24_and18 b=u_pg_rca24_pg_fa18_and0 out=u_pg_rca24_or18
.subckt pg_fa a=a[19] b=b[19] cin=u_pg_rca24_or18 pg_fa_xor0=u_pg_rca24_pg_fa19_xor0 pg_fa_and0=u_pg_rca24_pg_fa19_and0 pg_fa_xor1=u_pg_rca24_pg_fa19_xor1
.subckt and_gate a=u_pg_rca24_or18 b=u_pg_rca24_pg_fa19_xor0 out=u_pg_rca24_and19
.subckt or_gate a=u_pg_rca24_and19 b=u_pg_rca24_pg_fa19_and0 out=u_pg_rca24_or19
.subckt pg_fa a=a[20] b=b[20] cin=u_pg_rca24_or19 pg_fa_xor0=u_pg_rca24_pg_fa20_xor0 pg_fa_and0=u_pg_rca24_pg_fa20_and0 pg_fa_xor1=u_pg_rca24_pg_fa20_xor1
.subckt and_gate a=u_pg_rca24_or19 b=u_pg_rca24_pg_fa20_xor0 out=u_pg_rca24_and20
.subckt or_gate a=u_pg_rca24_and20 b=u_pg_rca24_pg_fa20_and0 out=u_pg_rca24_or20
.subckt pg_fa a=a[21] b=b[21] cin=u_pg_rca24_or20 pg_fa_xor0=u_pg_rca24_pg_fa21_xor0 pg_fa_and0=u_pg_rca24_pg_fa21_and0 pg_fa_xor1=u_pg_rca24_pg_fa21_xor1
.subckt and_gate a=u_pg_rca24_or20 b=u_pg_rca24_pg_fa21_xor0 out=u_pg_rca24_and21
.subckt or_gate a=u_pg_rca24_and21 b=u_pg_rca24_pg_fa21_and0 out=u_pg_rca24_or21
.subckt pg_fa a=a[22] b=b[22] cin=u_pg_rca24_or21 pg_fa_xor0=u_pg_rca24_pg_fa22_xor0 pg_fa_and0=u_pg_rca24_pg_fa22_and0 pg_fa_xor1=u_pg_rca24_pg_fa22_xor1
.subckt and_gate a=u_pg_rca24_or21 b=u_pg_rca24_pg_fa22_xor0 out=u_pg_rca24_and22
.subckt or_gate a=u_pg_rca24_and22 b=u_pg_rca24_pg_fa22_and0 out=u_pg_rca24_or22
.subckt pg_fa a=a[23] b=b[23] cin=u_pg_rca24_or22 pg_fa_xor0=u_pg_rca24_pg_fa23_xor0 pg_fa_and0=u_pg_rca24_pg_fa23_and0 pg_fa_xor1=u_pg_rca24_pg_fa23_xor1
.subckt and_gate a=u_pg_rca24_or22 b=u_pg_rca24_pg_fa23_xor0 out=u_pg_rca24_and23
.subckt or_gate a=u_pg_rca24_and23 b=u_pg_rca24_pg_fa23_and0 out=u_pg_rca24_or23
.names u_pg_rca24_pg_fa0_xor0 u_pg_rca24_out[0]
1 1
.names u_pg_rca24_pg_fa1_xor1 u_pg_rca24_out[1]
1 1
.names u_pg_rca24_pg_fa2_xor1 u_pg_rca24_out[2]
1 1
.names u_pg_rca24_pg_fa3_xor1 u_pg_rca24_out[3]
1 1
.names u_pg_rca24_pg_fa4_xor1 u_pg_rca24_out[4]
1 1
.names u_pg_rca24_pg_fa5_xor1 u_pg_rca24_out[5]
1 1
.names u_pg_rca24_pg_fa6_xor1 u_pg_rca24_out[6]
1 1
.names u_pg_rca24_pg_fa7_xor1 u_pg_rca24_out[7]
1 1
.names u_pg_rca24_pg_fa8_xor1 u_pg_rca24_out[8]
1 1
.names u_pg_rca24_pg_fa9_xor1 u_pg_rca24_out[9]
1 1
.names u_pg_rca24_pg_fa10_xor1 u_pg_rca24_out[10]
1 1
.names u_pg_rca24_pg_fa11_xor1 u_pg_rca24_out[11]
1 1
.names u_pg_rca24_pg_fa12_xor1 u_pg_rca24_out[12]
1 1
.names u_pg_rca24_pg_fa13_xor1 u_pg_rca24_out[13]
1 1
.names u_pg_rca24_pg_fa14_xor1 u_pg_rca24_out[14]
1 1
.names u_pg_rca24_pg_fa15_xor1 u_pg_rca24_out[15]
1 1
.names u_pg_rca24_pg_fa16_xor1 u_pg_rca24_out[16]
1 1
.names u_pg_rca24_pg_fa17_xor1 u_pg_rca24_out[17]
1 1
.names u_pg_rca24_pg_fa18_xor1 u_pg_rca24_out[18]
1 1
.names u_pg_rca24_pg_fa19_xor1 u_pg_rca24_out[19]
1 1
.names u_pg_rca24_pg_fa20_xor1 u_pg_rca24_out[20]
1 1
.names u_pg_rca24_pg_fa21_xor1 u_pg_rca24_out[21]
1 1
.names u_pg_rca24_pg_fa22_xor1 u_pg_rca24_out[22]
1 1
.names u_pg_rca24_pg_fa23_xor1 u_pg_rca24_out[23]
1 1
.names u_pg_rca24_or23 u_pg_rca24_out[24]
1 1
.end

.model pg_fa
.inputs a b cin
.outputs pg_fa_xor0 pg_fa_and0 pg_fa_xor1
.names vdd
1
.names gnd
0
.subckt xor_gate a=a b=b out=pg_fa_xor0
.subckt and_gate a=a b=b out=pg_fa_and0
.subckt xor_gate a=pg_fa_xor0 b=cin out=pg_fa_xor1
.end

.model or_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
1- 1
-1 1
.end

.model and_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
11 1
.end

.model xor_gate
.inputs a b
.outputs out
.names vdd
1
.names gnd
0
.names a b out
01 1
10 1
.end